1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 78 unchanged lines hidden (view full) ---

87 op = " -"
88
89 offset = op + " imm"
90 eaCode = "EA = Base"
91 if not post:
92 eaCode += offset
93 eaCode += ";"
94
95 memFlags = ["ArmISA::TLB::MustBeOne", "%d" % (size - 1)]
96 if prefetch:
97 Name = "%s_%s" % (mnem.upper(), Name)
98 memFlags.append("Request::PREFETCH")
99 accCode = '''
100 uint64_t temp = Mem%s;\n
101 temp = temp;
102 ''' % buildMemSuffix(sign, size)
103 else:
104 if ldrex:
105 memFlags.append("Request::LLSC")
106 Name = "%s_%s" % (mnem.upper(), Name)
107 accCode = "IWDest = Mem%s;\n" % buildMemSuffix(sign, size)
108
109 if not prefetch and not ldrex:
110 memFlags.append("ArmISA::TLB::AllowUnaligned")
111
112 if writeback:
113 accCode += "Base = Base %s;\n" % offset
114 base = buildMemBase("MemoryImm", post, writeback)
115
116 emitLoad(name, Name, True, eaCode, accCode, memFlags, [], base)
117
118 def buildRfeLoad(mnem, post, add, writeback):
119 name = mnem

--- 20 unchanged lines hidden (view full) ---

140 '''
141 if writeback:
142 accCode += "Base = Base + %s;\n" % wbDiff
143
144 global header_output, decoder_output, exec_output
145
146 (newHeader,
147 newDecoder,
148 newExec) = RfeBase(name, Name, eaCode, accCode,
149 ["ArmISA::TLB::AlignWord", "ArmISA::TLB::MustBeOne"], [])
150
151 header_output += newHeader
152 decoder_output += newDecoder
153 exec_output += newExec
154
155 def buildRegLoad(mnem, post, add, writeback, \
156 size=4, sign=False, user=False, prefetch=False):
157 name = mnem

--- 7 unchanged lines hidden (view full) ---

165
166 offset = op + " shift_rm_imm(Index, shiftAmt," + \
167 " shiftType, CondCodes<29:>)"
168 eaCode = "EA = Base"
169 if not post:
170 eaCode += offset
171 eaCode += ";"
172
173 memFlags = ["%d" % (size - 1), "ArmISA::TLB::MustBeOne"]
174 if prefetch:
175 Name = "%s_%s" % (mnem.upper(), Name)
176 memFlags.append("Request::PREFETCH")
177 accCode = '''
178 uint64_t temp = Mem%s;\n
179 temp = temp;
180 ''' % buildMemSuffix(sign, size)
181 else:
182 accCode = "IWDest = Mem%s;\n" % buildMemSuffix(sign, size)
183 if writeback:
184 accCode += "Base = Base %s;\n" % offset
185
186 if not prefetch:
187 memFlags.append("ArmISA::TLB::AllowUnaligned")
188
189 base = buildMemBase("MemoryReg", post, writeback)
190
191 emitLoad(name, Name, False, eaCode, accCode, \
192 memFlags, [], base)
193
194 def buildDoubleImmLoad(mnem, post, add, writeback, ldrex=False):
195 name = mnem
196 Name = loadDoubleImmClassName(post, add, writeback)

--- 17 unchanged lines hidden (view full) ---

214 memFlags = ["Request::LLSC"]
215 Name = "%s_%s" % (mnem.upper(), Name)
216 else:
217 memFlags = []
218 if writeback:
219 accCode += "Base = Base %s;\n" % offset
220 base = buildMemBase("MemoryDImm", post, writeback)
221
222 memFlags.extend(["ArmISA::TLB::MustBeOne",
223 "ArmISA::TLB::AlignWord"])
224
225 emitLoad(name, Name, True, eaCode, accCode, \
226 memFlags, [], base, double=True)
227
228 def buildDoubleRegLoad(mnem, post, add, writeback):
229 name = mnem
230 Name = loadDoubleRegClassName(post, add, writeback)
231
232 if add:

--- 12 unchanged lines hidden (view full) ---

245 Dest = bits(Mem.ud, 31, 0);
246 Dest2 = bits(Mem.ud, 63, 32);
247 '''
248 if writeback:
249 accCode += "Base = Base %s;\n" % offset
250 base = buildMemBase("MemoryDReg", post, writeback)
251
252 emitLoad(name, Name, False, eaCode, accCode,
253 ["ArmISA::TLB::MustBeOne", "ArmISA::TLB::AlignWord"],
254 [], base, double=True)
255
256 def buildLoads(mnem, size=4, sign=False, user=False):
257 buildImmLoad(mnem, True, True, True, size, sign, user)
258 buildRegLoad(mnem, True, True, True, size, sign, user)
259 buildImmLoad(mnem, True, False, True, size, sign, user)
260 buildRegLoad(mnem, True, False, True, size, sign, user)
261 buildImmLoad(mnem, False, True, True, size, sign, user)
262 buildRegLoad(mnem, False, True, True, size, sign, user)

--- 61 unchanged lines hidden ---