1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 60 unchanged lines hidden (view full) ---

69 memFlags, instFlags,
70 base, execTemplateBase = 'Load')
71
72 header_output += newHeader
73 decoder_output += newDecoder
74 exec_output += newExec
75
76 def buildImmLoad(mnem, post, add, writeback, \
77 size=4, sign=False, user=False, prefetch=False):
78 name = mnem
79 Name = loadImmClassName(post, add, writeback, \
80 size, sign, user)
81
82 if add:
83 op = " +"
84 else:
85 op = " -"
86
87 offset = op + " imm"
88 eaCode = "EA = Base"
89 if not post:
90 eaCode += offset
91 eaCode += ";"
92
93 if prefetch:
94 Name = "%s_%s" % (mnem.upper(), Name)
95 memFlags = ["Request::PREFETCH"]
96 accCode = '''
97 uint64_t temp = Mem%s;\n
98 temp = temp;
99 ''' % buildMemSuffix(sign, size)
100 else:
101 memFlags = []
102 accCode = "IWDest = Mem%s;\n" % buildMemSuffix(sign, size)
103 if writeback:
104 accCode += "Base = Base %s;\n" % offset
105 base = buildMemBase("MemoryImm", post, writeback)
106
107 emitLoad(name, Name, True, eaCode, accCode, memFlags, [], base)
108
109 def buildRegLoad(mnem, post, add, writeback, \
110 size=4, sign=False, user=False, prefetch=False):
111 name = mnem
112 Name = loadRegClassName(post, add, writeback,
113 size, sign, user)
114
115 if add:
116 op = " +"
117 else:
118 op = " -"
119
120 offset = op + " shift_rm_imm(Index, shiftAmt," + \
121 " shiftType, CondCodes<29:>)"
122 eaCode = "EA = Base"
123 if not post:
124 eaCode += offset
125 eaCode += ";"
126
127 if prefetch:
128 Name = "%s_%s" % (mnem.upper(), Name)
129 memFlags = ["Request::PREFETCH"]
130 accCode = '''
131 uint64_t temp = Mem%s;\n
132 temp = temp;
133 ''' % buildMemSuffix(sign, size)
134 else:
135 memFlags = []
136 accCode = "IWDest = Mem%s;\n" % buildMemSuffix(sign, size)
137 if writeback:
138 accCode += "Base = Base %s;\n" % offset
139 base = buildMemBase("MemoryReg", post, writeback)
140
141 emitLoad(name, Name, False, eaCode, accCode, memFlags, [], base)
142
143 def buildDoubleImmLoad(mnem, post, add, writeback):
144 name = mnem
145 Name = loadDoubleImmClassName(post, add, writeback)
146
147 if add:
148 op = " +"
149 else:

--- 64 unchanged lines hidden (view full) ---

214 buildDoubleRegLoad(mnem, False, True, True)
215 buildDoubleImmLoad(mnem, False, False, True)
216 buildDoubleRegLoad(mnem, False, False, True)
217 buildDoubleImmLoad(mnem, False, True, False)
218 buildDoubleRegLoad(mnem, False, True, False)
219 buildDoubleImmLoad(mnem, False, False, False)
220 buildDoubleRegLoad(mnem, False, False, False)
221
222 def buildPrefetches(mnem):
223 buildRegLoad(mnem, False, False, False, size=1, prefetch=True)
224 buildImmLoad(mnem, False, False, False, size=1, prefetch=True)
225 buildRegLoad(mnem, False, True, False, size=1, prefetch=True)
226 buildImmLoad(mnem, False, True, False, size=1, prefetch=True)
227
228 buildLoads("ldr")
229 buildLoads("ldrt", user=True)
230 buildLoads("ldrb", size=1)
231 buildLoads("ldrbt", size=1, user=True)
232 buildLoads("ldrsb", size=1, sign=True)
233 buildLoads("ldrsbt", size=1, sign=True, user=True)
234 buildLoads("ldrh", size=2)
235 buildLoads("ldrht", size=2, user=True)
236 buildLoads("hdrsh", size=2, sign=True)
237 buildLoads("ldrsht", size=2, sign=True, user=True)
238
239 buildDoubleLoads("ldrd")
240
241 buildPrefetches("pld")
242 buildPrefetches("pldw")
243 buildPrefetches("pli")
244}};