fp64.isa (11683:f1e198a028be) fp64.isa (12110:c24ee249b8ba)
1// -*- mode:c++ -*-
2
1// -*- mode:c++ -*-
2
3// Copyright (c) 2012-2013 ARM Limited
3// Copyright (c) 2012-2013, 2016 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder. You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated

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118 fmovCoreRegXIop = InstObjParams("fmov", "FmovCoreRegX", "FpRegRegOp",
119 { "code": fmovCoreRegXCode,
120 "op_class": "FloatMiscOp" }, [])
121 header_output += FpRegRegOpDeclare.subst(fmovCoreRegXIop);
122 decoder_output += AA64FpRegRegOpConstructor.subst(fmovCoreRegXIop);
123 exec_output += BasicExecute.subst(fmovCoreRegXIop);
124
125 fmovUCoreRegXCode = vfp64EnabledCheckCode + '''
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder. You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated

--- 106 unchanged lines hidden (view full) ---

118 fmovCoreRegXIop = InstObjParams("fmov", "FmovCoreRegX", "FpRegRegOp",
119 { "code": fmovCoreRegXCode,
120 "op_class": "FloatMiscOp" }, [])
121 header_output += FpRegRegOpDeclare.subst(fmovCoreRegXIop);
122 decoder_output += AA64FpRegRegOpConstructor.subst(fmovCoreRegXIop);
123 exec_output += BasicExecute.subst(fmovCoreRegXIop);
124
125 fmovUCoreRegXCode = vfp64EnabledCheckCode + '''
126 /* Explicitly merge with previous value */
127 AA64FpDestP0_uw = AA64FpDestP0_uw;
128 AA64FpDestP1_uw = AA64FpDestP1_uw;
126 AA64FpDestP2_uw = XOp1_ud;
129 AA64FpDestP2_uw = XOp1_ud;
127 AA64FpDestP3_uw = XOp1_ud >> 32;
128 '''
130 AA64FpDestP3_uw = XOp1_ud >> 32;'''
129 fmovUCoreRegXIop = InstObjParams("fmov", "FmovUCoreRegX", "FpRegRegOp",
130 { "code": fmovUCoreRegXCode,
131 "op_class": "FloatMiscOp" }, [])
132 header_output += FpRegRegOpDeclare.subst(fmovUCoreRegXIop);
133 decoder_output += AA64FpRegRegOpConstructor.subst(fmovUCoreRegXIop);
134 exec_output += BasicExecute.subst(fmovUCoreRegXIop);
135
136 fmovRegCoreWCode = vfp64EnabledCheckCode + '''

--- 676 unchanged lines hidden --- 		131 fmovUCoreRegXIop = InstObjParams("fmov", "FmovUCoreRegX", "FpRegRegOp",
132 { "code": fmovUCoreRegXCode,
133 "op_class": "FloatMiscOp" }, [])
134 header_output += FpRegRegOpDeclare.subst(fmovUCoreRegXIop);
135 decoder_output += AA64FpRegRegOpConstructor.subst(fmovUCoreRegXIop);
136 exec_output += BasicExecute.subst(fmovUCoreRegXIop);
137
138 fmovRegCoreWCode = vfp64EnabledCheckCode + '''

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