55c55
< "op_class": "SimdFloatMiscOp" }, [])
---
> "op_class": "FloatMiscOp" }, [])
68c68
< "op_class": "SimdFloatMiscOp" }, [])
---
> "op_class": "FloatMiscOp" }, [])
81c81
< "op_class": "SimdFloatMiscOp" }, [])
---
> "op_class": "FloatMiscOp" }, [])
94c94
< "op_class": "SimdFloatMiscOp" }, [])
---
> "op_class": "FloatMiscOp" }, [])
107c107
< "op_class": "SimdFloatMiscOp" }, [])
---
> "op_class": "FloatMiscOp" }, [])
120c120
< "op_class": "SimdFloatMiscOp" }, [])
---
> "op_class": "FloatMiscOp" }, [])
131c131
< "op_class": "SimdFloatMiscOp" }, [])
---
> "op_class": "FloatMiscOp" }, [])
141c141
< "op_class": "SimdFloatMiscOp" }, [])
---
> "op_class": "FloatMiscOp" }, [])
151c151
< "op_class": "SimdFloatMiscOp" }, [])
---
> "op_class": "FloatMiscOp" }, [])
161c161
< "op_class": "SimdFloatMiscOp" }, [])
---
> "op_class": "FloatMiscOp" }, [])
273c273
< buildTernaryFpOp("FMAdd", "SimdFloatMultAccOp",
---
> buildTernaryFpOp("FMAdd", "FloatMultAccOp",
276c276
< buildTernaryFpOp("FMSub", "SimdFloatMultAccOp",
---
> buildTernaryFpOp("FMSub", "FloatMultAccOp",
279c279
< buildTernaryFpOp("FNMAdd", "SimdFloatMultAccOp",
---
> buildTernaryFpOp("FNMAdd", "FloatMultAccOp",
282c282
< buildTernaryFpOp("FNMSub", "SimdFloatMultAccOp",
---
> buildTernaryFpOp("FNMSub", "FloatMultAccOp",
307c307
< buildBinFpOp("fadd", "FAdd", "FpRegRegRegOp", "SimdFloatAddOp",
---
> buildBinFpOp("fadd", "FAdd", "FpRegRegRegOp", "FloatAddOp",
310c310
< buildBinFpOp("fsub", "FSub", "FpRegRegRegOp", "SimdFloatAddOp",
---
> buildBinFpOp("fsub", "FSub", "FpRegRegRegOp", "FloatAddOp",
313c313
< buildBinFpOp("fdiv", "FDiv", "FpRegRegRegOp", "SimdFloatDivOp",
---
> buildBinFpOp("fdiv", "FDiv", "FpRegRegRegOp", "FloatDivOp",
316c316
< buildBinFpOp("fmul", "FMul", "FpRegRegRegOp", "SimdFloatMultOp",
---
> buildBinFpOp("fmul", "FMul", "FpRegRegRegOp", "FloatMultOp",
319c319
< buildBinFpOp("fnmul", "FNMul", "FpRegRegRegOp", "SimdFloatMultOp",
---
> buildBinFpOp("fnmul", "FNMul", "FpRegRegRegOp", "FloatMultOp",
322c322
< buildBinFpOp("fmin", "FMin", "FpRegRegRegOp", "SimdFloatCmpOp",
---
> buildBinFpOp("fmin", "FMin", "FpRegRegRegOp", "FloatCmpOp",
325c325
< buildBinFpOp("fmax", "FMax", "FpRegRegRegOp", "SimdFloatCmpOp",
---
> buildBinFpOp("fmax", "FMax", "FpRegRegRegOp", "FloatCmpOp",
328c328
< buildBinFpOp("fminnm", "FMinNM", "FpRegRegRegOp", "SimdFloatCmpOp",
---
> buildBinFpOp("fminnm", "FMinNM", "FpRegRegRegOp", "FloatCmpOp",
331c331
< buildBinFpOp("fmaxnm", "FMaxNM", "FpRegRegRegOp", "SimdFloatCmpOp",
---
> buildBinFpOp("fmaxnm", "FMaxNM", "FpRegRegRegOp", "FloatCmpOp",
357c357
< buildUnaryFpOp("fsqrt", "FSqrt", "FpRegRegOp", "SimdFloatSqrtOp",
---
> buildUnaryFpOp("fsqrt", "FSqrt", "FpRegRegOp", "FloatSqrtOp",
386c386
< buildSimpleUnaryFpOp("fneg", "FNeg", "FpRegRegOp", "SimdFloatMiscOp",
---
> buildSimpleUnaryFpOp("fneg", "FNeg", "FpRegRegOp", "FloatMiscOp",
388c388
< buildSimpleUnaryFpOp("fabs", "FAbs", "FpRegRegOp", "SimdFloatMiscOp",
---
> buildSimpleUnaryFpOp("fabs", "FAbs", "FpRegRegOp", "FloatMiscOp",
390c390
< buildSimpleUnaryFpOp("frintn", "FRIntN", "FpRegRegOp", "SimdFloatMiscOp",
---
> buildSimpleUnaryFpOp("frintn", "FRIntN", "FpRegRegOp", "FloatMiscOp",
393c393
< buildSimpleUnaryFpOp("frintp", "FRIntP", "FpRegRegOp", "SimdFloatMiscOp",
---
> buildSimpleUnaryFpOp("frintp", "FRIntP", "FpRegRegOp", "FloatMiscOp",
396c396
< buildSimpleUnaryFpOp("frintm", "FRIntM", "FpRegRegOp", "SimdFloatMiscOp",
---
> buildSimpleUnaryFpOp("frintm", "FRIntM", "FpRegRegOp", "FloatMiscOp",
399c399
< buildSimpleUnaryFpOp("frintz", "FRIntZ", "FpRegRegOp", "SimdFloatMiscOp",
---
> buildSimpleUnaryFpOp("frintz", "FRIntZ", "FpRegRegOp", "FloatMiscOp",
402c402
< buildSimpleUnaryFpOp("frinta", "FRIntA", "FpRegRegOp", "SimdFloatMiscOp",
---
> buildSimpleUnaryFpOp("frinta", "FRIntA", "FpRegRegOp", "FloatMiscOp",
405c405
< buildSimpleUnaryFpOp("frinti", "FRIntI", "FpRegRegOp", "SimdFloatMiscOp",
---
> buildSimpleUnaryFpOp("frinti", "FRIntI", "FpRegRegOp", "FloatMiscOp",
408c408
< buildSimpleUnaryFpOp("frintx", "FRIntX", "FpRegRegOp", "SimdFloatMiscOp",
---
> buildSimpleUnaryFpOp("frintx", "FRIntX", "FpRegRegOp", "FloatMiscOp",
454,455c454,455
< { "code": fcvtIntFpDCode,
< "op_class": "SimdFloatCvtOp" }, [])
---
> { "code": fcvtIntFpDCode,
> "op_class": "FloatCvtOp" }, [])
494c494
< "op_class": "SimdFloatCvtOp" }, [])
---
> "op_class": "FloatCvtOp" }, [])
517c517
< "op_class": "SimdFloatCvtOp" }, [])
---
> "op_class": "FloatCvtOp" }, [])
534c534
< "op_class": "SimdFloatCvtOp" }, [])
---
> "op_class": "FloatCvtOp" }, [])
566c566
< "op_class": "SimdFloatCvtOp" }, [])
---
> "op_class": "FloatCvtOp" }, [])
589c589
< "op_class": "SimdFloatCvtOp" }, [])
---
> "op_class": "FloatCvtOp" }, [])
629c629
< "op_class": "SimdFloatCmpOp"}, [])
---
> "op_class": "FloatCmpOp"}, [])
676c676
< "op_class": "SimdFloatCmpOp"}, [])
---
> "op_class": "FloatCmpOp"}, [])
721c721
< "op_class": "SimdFloatCvtOp" }, [])
---
> "op_class": "FloatCvtOp" }, [])
762c762
< "op_class": "SimdFloatCvtOp" }, [])
---
> "op_class": "FloatCvtOp" }, [])
807c807,808
< "FpCondSelOp", code)
---
> "FpCondSelOp", { "code": code,
> "op_class": "FloatCvtOp" })