fp64.isa (10037:5cac77888310) | fp64.isa (11683:f1e198a028be) |
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1// -*- mode:c++ -*- 2 3// Copyright (c) 2012-2013 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating --- 38 unchanged lines hidden (view full) --- 47 fmovImmSCode = vfp64EnabledCheckCode + ''' 48 AA64FpDestP0_uw = bits(imm, 31, 0); 49 AA64FpDestP1_uw = 0; 50 AA64FpDestP2_uw = 0; 51 AA64FpDestP3_uw = 0; 52 ''' 53 fmovImmSIop = InstObjParams("fmov", "FmovImmS", "FpRegImmOp", 54 { "code": fmovImmSCode, | 1// -*- mode:c++ -*- 2 3// Copyright (c) 2012-2013 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating --- 38 unchanged lines hidden (view full) --- 47 fmovImmSCode = vfp64EnabledCheckCode + ''' 48 AA64FpDestP0_uw = bits(imm, 31, 0); 49 AA64FpDestP1_uw = 0; 50 AA64FpDestP2_uw = 0; 51 AA64FpDestP3_uw = 0; 52 ''' 53 fmovImmSIop = InstObjParams("fmov", "FmovImmS", "FpRegImmOp", 54 { "code": fmovImmSCode, |
55 "op_class": "SimdFloatMiscOp" }, []) | 55 "op_class": "FloatMiscOp" }, []) |
56 header_output += FpRegImmOpDeclare.subst(fmovImmSIop); 57 decoder_output += FpRegImmOpConstructor.subst(fmovImmSIop); 58 exec_output += BasicExecute.subst(fmovImmSIop); 59 60 fmovImmDCode = vfp64EnabledCheckCode + ''' 61 AA64FpDestP0_uw = bits(imm, 31, 0); 62 AA64FpDestP1_uw = bits(imm, 63, 32); 63 AA64FpDestP2_uw = 0; 64 AA64FpDestP3_uw = 0; 65 ''' 66 fmovImmDIop = InstObjParams("fmov", "FmovImmD", "FpRegImmOp", 67 { "code": fmovImmDCode, | 56 header_output += FpRegImmOpDeclare.subst(fmovImmSIop); 57 decoder_output += FpRegImmOpConstructor.subst(fmovImmSIop); 58 exec_output += BasicExecute.subst(fmovImmSIop); 59 60 fmovImmDCode = vfp64EnabledCheckCode + ''' 61 AA64FpDestP0_uw = bits(imm, 31, 0); 62 AA64FpDestP1_uw = bits(imm, 63, 32); 63 AA64FpDestP2_uw = 0; 64 AA64FpDestP3_uw = 0; 65 ''' 66 fmovImmDIop = InstObjParams("fmov", "FmovImmD", "FpRegImmOp", 67 { "code": fmovImmDCode, |
68 "op_class": "SimdFloatMiscOp" }, []) | 68 "op_class": "FloatMiscOp" }, []) |
69 header_output += FpRegImmOpDeclare.subst(fmovImmDIop); 70 decoder_output += AA64FpRegImmOpConstructor.subst(fmovImmDIop); 71 exec_output += BasicExecute.subst(fmovImmDIop); 72 73 fmovRegSCode = vfp64EnabledCheckCode + ''' 74 AA64FpDestP0_uw = AA64FpOp1P0_uw; 75 AA64FpDestP1_uw = 0; 76 AA64FpDestP2_uw = 0; 77 AA64FpDestP3_uw = 0; 78 ''' 79 fmovRegSIop = InstObjParams("fmov", "FmovRegS", "FpRegRegOp", 80 { "code": fmovRegSCode, | 69 header_output += FpRegImmOpDeclare.subst(fmovImmDIop); 70 decoder_output += AA64FpRegImmOpConstructor.subst(fmovImmDIop); 71 exec_output += BasicExecute.subst(fmovImmDIop); 72 73 fmovRegSCode = vfp64EnabledCheckCode + ''' 74 AA64FpDestP0_uw = AA64FpOp1P0_uw; 75 AA64FpDestP1_uw = 0; 76 AA64FpDestP2_uw = 0; 77 AA64FpDestP3_uw = 0; 78 ''' 79 fmovRegSIop = InstObjParams("fmov", "FmovRegS", "FpRegRegOp", 80 { "code": fmovRegSCode, |
81 "op_class": "SimdFloatMiscOp" }, []) | 81 "op_class": "FloatMiscOp" }, []) |
82 header_output += FpRegRegOpDeclare.subst(fmovRegSIop); 83 decoder_output += AA64FpRegRegOpConstructor.subst(fmovRegSIop); 84 exec_output += BasicExecute.subst(fmovRegSIop); 85 86 fmovRegDCode = vfp64EnabledCheckCode + ''' 87 AA64FpDestP0_uw = AA64FpOp1P0_uw; 88 AA64FpDestP1_uw = AA64FpOp1P1_uw; 89 AA64FpDestP2_uw = 0; 90 AA64FpDestP3_uw = 0; 91 ''' 92 fmovRegDIop = InstObjParams("fmov", "FmovRegD", "FpRegRegOp", 93 { "code": fmovRegDCode, | 82 header_output += FpRegRegOpDeclare.subst(fmovRegSIop); 83 decoder_output += AA64FpRegRegOpConstructor.subst(fmovRegSIop); 84 exec_output += BasicExecute.subst(fmovRegSIop); 85 86 fmovRegDCode = vfp64EnabledCheckCode + ''' 87 AA64FpDestP0_uw = AA64FpOp1P0_uw; 88 AA64FpDestP1_uw = AA64FpOp1P1_uw; 89 AA64FpDestP2_uw = 0; 90 AA64FpDestP3_uw = 0; 91 ''' 92 fmovRegDIop = InstObjParams("fmov", "FmovRegD", "FpRegRegOp", 93 { "code": fmovRegDCode, |
94 "op_class": "SimdFloatMiscOp" }, []) | 94 "op_class": "FloatMiscOp" }, []) |
95 header_output += FpRegRegOpDeclare.subst(fmovRegDIop); 96 decoder_output += AA64FpRegRegOpConstructor.subst(fmovRegDIop); 97 exec_output += BasicExecute.subst(fmovRegDIop); 98 99 fmovCoreRegWCode = vfp64EnabledCheckCode + ''' 100 AA64FpDestP0_uw = WOp1_uw; 101 AA64FpDestP1_uw = 0; 102 AA64FpDestP2_uw = 0; 103 AA64FpDestP3_uw = 0; 104 ''' 105 fmovCoreRegWIop = InstObjParams("fmov", "FmovCoreRegW", "FpRegRegOp", 106 { "code": fmovCoreRegWCode, | 95 header_output += FpRegRegOpDeclare.subst(fmovRegDIop); 96 decoder_output += AA64FpRegRegOpConstructor.subst(fmovRegDIop); 97 exec_output += BasicExecute.subst(fmovRegDIop); 98 99 fmovCoreRegWCode = vfp64EnabledCheckCode + ''' 100 AA64FpDestP0_uw = WOp1_uw; 101 AA64FpDestP1_uw = 0; 102 AA64FpDestP2_uw = 0; 103 AA64FpDestP3_uw = 0; 104 ''' 105 fmovCoreRegWIop = InstObjParams("fmov", "FmovCoreRegW", "FpRegRegOp", 106 { "code": fmovCoreRegWCode, |
107 "op_class": "SimdFloatMiscOp" }, []) | 107 "op_class": "FloatMiscOp" }, []) |
108 header_output += FpRegRegOpDeclare.subst(fmovCoreRegWIop); 109 decoder_output += AA64FpRegRegOpConstructor.subst(fmovCoreRegWIop); 110 exec_output += BasicExecute.subst(fmovCoreRegWIop); 111 112 fmovCoreRegXCode = vfp64EnabledCheckCode + ''' 113 AA64FpDestP0_uw = XOp1_ud; 114 AA64FpDestP1_uw = XOp1_ud >> 32; 115 AA64FpDestP2_uw = 0; 116 AA64FpDestP3_uw = 0; 117 ''' 118 fmovCoreRegXIop = InstObjParams("fmov", "FmovCoreRegX", "FpRegRegOp", 119 { "code": fmovCoreRegXCode, | 108 header_output += FpRegRegOpDeclare.subst(fmovCoreRegWIop); 109 decoder_output += AA64FpRegRegOpConstructor.subst(fmovCoreRegWIop); 110 exec_output += BasicExecute.subst(fmovCoreRegWIop); 111 112 fmovCoreRegXCode = vfp64EnabledCheckCode + ''' 113 AA64FpDestP0_uw = XOp1_ud; 114 AA64FpDestP1_uw = XOp1_ud >> 32; 115 AA64FpDestP2_uw = 0; 116 AA64FpDestP3_uw = 0; 117 ''' 118 fmovCoreRegXIop = InstObjParams("fmov", "FmovCoreRegX", "FpRegRegOp", 119 { "code": fmovCoreRegXCode, |
120 "op_class": "SimdFloatMiscOp" }, []) | 120 "op_class": "FloatMiscOp" }, []) |
121 header_output += FpRegRegOpDeclare.subst(fmovCoreRegXIop); 122 decoder_output += AA64FpRegRegOpConstructor.subst(fmovCoreRegXIop); 123 exec_output += BasicExecute.subst(fmovCoreRegXIop); 124 125 fmovUCoreRegXCode = vfp64EnabledCheckCode + ''' 126 AA64FpDestP2_uw = XOp1_ud; 127 AA64FpDestP3_uw = XOp1_ud >> 32; 128 ''' 129 fmovUCoreRegXIop = InstObjParams("fmov", "FmovUCoreRegX", "FpRegRegOp", 130 { "code": fmovUCoreRegXCode, | 121 header_output += FpRegRegOpDeclare.subst(fmovCoreRegXIop); 122 decoder_output += AA64FpRegRegOpConstructor.subst(fmovCoreRegXIop); 123 exec_output += BasicExecute.subst(fmovCoreRegXIop); 124 125 fmovUCoreRegXCode = vfp64EnabledCheckCode + ''' 126 AA64FpDestP2_uw = XOp1_ud; 127 AA64FpDestP3_uw = XOp1_ud >> 32; 128 ''' 129 fmovUCoreRegXIop = InstObjParams("fmov", "FmovUCoreRegX", "FpRegRegOp", 130 { "code": fmovUCoreRegXCode, |
131 "op_class": "SimdFloatMiscOp" }, []) | 131 "op_class": "FloatMiscOp" }, []) |
132 header_output += FpRegRegOpDeclare.subst(fmovUCoreRegXIop); 133 decoder_output += AA64FpRegRegOpConstructor.subst(fmovUCoreRegXIop); 134 exec_output += BasicExecute.subst(fmovUCoreRegXIop); 135 136 fmovRegCoreWCode = vfp64EnabledCheckCode + ''' 137 WDest = AA64FpOp1P0_uw; 138 ''' 139 fmovRegCoreWIop = InstObjParams("fmov", "FmovRegCoreW", "FpRegRegOp", 140 { "code": fmovRegCoreWCode, | 132 header_output += FpRegRegOpDeclare.subst(fmovUCoreRegXIop); 133 decoder_output += AA64FpRegRegOpConstructor.subst(fmovUCoreRegXIop); 134 exec_output += BasicExecute.subst(fmovUCoreRegXIop); 135 136 fmovRegCoreWCode = vfp64EnabledCheckCode + ''' 137 WDest = AA64FpOp1P0_uw; 138 ''' 139 fmovRegCoreWIop = InstObjParams("fmov", "FmovRegCoreW", "FpRegRegOp", 140 { "code": fmovRegCoreWCode, |
141 "op_class": "SimdFloatMiscOp" }, []) | 141 "op_class": "FloatMiscOp" }, []) |
142 header_output += FpRegRegOpDeclare.subst(fmovRegCoreWIop); 143 decoder_output += AA64FpRegRegOpConstructor.subst(fmovRegCoreWIop); 144 exec_output += BasicExecute.subst(fmovRegCoreWIop); 145 146 fmovRegCoreXCode = vfp64EnabledCheckCode + ''' 147 XDest = ( ((uint64_t) AA64FpOp1P1_uw) << 32) | AA64FpOp1P0_uw; 148 ''' 149 fmovRegCoreXIop = InstObjParams("fmov", "FmovRegCoreX", "FpRegRegOp", 150 { "code": fmovRegCoreXCode, | 142 header_output += FpRegRegOpDeclare.subst(fmovRegCoreWIop); 143 decoder_output += AA64FpRegRegOpConstructor.subst(fmovRegCoreWIop); 144 exec_output += BasicExecute.subst(fmovRegCoreWIop); 145 146 fmovRegCoreXCode = vfp64EnabledCheckCode + ''' 147 XDest = ( ((uint64_t) AA64FpOp1P1_uw) << 32) | AA64FpOp1P0_uw; 148 ''' 149 fmovRegCoreXIop = InstObjParams("fmov", "FmovRegCoreX", "FpRegRegOp", 150 { "code": fmovRegCoreXCode, |
151 "op_class": "SimdFloatMiscOp" }, []) | 151 "op_class": "FloatMiscOp" }, []) |
152 header_output += FpRegRegOpDeclare.subst(fmovRegCoreXIop); 153 decoder_output += AA64FpRegRegOpConstructor.subst(fmovRegCoreXIop); 154 exec_output += BasicExecute.subst(fmovRegCoreXIop); 155 156 fmovURegCoreXCode = vfp64EnabledCheckCode + ''' 157 XDest = ( ((uint64_t) AA64FpOp1P3_uw) << 32) | AA64FpOp1P2_uw; 158 ''' 159 fmovURegCoreXIop = InstObjParams("fmov", "FmovURegCoreX", "FpRegRegOp", 160 { "code": fmovURegCoreXCode, | 152 header_output += FpRegRegOpDeclare.subst(fmovRegCoreXIop); 153 decoder_output += AA64FpRegRegOpConstructor.subst(fmovRegCoreXIop); 154 exec_output += BasicExecute.subst(fmovRegCoreXIop); 155 156 fmovURegCoreXCode = vfp64EnabledCheckCode + ''' 157 XDest = ( ((uint64_t) AA64FpOp1P3_uw) << 32) | AA64FpOp1P2_uw; 158 ''' 159 fmovURegCoreXIop = InstObjParams("fmov", "FmovURegCoreX", "FpRegRegOp", 160 { "code": fmovURegCoreXCode, |
161 "op_class": "SimdFloatMiscOp" }, []) | 161 "op_class": "FloatMiscOp" }, []) |
162 header_output += FpRegRegOpDeclare.subst(fmovURegCoreXIop); 163 decoder_output += AA64FpRegRegOpConstructor.subst(fmovURegCoreXIop); 164 exec_output += BasicExecute.subst(fmovURegCoreXIop); 165}}; 166 167let {{ 168 169 header_output = "" --- 95 unchanged lines hidden (view full) --- 265 iop = InstObjParams(name.lower(), name + ("D" if isDouble else "S"), 266 "FpRegRegRegRegOp", 267 { "code": code, "op_class": opClass }, []) 268 269 header_output += AA64FpRegRegRegRegOpDeclare.subst(iop) 270 decoder_output += AA64FpRegRegRegRegOpConstructor.subst(iop) 271 exec_output += BasicExecute.subst(iop) 272 | 162 header_output += FpRegRegOpDeclare.subst(fmovURegCoreXIop); 163 decoder_output += AA64FpRegRegOpConstructor.subst(fmovURegCoreXIop); 164 exec_output += BasicExecute.subst(fmovURegCoreXIop); 165}}; 166 167let {{ 168 169 header_output = "" --- 95 unchanged lines hidden (view full) --- 265 iop = InstObjParams(name.lower(), name + ("D" if isDouble else "S"), 266 "FpRegRegRegRegOp", 267 { "code": code, "op_class": opClass }, []) 268 269 header_output += AA64FpRegRegRegRegOpDeclare.subst(iop) 270 decoder_output += AA64FpRegRegRegRegOpConstructor.subst(iop) 271 exec_output += BasicExecute.subst(iop) 272 |
273 buildTernaryFpOp("FMAdd", "SimdFloatMultAccOp", | 273 buildTernaryFpOp("FMAdd", "FloatMultAccOp", |
274 "fplibMulAdd<uint32_t>(cOp3, cOp1, cOp2, fpscr)", 275 "fplibMulAdd<uint64_t>(cOp3, cOp1, cOp2, fpscr)" ) | 274 "fplibMulAdd<uint32_t>(cOp3, cOp1, cOp2, fpscr)", 275 "fplibMulAdd<uint64_t>(cOp3, cOp1, cOp2, fpscr)" ) |
276 buildTernaryFpOp("FMSub", "SimdFloatMultAccOp", | 276 buildTernaryFpOp("FMSub", "FloatMultAccOp", |
277 "fplibMulAdd<uint32_t>(cOp3, fplibNeg<uint32_t>(cOp1), cOp2, fpscr)", 278 "fplibMulAdd<uint64_t>(cOp3, fplibNeg<uint64_t>(cOp1), cOp2, fpscr)" ) | 277 "fplibMulAdd<uint32_t>(cOp3, fplibNeg<uint32_t>(cOp1), cOp2, fpscr)", 278 "fplibMulAdd<uint64_t>(cOp3, fplibNeg<uint64_t>(cOp1), cOp2, fpscr)" ) |
279 buildTernaryFpOp("FNMAdd", "SimdFloatMultAccOp", | 279 buildTernaryFpOp("FNMAdd", "FloatMultAccOp", |
280 "fplibMulAdd<uint32_t>(fplibNeg<uint32_t>(cOp3), fplibNeg<uint32_t>(cOp1), cOp2, fpscr)", 281 "fplibMulAdd<uint64_t>(fplibNeg<uint64_t>(cOp3), fplibNeg<uint64_t>(cOp1), cOp2, fpscr)" ) | 280 "fplibMulAdd<uint32_t>(fplibNeg<uint32_t>(cOp3), fplibNeg<uint32_t>(cOp1), cOp2, fpscr)", 281 "fplibMulAdd<uint64_t>(fplibNeg<uint64_t>(cOp3), fplibNeg<uint64_t>(cOp1), cOp2, fpscr)" ) |
282 buildTernaryFpOp("FNMSub", "SimdFloatMultAccOp", | 282 buildTernaryFpOp("FNMSub", "FloatMultAccOp", |
283 "fplibMulAdd<uint32_t>(fplibNeg<uint32_t>(cOp3), cOp1, cOp2, fpscr)", 284 "fplibMulAdd<uint64_t>(fplibNeg<uint64_t>(cOp3), cOp1, cOp2, fpscr)" ) 285 286 def buildBinFpOp(name, Name, base, opClass, singleOp, doubleOp): 287 global header_output, decoder_output, exec_output 288 289 code = singleIntConvCode2 % { "op": singleOp } 290 sIop = InstObjParams(name, Name + "S", base, --- 8 unchanged lines hidden (view full) --- 299 declareTempl = eval( base + "Declare"); 300 constructorTempl = eval("AA64" + base + "Constructor"); 301 302 for iop in sIop, dIop: 303 header_output += declareTempl.subst(iop) 304 decoder_output += constructorTempl.subst(iop) 305 exec_output += BasicExecute.subst(iop) 306 | 283 "fplibMulAdd<uint32_t>(fplibNeg<uint32_t>(cOp3), cOp1, cOp2, fpscr)", 284 "fplibMulAdd<uint64_t>(fplibNeg<uint64_t>(cOp3), cOp1, cOp2, fpscr)" ) 285 286 def buildBinFpOp(name, Name, base, opClass, singleOp, doubleOp): 287 global header_output, decoder_output, exec_output 288 289 code = singleIntConvCode2 % { "op": singleOp } 290 sIop = InstObjParams(name, Name + "S", base, --- 8 unchanged lines hidden (view full) --- 299 declareTempl = eval( base + "Declare"); 300 constructorTempl = eval("AA64" + base + "Constructor"); 301 302 for iop in sIop, dIop: 303 header_output += declareTempl.subst(iop) 304 decoder_output += constructorTempl.subst(iop) 305 exec_output += BasicExecute.subst(iop) 306 |
307 buildBinFpOp("fadd", "FAdd", "FpRegRegRegOp", "SimdFloatAddOp", | 307 buildBinFpOp("fadd", "FAdd", "FpRegRegRegOp", "FloatAddOp", |
308 "fplibAdd<uint32_t>(cOp1, cOp2, fpscr)", 309 "fplibAdd<uint64_t>(cOp1, cOp2, fpscr)") | 308 "fplibAdd<uint32_t>(cOp1, cOp2, fpscr)", 309 "fplibAdd<uint64_t>(cOp1, cOp2, fpscr)") |
310 buildBinFpOp("fsub", "FSub", "FpRegRegRegOp", "SimdFloatAddOp", | 310 buildBinFpOp("fsub", "FSub", "FpRegRegRegOp", "FloatAddOp", |
311 "fplibSub<uint32_t>(cOp1, cOp2, fpscr)", 312 "fplibSub<uint64_t>(cOp1, cOp2, fpscr)") | 311 "fplibSub<uint32_t>(cOp1, cOp2, fpscr)", 312 "fplibSub<uint64_t>(cOp1, cOp2, fpscr)") |
313 buildBinFpOp("fdiv", "FDiv", "FpRegRegRegOp", "SimdFloatDivOp", | 313 buildBinFpOp("fdiv", "FDiv", "FpRegRegRegOp", "FloatDivOp", |
314 "fplibDiv<uint32_t>(cOp1, cOp2, fpscr)", 315 "fplibDiv<uint64_t>(cOp1, cOp2, fpscr)") | 314 "fplibDiv<uint32_t>(cOp1, cOp2, fpscr)", 315 "fplibDiv<uint64_t>(cOp1, cOp2, fpscr)") |
316 buildBinFpOp("fmul", "FMul", "FpRegRegRegOp", "SimdFloatMultOp", | 316 buildBinFpOp("fmul", "FMul", "FpRegRegRegOp", "FloatMultOp", |
317 "fplibMul<uint32_t>(cOp1, cOp2, fpscr)", 318 "fplibMul<uint64_t>(cOp1, cOp2, fpscr)") | 317 "fplibMul<uint32_t>(cOp1, cOp2, fpscr)", 318 "fplibMul<uint64_t>(cOp1, cOp2, fpscr)") |
319 buildBinFpOp("fnmul", "FNMul", "FpRegRegRegOp", "SimdFloatMultOp", | 319 buildBinFpOp("fnmul", "FNMul", "FpRegRegRegOp", "FloatMultOp", |
320 "fplibNeg<uint32_t>(fplibMul<uint32_t>(cOp1, cOp2, fpscr))", 321 "fplibNeg<uint64_t>(fplibMul<uint64_t>(cOp1, cOp2, fpscr))") | 320 "fplibNeg<uint32_t>(fplibMul<uint32_t>(cOp1, cOp2, fpscr))", 321 "fplibNeg<uint64_t>(fplibMul<uint64_t>(cOp1, cOp2, fpscr))") |
322 buildBinFpOp("fmin", "FMin", "FpRegRegRegOp", "SimdFloatCmpOp", | 322 buildBinFpOp("fmin", "FMin", "FpRegRegRegOp", "FloatCmpOp", |
323 "fplibMin<uint32_t>(cOp1, cOp2, fpscr)", 324 "fplibMin<uint64_t>(cOp1, cOp2, fpscr)") | 323 "fplibMin<uint32_t>(cOp1, cOp2, fpscr)", 324 "fplibMin<uint64_t>(cOp1, cOp2, fpscr)") |
325 buildBinFpOp("fmax", "FMax", "FpRegRegRegOp", "SimdFloatCmpOp", | 325 buildBinFpOp("fmax", "FMax", "FpRegRegRegOp", "FloatCmpOp", |
326 "fplibMax<uint32_t>(cOp1, cOp2, fpscr)", 327 "fplibMax<uint64_t>(cOp1, cOp2, fpscr)") | 326 "fplibMax<uint32_t>(cOp1, cOp2, fpscr)", 327 "fplibMax<uint64_t>(cOp1, cOp2, fpscr)") |
328 buildBinFpOp("fminnm", "FMinNM", "FpRegRegRegOp", "SimdFloatCmpOp", | 328 buildBinFpOp("fminnm", "FMinNM", "FpRegRegRegOp", "FloatCmpOp", |
329 "fplibMinNum<uint32_t>(cOp1, cOp2, fpscr)", 330 "fplibMinNum<uint64_t>(cOp1, cOp2, fpscr)") | 329 "fplibMinNum<uint32_t>(cOp1, cOp2, fpscr)", 330 "fplibMinNum<uint64_t>(cOp1, cOp2, fpscr)") |
331 buildBinFpOp("fmaxnm", "FMaxNM", "FpRegRegRegOp", "SimdFloatCmpOp", | 331 buildBinFpOp("fmaxnm", "FMaxNM", "FpRegRegRegOp", "FloatCmpOp", |
332 "fplibMaxNum<uint32_t>(cOp1, cOp2, fpscr)", 333 "fplibMaxNum<uint64_t>(cOp1, cOp2, fpscr)") 334 335 def buildUnaryFpOp(name, Name, base, opClass, singleOp, doubleOp = None): 336 if doubleOp is None: 337 doubleOp = singleOp 338 global header_output, decoder_output, exec_output 339 --- 9 unchanged lines hidden (view full) --- 349 declareTempl = eval( base + "Declare"); 350 constructorTempl = eval("AA64" + base + "Constructor"); 351 352 for iop in sIop, dIop: 353 header_output += declareTempl.subst(iop) 354 decoder_output += constructorTempl.subst(iop) 355 exec_output += BasicExecute.subst(iop) 356 | 332 "fplibMaxNum<uint32_t>(cOp1, cOp2, fpscr)", 333 "fplibMaxNum<uint64_t>(cOp1, cOp2, fpscr)") 334 335 def buildUnaryFpOp(name, Name, base, opClass, singleOp, doubleOp = None): 336 if doubleOp is None: 337 doubleOp = singleOp 338 global header_output, decoder_output, exec_output 339 --- 9 unchanged lines hidden (view full) --- 349 declareTempl = eval( base + "Declare"); 350 constructorTempl = eval("AA64" + base + "Constructor"); 351 352 for iop in sIop, dIop: 353 header_output += declareTempl.subst(iop) 354 decoder_output += constructorTempl.subst(iop) 355 exec_output += BasicExecute.subst(iop) 356 |
357 buildUnaryFpOp("fsqrt", "FSqrt", "FpRegRegOp", "SimdFloatSqrtOp", | 357 buildUnaryFpOp("fsqrt", "FSqrt", "FpRegRegOp", "FloatSqrtOp", |
358 "fplibSqrt<uint32_t>(cOp1, fpscr)", "fplibSqrt<uint64_t>(cOp1, fpscr)") 359 360 def buildSimpleUnaryFpOp(name, Name, base, opClass, singleOp, 361 doubleOp = None, isIntConv = True): 362 if doubleOp is None: 363 doubleOp = singleOp 364 global header_output, decoder_output, exec_output 365 --- 12 unchanged lines hidden (view full) --- 378 379 declareTempl = eval( base + "Declare"); 380 constructorTempl = eval("AA64" + base + "Constructor"); 381 382 header_output += declareTempl.subst(iop) 383 decoder_output += constructorTempl.subst(iop) 384 exec_output += BasicExecute.subst(iop) 385 | 358 "fplibSqrt<uint32_t>(cOp1, fpscr)", "fplibSqrt<uint64_t>(cOp1, fpscr)") 359 360 def buildSimpleUnaryFpOp(name, Name, base, opClass, singleOp, 361 doubleOp = None, isIntConv = True): 362 if doubleOp is None: 363 doubleOp = singleOp 364 global header_output, decoder_output, exec_output 365 --- 12 unchanged lines hidden (view full) --- 378 379 declareTempl = eval( base + "Declare"); 380 constructorTempl = eval("AA64" + base + "Constructor"); 381 382 header_output += declareTempl.subst(iop) 383 decoder_output += constructorTempl.subst(iop) 384 exec_output += BasicExecute.subst(iop) 385 |
386 buildSimpleUnaryFpOp("fneg", "FNeg", "FpRegRegOp", "SimdFloatMiscOp", | 386 buildSimpleUnaryFpOp("fneg", "FNeg", "FpRegRegOp", "FloatMiscOp", |
387 "fplibNeg<uint32_t>(cOp1)", "fplibNeg<uint64_t>(cOp1)") | 387 "fplibNeg<uint32_t>(cOp1)", "fplibNeg<uint64_t>(cOp1)") |
388 buildSimpleUnaryFpOp("fabs", "FAbs", "FpRegRegOp", "SimdFloatMiscOp", | 388 buildSimpleUnaryFpOp("fabs", "FAbs", "FpRegRegOp", "FloatMiscOp", |
389 "fplibAbs<uint32_t>(cOp1)", "fplibAbs<uint64_t>(cOp1)") | 389 "fplibAbs<uint32_t>(cOp1)", "fplibAbs<uint64_t>(cOp1)") |
390 buildSimpleUnaryFpOp("frintn", "FRIntN", "FpRegRegOp", "SimdFloatMiscOp", | 390 buildSimpleUnaryFpOp("frintn", "FRIntN", "FpRegRegOp", "FloatMiscOp", |
391 "fplibRoundInt<uint32_t>(cOp1, FPRounding_TIEEVEN, false, fpscr)", 392 "fplibRoundInt<uint64_t>(cOp1, FPRounding_TIEEVEN, false, fpscr)") | 391 "fplibRoundInt<uint32_t>(cOp1, FPRounding_TIEEVEN, false, fpscr)", 392 "fplibRoundInt<uint64_t>(cOp1, FPRounding_TIEEVEN, false, fpscr)") |
393 buildSimpleUnaryFpOp("frintp", "FRIntP", "FpRegRegOp", "SimdFloatMiscOp", | 393 buildSimpleUnaryFpOp("frintp", "FRIntP", "FpRegRegOp", "FloatMiscOp", |
394 "fplibRoundInt<uint32_t>(cOp1, FPRounding_POSINF, false, fpscr)", 395 "fplibRoundInt<uint64_t>(cOp1, FPRounding_POSINF, false, fpscr)") | 394 "fplibRoundInt<uint32_t>(cOp1, FPRounding_POSINF, false, fpscr)", 395 "fplibRoundInt<uint64_t>(cOp1, FPRounding_POSINF, false, fpscr)") |
396 buildSimpleUnaryFpOp("frintm", "FRIntM", "FpRegRegOp", "SimdFloatMiscOp", | 396 buildSimpleUnaryFpOp("frintm", "FRIntM", "FpRegRegOp", "FloatMiscOp", |
397 "fplibRoundInt<uint32_t>(cOp1, FPRounding_NEGINF, false, fpscr)", 398 "fplibRoundInt<uint64_t>(cOp1, FPRounding_NEGINF, false, fpscr)") | 397 "fplibRoundInt<uint32_t>(cOp1, FPRounding_NEGINF, false, fpscr)", 398 "fplibRoundInt<uint64_t>(cOp1, FPRounding_NEGINF, false, fpscr)") |
399 buildSimpleUnaryFpOp("frintz", "FRIntZ", "FpRegRegOp", "SimdFloatMiscOp", | 399 buildSimpleUnaryFpOp("frintz", "FRIntZ", "FpRegRegOp", "FloatMiscOp", |
400 "fplibRoundInt<uint32_t>(cOp1, FPRounding_ZERO, false, fpscr)", 401 "fplibRoundInt<uint64_t>(cOp1, FPRounding_ZERO, false, fpscr)") | 400 "fplibRoundInt<uint32_t>(cOp1, FPRounding_ZERO, false, fpscr)", 401 "fplibRoundInt<uint64_t>(cOp1, FPRounding_ZERO, false, fpscr)") |
402 buildSimpleUnaryFpOp("frinta", "FRIntA", "FpRegRegOp", "SimdFloatMiscOp", | 402 buildSimpleUnaryFpOp("frinta", "FRIntA", "FpRegRegOp", "FloatMiscOp", |
403 "fplibRoundInt<uint32_t>(cOp1, FPRounding_TIEAWAY, false, fpscr)", 404 "fplibRoundInt<uint64_t>(cOp1, FPRounding_TIEAWAY, false, fpscr)") | 403 "fplibRoundInt<uint32_t>(cOp1, FPRounding_TIEAWAY, false, fpscr)", 404 "fplibRoundInt<uint64_t>(cOp1, FPRounding_TIEAWAY, false, fpscr)") |
405 buildSimpleUnaryFpOp("frinti", "FRIntI", "FpRegRegOp", "SimdFloatMiscOp", | 405 buildSimpleUnaryFpOp("frinti", "FRIntI", "FpRegRegOp", "FloatMiscOp", |
406 "fplibRoundInt<uint32_t>(cOp1, FPCRRounding(fpscr), false, fpscr)", 407 "fplibRoundInt<uint64_t>(cOp1, FPCRRounding(fpscr), false, fpscr)") | 406 "fplibRoundInt<uint32_t>(cOp1, FPCRRounding(fpscr), false, fpscr)", 407 "fplibRoundInt<uint64_t>(cOp1, FPCRRounding(fpscr), false, fpscr)") |
408 buildSimpleUnaryFpOp("frintx", "FRIntX", "FpRegRegOp", "SimdFloatMiscOp", | 408 buildSimpleUnaryFpOp("frintx", "FRIntX", "FpRegRegOp", "FloatMiscOp", |
409 "fplibRoundInt<uint32_t>(cOp1, FPCRRounding(fpscr), true, fpscr)", 410 "fplibRoundInt<uint64_t>(cOp1, FPCRRounding(fpscr), true, fpscr)") 411}}; 412 413let {{ 414 415 header_output = "" 416 decoder_output = "" --- 29 unchanged lines hidden (view full) --- 446 AA64FpDestP2_uw = 0; 447 AA64FpDestP3_uw = 0; 448 FpscrExc = fpscr; 449 ''' 450 451 instName = "Fcvt%s%sIntFp%s" %(regL, us, "D" if isDouble else "S") 452 mnem = "%scvtf" %(us.lower()) 453 fcvtIntFpDIop = InstObjParams(mnem, instName, "FpRegRegOp", | 409 "fplibRoundInt<uint32_t>(cOp1, FPCRRounding(fpscr), true, fpscr)", 410 "fplibRoundInt<uint64_t>(cOp1, FPCRRounding(fpscr), true, fpscr)") 411}}; 412 413let {{ 414 415 header_output = "" 416 decoder_output = "" --- 29 unchanged lines hidden (view full) --- 446 AA64FpDestP2_uw = 0; 447 AA64FpDestP3_uw = 0; 448 FpscrExc = fpscr; 449 ''' 450 451 instName = "Fcvt%s%sIntFp%s" %(regL, us, "D" if isDouble else "S") 452 mnem = "%scvtf" %(us.lower()) 453 fcvtIntFpDIop = InstObjParams(mnem, instName, "FpRegRegOp", |
454 { "code": fcvtIntFpDCode, 455 "op_class": "SimdFloatCvtOp" }, []) | 454 { "code": fcvtIntFpDCode, 455 "op_class": "FloatCvtOp" }, []) |
456 header_output += FpRegRegOpDeclare.subst(fcvtIntFpDIop); 457 decoder_output += AA64FpRegRegOpConstructor.subst(fcvtIntFpDIop); 458 exec_output += BasicExecute.subst(fcvtIntFpDIop); 459 460 # Generates the floating point to integer conversion instructions in various 461 # variants, eg signed/unsigned 462 def buildFpCvtIntOp(isDouble, isSigned, isXReg): 463 global header_output, decoder_output, exec_output --- 22 unchanged lines hidden (view full) --- 486 roundingMode) 487 488 instName = "FcvtFp%sInt%s%s%s" %("S" if isSigned else "U", 489 "X" if isXReg else "W", 490 "D" if isDouble else "S", rmode) 491 mnem = "fcvt%s%s" %(rmode, "s" if isSigned else "u") 492 fcvtFpIntIop = InstObjParams(mnem, instName, "FpRegRegOp", 493 { "code": fcvtFpIntCode, | 456 header_output += FpRegRegOpDeclare.subst(fcvtIntFpDIop); 457 decoder_output += AA64FpRegRegOpConstructor.subst(fcvtIntFpDIop); 458 exec_output += BasicExecute.subst(fcvtIntFpDIop); 459 460 # Generates the floating point to integer conversion instructions in various 461 # variants, eg signed/unsigned 462 def buildFpCvtIntOp(isDouble, isSigned, isXReg): 463 global header_output, decoder_output, exec_output --- 22 unchanged lines hidden (view full) --- 486 roundingMode) 487 488 instName = "FcvtFp%sInt%s%s%s" %("S" if isSigned else "U", 489 "X" if isXReg else "W", 490 "D" if isDouble else "S", rmode) 491 mnem = "fcvt%s%s" %(rmode, "s" if isSigned else "u") 492 fcvtFpIntIop = InstObjParams(mnem, instName, "FpRegRegOp", 493 { "code": fcvtFpIntCode, |
494 "op_class": "SimdFloatCvtOp" }, []) | 494 "op_class": "FloatCvtOp" }, []) |
495 header_output += FpRegRegOpDeclare.subst(fcvtFpIntIop); 496 decoder_output += FpRegRegOpConstructor.subst(fcvtFpIntIop); 497 exec_output += BasicExecute.subst(fcvtFpIntIop); 498 499 # Now actually do the building with the different variants 500 for isDouble in True, False: 501 for isSigned in True, False: 502 for isXReg in True, False: --- 6 unchanged lines hidden (view full) --- 509 AA64FpDestP0_uw = cDest; 510 AA64FpDestP1_uw = cDest >> 32; 511 AA64FpDestP2_uw = 0; 512 AA64FpDestP3_uw = 0; 513 FpscrExc = fpscr; 514 ''' 515 fcvtFpSFpDIop = InstObjParams("fcvt", "FCvtFpSFpD", "FpRegRegOp", 516 { "code": fcvtFpSFpDCode, | 495 header_output += FpRegRegOpDeclare.subst(fcvtFpIntIop); 496 decoder_output += FpRegRegOpConstructor.subst(fcvtFpIntIop); 497 exec_output += BasicExecute.subst(fcvtFpIntIop); 498 499 # Now actually do the building with the different variants 500 for isDouble in True, False: 501 for isSigned in True, False: 502 for isXReg in True, False: --- 6 unchanged lines hidden (view full) --- 509 AA64FpDestP0_uw = cDest; 510 AA64FpDestP1_uw = cDest >> 32; 511 AA64FpDestP2_uw = 0; 512 AA64FpDestP3_uw = 0; 513 FpscrExc = fpscr; 514 ''' 515 fcvtFpSFpDIop = InstObjParams("fcvt", "FCvtFpSFpD", "FpRegRegOp", 516 { "code": fcvtFpSFpDCode, |
517 "op_class": "SimdFloatCvtOp" }, []) | 517 "op_class": "FloatCvtOp" }, []) |
518 header_output += FpRegRegOpDeclare.subst(fcvtFpSFpDIop); 519 decoder_output += AA64FpRegRegOpConstructor.subst(fcvtFpSFpDIop); 520 exec_output += BasicExecute.subst(fcvtFpSFpDIop); 521 522 fcvtFpDFpSCode = vfp64EnabledCheckCode + ''' 523 FPSCR fpscr = (FPSCR) FpscrExc; 524 uint64_t cOp1 = AA64FpOp1P0_uw | (uint64_t)AA64FpOp1P1_uw << 32; 525 AA64FpDestP0_uw = fplibConvert<uint64_t, uint32_t>(cOp1, 526 FPCRRounding(fpscr), fpscr); 527 AA64FpDestP1_uw = 0; 528 AA64FpDestP2_uw = 0; 529 AA64FpDestP3_uw = 0; 530 FpscrExc = fpscr; 531 ''' 532 fcvtFpDFpSIop = InstObjParams("fcvt", "FcvtFpDFpS", "FpRegRegOp", 533 {"code": fcvtFpDFpSCode, | 518 header_output += FpRegRegOpDeclare.subst(fcvtFpSFpDIop); 519 decoder_output += AA64FpRegRegOpConstructor.subst(fcvtFpSFpDIop); 520 exec_output += BasicExecute.subst(fcvtFpSFpDIop); 521 522 fcvtFpDFpSCode = vfp64EnabledCheckCode + ''' 523 FPSCR fpscr = (FPSCR) FpscrExc; 524 uint64_t cOp1 = AA64FpOp1P0_uw | (uint64_t)AA64FpOp1P1_uw << 32; 525 AA64FpDestP0_uw = fplibConvert<uint64_t, uint32_t>(cOp1, 526 FPCRRounding(fpscr), fpscr); 527 AA64FpDestP1_uw = 0; 528 AA64FpDestP2_uw = 0; 529 AA64FpDestP3_uw = 0; 530 FpscrExc = fpscr; 531 ''' 532 fcvtFpDFpSIop = InstObjParams("fcvt", "FcvtFpDFpS", "FpRegRegOp", 533 {"code": fcvtFpDFpSCode, |
534 "op_class": "SimdFloatCvtOp" }, []) | 534 "op_class": "FloatCvtOp" }, []) |
535 header_output += FpRegRegOpDeclare.subst(fcvtFpDFpSIop); 536 decoder_output += AA64FpRegRegOpConstructor.subst(fcvtFpDFpSIop); 537 exec_output += BasicExecute.subst(fcvtFpDFpSIop); 538 539 # Half precision to single or double precision conversion 540 for isDouble in True, False: 541 code = vfp64EnabledCheckCode + ''' 542 FPSCR fpscr = (FPSCR) FpscrExc; --- 15 unchanged lines hidden (view full) --- 558 AA64FpDestP2_uw = 0; 559 AA64FpDestP3_uw = 0; 560 FpscrExc = fpscr; 561 ''' 562 563 instName = "FcvtFpHFp%s" %("D" if isDouble else "S") 564 fcvtFpHFpIop = InstObjParams("fcvt", instName, "FpRegRegOp", 565 { "code": code, | 535 header_output += FpRegRegOpDeclare.subst(fcvtFpDFpSIop); 536 decoder_output += AA64FpRegRegOpConstructor.subst(fcvtFpDFpSIop); 537 exec_output += BasicExecute.subst(fcvtFpDFpSIop); 538 539 # Half precision to single or double precision conversion 540 for isDouble in True, False: 541 code = vfp64EnabledCheckCode + ''' 542 FPSCR fpscr = (FPSCR) FpscrExc; --- 15 unchanged lines hidden (view full) --- 558 AA64FpDestP2_uw = 0; 559 AA64FpDestP3_uw = 0; 560 FpscrExc = fpscr; 561 ''' 562 563 instName = "FcvtFpHFp%s" %("D" if isDouble else "S") 564 fcvtFpHFpIop = InstObjParams("fcvt", instName, "FpRegRegOp", 565 { "code": code, |
566 "op_class": "SimdFloatCvtOp" }, []) | 566 "op_class": "FloatCvtOp" }, []) |
567 header_output += FpRegRegOpDeclare.subst(fcvtFpHFpIop); 568 decoder_output += AA64FpRegRegOpConstructor.subst(fcvtFpHFpIop); 569 exec_output += BasicExecute.subst(fcvtFpHFpIop); 570 571 # single or double precision to Half precision conversion 572 for isDouble in True, False: 573 code = vfp64EnabledCheckCode + ''' 574 FPSCR fpscr = (FPSCR) FpscrExc; --- 6 unchanged lines hidden (view full) --- 581 FpscrExc = fpscr; 582 ''' % ("uint64_t cOp1 = AA64FpOp1P0_uw | (uint64_t)AA64FpOp1P1_uw << 32" 583 if isDouble else "uint32_t cOp1 = AA64FpOp1P0_uw", 584 "64" if isDouble else "32") 585 586 instName = "FcvtFp%sFpH" %("D" if isDouble else "S") 587 fcvtFpFpHIop = InstObjParams("fcvt", instName, "FpRegRegOp", 588 { "code": code, | 567 header_output += FpRegRegOpDeclare.subst(fcvtFpHFpIop); 568 decoder_output += AA64FpRegRegOpConstructor.subst(fcvtFpHFpIop); 569 exec_output += BasicExecute.subst(fcvtFpHFpIop); 570 571 # single or double precision to Half precision conversion 572 for isDouble in True, False: 573 code = vfp64EnabledCheckCode + ''' 574 FPSCR fpscr = (FPSCR) FpscrExc; --- 6 unchanged lines hidden (view full) --- 581 FpscrExc = fpscr; 582 ''' % ("uint64_t cOp1 = AA64FpOp1P0_uw | (uint64_t)AA64FpOp1P1_uw << 32" 583 if isDouble else "uint32_t cOp1 = AA64FpOp1P0_uw", 584 "64" if isDouble else "32") 585 586 instName = "FcvtFp%sFpH" %("D" if isDouble else "S") 587 fcvtFpFpHIop = InstObjParams("fcvt", instName, "FpRegRegOp", 588 { "code": code, |
589 "op_class": "SimdFloatCvtOp" }, []) | 589 "op_class": "FloatCvtOp" }, []) |
590 header_output += FpRegRegOpDeclare.subst(fcvtFpFpHIop); 591 decoder_output += AA64FpRegRegOpConstructor.subst(fcvtFpFpHIop); 592 exec_output += BasicExecute.subst(fcvtFpFpHIop); 593 594 # Build the various versions of the floating point compare instructions 595 def buildFCmpOp(isQuiet, isDouble, isImm): 596 global header_output, decoder_output, exec_output 597 --- 23 unchanged lines hidden (view full) --- 621 ''' % ("64" if isDouble else "32", "false" if isQuiet else "true") 622 623 typeName = "Imm" if isImm else "Reg" 624 instName = "FCmp%s%s%s" %("" if isQuiet else "E", typeName, 625 "D" if isDouble else "S") 626 fcmpIop = InstObjParams("fcmp%s" %("" if isQuiet else "e"), instName, 627 "FpReg%sOp" %(typeName), 628 {"code": fcmpCode, | 590 header_output += FpRegRegOpDeclare.subst(fcvtFpFpHIop); 591 decoder_output += AA64FpRegRegOpConstructor.subst(fcvtFpFpHIop); 592 exec_output += BasicExecute.subst(fcvtFpFpHIop); 593 594 # Build the various versions of the floating point compare instructions 595 def buildFCmpOp(isQuiet, isDouble, isImm): 596 global header_output, decoder_output, exec_output 597 --- 23 unchanged lines hidden (view full) --- 621 ''' % ("64" if isDouble else "32", "false" if isQuiet else "true") 622 623 typeName = "Imm" if isImm else "Reg" 624 instName = "FCmp%s%s%s" %("" if isQuiet else "E", typeName, 625 "D" if isDouble else "S") 626 fcmpIop = InstObjParams("fcmp%s" %("" if isQuiet else "e"), instName, 627 "FpReg%sOp" %(typeName), 628 {"code": fcmpCode, |
629 "op_class": "SimdFloatCmpOp"}, []) | 629 "op_class": "FloatCmpOp"}, []) |
630 631 declareTemp = eval("FpReg%sOpDeclare" %(typeName)); 632 constructorTemp = eval("AA64FpReg%sOpConstructor" %(typeName)); 633 header_output += declareTemp.subst(fcmpIop); 634 decoder_output += constructorTemp.subst(fcmpIop); 635 exec_output += BasicExecute.subst(fcmpIop); 636 637 for isQuiet in True, False: --- 30 unchanged lines hidden (view full) --- 668 if isDouble else "AA64FpOp2P0_uw", 669 "64" if isDouble else "32", "false" if isQuiet else "true") 670 671 instName = "FCCmp%sReg%s" %("" if isQuiet else "E", 672 "D" if isDouble else "S") 673 fccmpIop = InstObjParams("fccmp%s" %("" if isQuiet else "e"), 674 instName, "FpCondCompRegOp", 675 {"code": fccmpCode, | 630 631 declareTemp = eval("FpReg%sOpDeclare" %(typeName)); 632 constructorTemp = eval("AA64FpReg%sOpConstructor" %(typeName)); 633 header_output += declareTemp.subst(fcmpIop); 634 decoder_output += constructorTemp.subst(fcmpIop); 635 exec_output += BasicExecute.subst(fcmpIop); 636 637 for isQuiet in True, False: --- 30 unchanged lines hidden (view full) --- 668 if isDouble else "AA64FpOp2P0_uw", 669 "64" if isDouble else "32", "false" if isQuiet else "true") 670 671 instName = "FCCmp%sReg%s" %("" if isQuiet else "E", 672 "D" if isDouble else "S") 673 fccmpIop = InstObjParams("fccmp%s" %("" if isQuiet else "e"), 674 instName, "FpCondCompRegOp", 675 {"code": fccmpCode, |
676 "op_class": "SimdFloatCmpOp"}, []) | 676 "op_class": "FloatCmpOp"}, []) |
677 header_output += DataXCondCompRegDeclare.subst(fccmpIop); 678 decoder_output += DataXCondCompRegConstructor.subst(fccmpIop); 679 exec_output += BasicExecute.subst(fccmpIop); 680 681 for isQuiet in True, False: 682 for isDouble in True, False: 683 buildFCCmpOp(isQuiet, isDouble) 684 --- 28 unchanged lines hidden (view full) --- 713 "false" if isSigned else "true") 714 715 instName = "FcvtFp%sFixed%s%s" %("S" if isSigned else "U", 716 "D" if isDouble else "S", 717 "X" if isXReg else "W") 718 mnem = "fcvtz%s" %("s" if isSigned else "u") 719 fcvtFpFixedIop = InstObjParams(mnem, instName, "FpRegRegImmOp", 720 { "code": fcvtFpFixedCode, | 677 header_output += DataXCondCompRegDeclare.subst(fccmpIop); 678 decoder_output += DataXCondCompRegConstructor.subst(fccmpIop); 679 exec_output += BasicExecute.subst(fccmpIop); 680 681 for isQuiet in True, False: 682 for isDouble in True, False: 683 buildFCCmpOp(isQuiet, isDouble) 684 --- 28 unchanged lines hidden (view full) --- 713 "false" if isSigned else "true") 714 715 instName = "FcvtFp%sFixed%s%s" %("S" if isSigned else "U", 716 "D" if isDouble else "S", 717 "X" if isXReg else "W") 718 mnem = "fcvtz%s" %("s" if isSigned else "u") 719 fcvtFpFixedIop = InstObjParams(mnem, instName, "FpRegRegImmOp", 720 { "code": fcvtFpFixedCode, |
721 "op_class": "SimdFloatCvtOp" }, []) | 721 "op_class": "FloatCvtOp" }, []) |
722 header_output += FpRegRegImmOpDeclare.subst(fcvtFpFixedIop); 723 decoder_output += AA64FpRegRegImmOpConstructor.subst(fcvtFpFixedIop); 724 exec_output += BasicExecute.subst(fcvtFpFixedIop); 725 726 # Generates the variants of the fixed to floating point instructions 727 def buildFixedCvtFpOp(isSigned, isDouble, isXReg): 728 global header_output, decoder_output, exec_output 729 --- 24 unchanged lines hidden (view full) --- 754 ''' 755 756 instName = "Fcvt%sFixedFp%s%s" %("S" if isSigned else "U", 757 "D" if isDouble else "S", 758 srcRegType) 759 mnem = "%scvtf" %("s" if isSigned else "u") 760 fcvtFixedFpIop = InstObjParams(mnem, instName, "FpRegRegImmOp", 761 { "code": fcvtFixedFpCode, | 722 header_output += FpRegRegImmOpDeclare.subst(fcvtFpFixedIop); 723 decoder_output += AA64FpRegRegImmOpConstructor.subst(fcvtFpFixedIop); 724 exec_output += BasicExecute.subst(fcvtFpFixedIop); 725 726 # Generates the variants of the fixed to floating point instructions 727 def buildFixedCvtFpOp(isSigned, isDouble, isXReg): 728 global header_output, decoder_output, exec_output 729 --- 24 unchanged lines hidden (view full) --- 754 ''' 755 756 instName = "Fcvt%sFixedFp%s%s" %("S" if isSigned else "U", 757 "D" if isDouble else "S", 758 srcRegType) 759 mnem = "%scvtf" %("s" if isSigned else "u") 760 fcvtFixedFpIop = InstObjParams(mnem, instName, "FpRegRegImmOp", 761 { "code": fcvtFixedFpCode, |
762 "op_class": "SimdFloatCvtOp" }, []) | 762 "op_class": "FloatCvtOp" }, []) |
763 header_output += FpRegRegImmOpDeclare.subst(fcvtFixedFpIop); 764 decoder_output += FpRegRegImmOpConstructor.subst(fcvtFixedFpIop); 765 exec_output += BasicExecute.subst(fcvtFixedFpIop); 766 767 # loop over the variants building the instructions for each 768 for isXReg in True, False: 769 for isDouble in True, False: 770 for isSigned in True, False: --- 28 unchanged lines hidden (view full) --- 799 AA64FpDestP1_uw = 0; 800 ''' 801 code += ''' 802 AA64FpDestP2_uw = 0; 803 AA64FpDestP3_uw = 0; 804 ''' 805 806 iop = InstObjParams("fcsel", "FCSel%s" %("D" if isDouble else "S"), | 763 header_output += FpRegRegImmOpDeclare.subst(fcvtFixedFpIop); 764 decoder_output += FpRegRegImmOpConstructor.subst(fcvtFixedFpIop); 765 exec_output += BasicExecute.subst(fcvtFixedFpIop); 766 767 # loop over the variants building the instructions for each 768 for isXReg in True, False: 769 for isDouble in True, False: 770 for isSigned in True, False: --- 28 unchanged lines hidden (view full) --- 799 AA64FpDestP1_uw = 0; 800 ''' 801 code += ''' 802 AA64FpDestP2_uw = 0; 803 AA64FpDestP3_uw = 0; 804 ''' 805 806 iop = InstObjParams("fcsel", "FCSel%s" %("D" if isDouble else "S"), |
807 "FpCondSelOp", code) | 807 "FpCondSelOp", { "code": code, 808 "op_class": "FloatCvtOp" }) |
808 header_output += DataXCondSelDeclare.subst(iop) 809 decoder_output += DataXCondSelConstructor.subst(iop) 810 exec_output += BasicExecute.subst(iop) 811}}; | 809 header_output += DataXCondSelDeclare.subst(iop) 810 decoder_output += DataXCondSelConstructor.subst(iop) 811 exec_output += BasicExecute.subst(iop) 812}}; |