1// -*- mode:c++ -*-
2
3// Copyright (c) 2012-2013, 2016 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder. You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated

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167}};
168
169let {{
170
171 header_output = ""
172 decoder_output = ""
173 exec_output = ""
174
175 singleIntConvCode = vfp64EnabledCheckCode + '''
176 FPSCR fpscr = (FPSCR) FpscrExc;
177 uint32_t cOp1 = AA64FpOp1P0_uw;
178 uint32_t cDest = %(op)s;
179 AA64FpDestP0_uw = cDest;
180 AA64FpDestP1_uw = 0;
181 AA64FpDestP2_uw = 0;
182 AA64FpDestP3_uw = 0;

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227 dbl(AA64FpOp2P0_uw, AA64FpOp2P1_uw),
228 %(func)s, fpscr.fz, fpscr.dn, fpscr.rMode);
229 '''
230 doubleUnaryOp = '''
231 unaryOp(fpscr, dbl(AA64FpOp1P0_uw, AA64FpOp1P1_uw), %(func)s,
232 fpscr.fz, fpscr.rMode)
233 '''
234
235 def buildTernaryFpOp(name, opClass, sOp, dOp):
236 global header_output, decoder_output, exec_output
237 for isDouble in True, False:
238 code = vfp64EnabledCheckCode + '''
239 FPSCR fpscr = (FPSCR) FpscrExc;
240 '''
241 if isDouble:
242 code += '''
243 uint64_t cOp1 = AA64FpOp1P0_uw | (uint64_t)AA64FpOp1P1_uw << 32;
244 uint64_t cOp2 = AA64FpOp2P0_uw | (uint64_t)AA64FpOp2P1_uw << 32;
245 uint64_t cOp3 = AA64FpOp3P0_uw | (uint64_t)AA64FpOp3P1_uw << 32;
246 uint64_t cDest;
247 ''' "cDest = " + dOp + ";" + '''
248 AA64FpDestP0_uw = cDest;
249 AA64FpDestP1_uw = cDest >> 32;
250 '''
251 else:
252 code += '''
253 uint32_t cOp1 = AA64FpOp1P0_uw;
254 uint32_t cOp2 = AA64FpOp2P0_uw;
255 uint32_t cOp3 = AA64FpOp3P0_uw;
256 uint32_t cDest;
257 ''' "cDest = " + sOp + ";" + '''
258 AA64FpDestP0_uw = cDest;
259 AA64FpDestP1_uw = 0;
260 '''
261 code += '''
262 AA64FpDestP2_uw = 0;
263 AA64FpDestP3_uw = 0;
264 FpscrExc = fpscr;
265 '''
266
267 iop = InstObjParams(name.lower(), name + ("D" if isDouble else "S"),
268 "FpRegRegRegRegOp",
269 { "code": code, "op_class": opClass }, [])
270
271 header_output += AA64FpRegRegRegRegOpDeclare.subst(iop)
272 decoder_output += AA64FpRegRegRegRegOpConstructor.subst(iop)
273 exec_output += BasicExecute.subst(iop)
274
275 buildTernaryFpOp("FMAdd", "FloatMultAccOp",
276 "fplibMulAdd<uint32_t>(cOp3, cOp1, cOp2, fpscr)",
277 "fplibMulAdd<uint64_t>(cOp3, cOp1, cOp2, fpscr)" )
278 buildTernaryFpOp("FMSub", "FloatMultAccOp",
279 "fplibMulAdd<uint32_t>(cOp3, fplibNeg<uint32_t>(cOp1), cOp2, fpscr)",
280 "fplibMulAdd<uint64_t>(cOp3, fplibNeg<uint64_t>(cOp1), cOp2, fpscr)" )
281 buildTernaryFpOp("FNMAdd", "FloatMultAccOp",
282 "fplibMulAdd<uint32_t>(fplibNeg<uint32_t>(cOp3), fplibNeg<uint32_t>(cOp1), cOp2, fpscr)",
283 "fplibMulAdd<uint64_t>(fplibNeg<uint64_t>(cOp3), fplibNeg<uint64_t>(cOp1), cOp2, fpscr)" )
284 buildTernaryFpOp("FNMSub", "FloatMultAccOp",
285 "fplibMulAdd<uint32_t>(fplibNeg<uint32_t>(cOp3), cOp1, cOp2, fpscr)",
286 "fplibMulAdd<uint64_t>(fplibNeg<uint64_t>(cOp3), cOp1, cOp2, fpscr)" )
287
288 def buildBinFpOp(name, Name, base, opClass, singleOp, doubleOp):
289 global header_output, decoder_output, exec_output
290
291 code = singleIntConvCode2 % { "op": singleOp }
292 sIop = InstObjParams(name, Name + "S", base,
293 { "code": code,
294 "op_class": opClass }, [])
295
296 code = doubleIntConvCode2 % { "op": doubleOp }
297 dIop = InstObjParams(name, Name + "D", base,
298 { "code": code,
299 "op_class": opClass }, [])
300
301 declareTempl = eval( base + "Declare");
302 constructorTempl = eval("AA64" + base + "Constructor");
303
304 for iop in sIop, dIop:
305 header_output += declareTempl.subst(iop)
306 decoder_output += constructorTempl.subst(iop)
307 exec_output += BasicExecute.subst(iop)
308
309 buildBinFpOp("fadd", "FAdd", "FpRegRegRegOp", "FloatAddOp",
310 "fplibAdd<uint32_t>(cOp1, cOp2, fpscr)",
311 "fplibAdd<uint64_t>(cOp1, cOp2, fpscr)")
312 buildBinFpOp("fsub", "FSub", "FpRegRegRegOp", "FloatAddOp",
313 "fplibSub<uint32_t>(cOp1, cOp2, fpscr)",
314 "fplibSub<uint64_t>(cOp1, cOp2, fpscr)")
315 buildBinFpOp("fdiv", "FDiv", "FpRegRegRegOp", "FloatDivOp",
316 "fplibDiv<uint32_t>(cOp1, cOp2, fpscr)",
317 "fplibDiv<uint64_t>(cOp1, cOp2, fpscr)")
318 buildBinFpOp("fmul", "FMul", "FpRegRegRegOp", "FloatMultOp",
319 "fplibMul<uint32_t>(cOp1, cOp2, fpscr)",
320 "fplibMul<uint64_t>(cOp1, cOp2, fpscr)")
321 buildBinFpOp("fnmul", "FNMul", "FpRegRegRegOp", "FloatMultOp",
322 "fplibNeg<uint32_t>(fplibMul<uint32_t>(cOp1, cOp2, fpscr))",
323 "fplibNeg<uint64_t>(fplibMul<uint64_t>(cOp1, cOp2, fpscr))")
324 buildBinFpOp("fmin", "FMin", "FpRegRegRegOp", "FloatCmpOp",
325 "fplibMin<uint32_t>(cOp1, cOp2, fpscr)",
326 "fplibMin<uint64_t>(cOp1, cOp2, fpscr)")
327 buildBinFpOp("fmax", "FMax", "FpRegRegRegOp", "FloatCmpOp",
328 "fplibMax<uint32_t>(cOp1, cOp2, fpscr)",
329 "fplibMax<uint64_t>(cOp1, cOp2, fpscr)")
330 buildBinFpOp("fminnm", "FMinNM", "FpRegRegRegOp", "FloatCmpOp",
331 "fplibMinNum<uint32_t>(cOp1, cOp2, fpscr)",
332 "fplibMinNum<uint64_t>(cOp1, cOp2, fpscr)")
333 buildBinFpOp("fmaxnm", "FMaxNM", "FpRegRegRegOp", "FloatCmpOp",
334 "fplibMaxNum<uint32_t>(cOp1, cOp2, fpscr)",
335 "fplibMaxNum<uint64_t>(cOp1, cOp2, fpscr)")
336
337 def buildUnaryFpOp(name, Name, base, opClass, singleOp, doubleOp = None):
338 if doubleOp is None:
339 doubleOp = singleOp
340 global header_output, decoder_output, exec_output
341
342 code = singleIntConvCode % { "op": singleOp }
343 sIop = InstObjParams(name, Name + "S", base,
344 { "code": code,
345 "op_class": opClass }, [])
346 code = doubleIntConvCode % { "op": doubleOp }
347 dIop = InstObjParams(name, Name + "D", base,
348 { "code": code,
349 "op_class": opClass }, [])
350
351 declareTempl = eval( base + "Declare");
352 constructorTempl = eval("AA64" + base + "Constructor");
353
354 for iop in sIop, dIop:
355 header_output += declareTempl.subst(iop)
356 decoder_output += constructorTempl.subst(iop)
357 exec_output += BasicExecute.subst(iop)
358
359 buildUnaryFpOp("fsqrt", "FSqrt", "FpRegRegOp", "FloatSqrtOp",
360 "fplibSqrt<uint32_t>(cOp1, fpscr)", "fplibSqrt<uint64_t>(cOp1, fpscr)")
361
362 def buildSimpleUnaryFpOp(name, Name, base, opClass, singleOp,
363 doubleOp = None, isIntConv = True):
364 if doubleOp is None:
365 doubleOp = singleOp
366 global header_output, decoder_output, exec_output
367
368 if isIntConv:
369 sCode = singleIntConvCode
370 dCode = doubleIntConvCode
371 else:
372 sCode = singleCode
373 dCode = doubleCode
374
375 for code, op, suffix in [[sCode, singleOp, "S"],
376 [dCode, doubleOp, "D"]]:
377 iop = InstObjParams(name, Name + suffix, base,
378 { "code": code % { "op": op },
379 "op_class": opClass }, [])
380
381 declareTempl = eval( base + "Declare");
382 constructorTempl = eval("AA64" + base + "Constructor");
383
384 header_output += declareTempl.subst(iop)
385 decoder_output += constructorTempl.subst(iop)
386 exec_output += BasicExecute.subst(iop)
387
388 buildSimpleUnaryFpOp("fneg", "FNeg", "FpRegRegOp", "FloatMiscOp",
389 "fplibNeg<uint32_t>(cOp1)", "fplibNeg<uint64_t>(cOp1)")
390 buildSimpleUnaryFpOp("fabs", "FAbs", "FpRegRegOp", "FloatMiscOp",
391 "fplibAbs<uint32_t>(cOp1)", "fplibAbs<uint64_t>(cOp1)")
392 buildSimpleUnaryFpOp("frintn", "FRIntN", "FpRegRegOp", "FloatMiscOp",
393 "fplibRoundInt<uint32_t>(cOp1, FPRounding_TIEEVEN, false, fpscr)",
394 "fplibRoundInt<uint64_t>(cOp1, FPRounding_TIEEVEN, false, fpscr)")
395 buildSimpleUnaryFpOp("frintp", "FRIntP", "FpRegRegOp", "FloatMiscOp",
396 "fplibRoundInt<uint32_t>(cOp1, FPRounding_POSINF, false, fpscr)",
397 "fplibRoundInt<uint64_t>(cOp1, FPRounding_POSINF, false, fpscr)")
398 buildSimpleUnaryFpOp("frintm", "FRIntM", "FpRegRegOp", "FloatMiscOp",
399 "fplibRoundInt<uint32_t>(cOp1, FPRounding_NEGINF, false, fpscr)",
400 "fplibRoundInt<uint64_t>(cOp1, FPRounding_NEGINF, false, fpscr)")
401 buildSimpleUnaryFpOp("frintz", "FRIntZ", "FpRegRegOp", "FloatMiscOp",
402 "fplibRoundInt<uint32_t>(cOp1, FPRounding_ZERO, false, fpscr)",
403 "fplibRoundInt<uint64_t>(cOp1, FPRounding_ZERO, false, fpscr)")
404 buildSimpleUnaryFpOp("frinta", "FRIntA", "FpRegRegOp", "FloatMiscOp",
405 "fplibRoundInt<uint32_t>(cOp1, FPRounding_TIEAWAY, false, fpscr)",
406 "fplibRoundInt<uint64_t>(cOp1, FPRounding_TIEAWAY, false, fpscr)")
407 buildSimpleUnaryFpOp("frinti", "FRIntI", "FpRegRegOp", "FloatMiscOp",
408 "fplibRoundInt<uint32_t>(cOp1, FPCRRounding(fpscr), false, fpscr)",
409 "fplibRoundInt<uint64_t>(cOp1, FPCRRounding(fpscr), false, fpscr)")
410 buildSimpleUnaryFpOp("frintx", "FRIntX", "FpRegRegOp", "FloatMiscOp",
411 "fplibRoundInt<uint32_t>(cOp1, FPCRRounding(fpscr), true, fpscr)",
412 "fplibRoundInt<uint64_t>(cOp1, FPCRRounding(fpscr), true, fpscr)")
413}};
414
415let {{
416
417 header_output = ""
418 decoder_output = ""
419 exec_output = ""
420

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