fp.isa (8607:5fb918115c07) | fp.isa (10037:5cac77888310) |
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1// -*- mode:c++ -*- 2 | 1// -*- mode:c++ -*- 2 |
3// Copyright (c) 2010 ARM Limited | 3// Copyright (c) 2010-2013 ARM Limited |
4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating 9// to a hardware implementation of the functionality of the software 10// licensed hereunder. You may use the software subject to the license 11// terms below provided that you ensure that this notice is replicated --- 174 unchanged lines hidden (view full) --- 186}}; 187 188let {{ 189 190 header_output = "" 191 decoder_output = "" 192 exec_output = "" 193 | 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating 9// to a hardware implementation of the functionality of the software 10// licensed hereunder. You may use the software subject to the license 11// terms below provided that you ensure that this notice is replicated --- 174 unchanged lines hidden (view full) --- 186}}; 187 188let {{ 189 190 header_output = "" 191 decoder_output = "" 192 exec_output = "" 193 |
194 vmsrIop = InstObjParams("vmsr", "Vmsr", "FpRegRegOp", 195 { "code": vmsrEnabledCheckCode + \ 196 "MiscDest = Op1;", | 194 vmsrCode = vmsrEnabledCheckCode + ''' 195 MiscDest = Op1; 196 ''' 197 198 vmsrIop = InstObjParams("vmsr", "Vmsr", "FpRegRegImmOp", 199 { "code": vmsrCode, |
197 "predicate_test": predicateTest, 198 "op_class": "SimdFloatMiscOp" }, 199 ["IsSerializeAfter","IsNonSpeculative"]) | 200 "predicate_test": predicateTest, 201 "op_class": "SimdFloatMiscOp" }, 202 ["IsSerializeAfter","IsNonSpeculative"]) |
200 header_output += FpRegRegOpDeclare.subst(vmsrIop); 201 decoder_output += FpRegRegOpConstructor.subst(vmsrIop); | 203 header_output += FpRegRegImmOpDeclare.subst(vmsrIop); 204 decoder_output += FpRegRegImmOpConstructor.subst(vmsrIop); |
202 exec_output += PredOpExecute.subst(vmsrIop); 203 204 vmsrFpscrCode = vmsrEnabledCheckCode + ''' 205 Fpscr = Op1 & ~FpCondCodesMask; 206 FpCondCodes = Op1 & FpCondCodesMask; 207 ''' 208 vmsrFpscrIop = InstObjParams("vmsr", "VmsrFpscr", "FpRegRegOp", 209 { "code": vmsrFpscrCode, 210 "predicate_test": predicateTest, 211 "op_class": "SimdFloatMiscOp" }, 212 ["IsSerializeAfter","IsNonSpeculative", 213 "IsSquashAfter"]) 214 header_output += FpRegRegOpDeclare.subst(vmsrFpscrIop); 215 decoder_output += FpRegRegOpConstructor.subst(vmsrFpscrIop); 216 exec_output += PredOpExecute.subst(vmsrFpscrIop); 217 | 205 exec_output += PredOpExecute.subst(vmsrIop); 206 207 vmsrFpscrCode = vmsrEnabledCheckCode + ''' 208 Fpscr = Op1 & ~FpCondCodesMask; 209 FpCondCodes = Op1 & FpCondCodesMask; 210 ''' 211 vmsrFpscrIop = InstObjParams("vmsr", "VmsrFpscr", "FpRegRegOp", 212 { "code": vmsrFpscrCode, 213 "predicate_test": predicateTest, 214 "op_class": "SimdFloatMiscOp" }, 215 ["IsSerializeAfter","IsNonSpeculative", 216 "IsSquashAfter"]) 217 header_output += FpRegRegOpDeclare.subst(vmsrFpscrIop); 218 decoder_output += FpRegRegOpConstructor.subst(vmsrFpscrIop); 219 exec_output += PredOpExecute.subst(vmsrFpscrIop); 220 |
218 vmrsIop = InstObjParams("vmrs", "Vmrs", "FpRegRegOp", 219 { "code": vmrsEnabledCheckCode + \ 220 "Dest = MiscOp1;", | 221 vmrsCode = vmrsEnabledCheckCode + ''' 222 CPSR cpsr = Cpsr; 223 SCR scr = Scr; 224 if (!inSecureState(scr, cpsr) && (cpsr.mode != MODE_HYP)) { 225 HCR hcr = Hcr; 226 bool hypTrap = false; 227 switch(xc->tcBase()->flattenMiscIndex(op1)) { 228 case MISCREG_FPSID: 229 hypTrap = hcr.tid0; 230 break; 231 case MISCREG_MVFR0: 232 case MISCREG_MVFR1: 233 hypTrap = hcr.tid3; 234 break; 235 } 236 if (hypTrap) { 237 return new HypervisorTrap(machInst, imm, 238 EC_TRAPPED_CP10_MRC_VMRS); 239 } 240 } 241 Dest = MiscOp1; 242 ''' 243 244 vmrsIop = InstObjParams("vmrs", "Vmrs", "FpRegRegImmOp", 245 { "code": vmrsCode, |
221 "predicate_test": predicateTest, 222 "op_class": "SimdFloatMiscOp" }, 223 ["IsSerializeBefore"]) | 246 "predicate_test": predicateTest, 247 "op_class": "SimdFloatMiscOp" }, 248 ["IsSerializeBefore"]) |
224 header_output += FpRegRegOpDeclare.subst(vmrsIop); 225 decoder_output += FpRegRegOpConstructor.subst(vmrsIop); | 249 header_output += FpRegRegImmOpDeclare.subst(vmrsIop); 250 decoder_output += FpRegRegImmOpConstructor.subst(vmrsIop); |
226 exec_output += PredOpExecute.subst(vmrsIop); 227 228 vmrsFpscrIop = InstObjParams("vmrs", "VmrsFpscr", "FpRegRegOp", 229 { "code": vmrsEnabledCheckCode + \ 230 "Dest = Fpscr | FpCondCodes;", 231 "predicate_test": predicateTest, 232 "op_class": "SimdFloatMiscOp" }, 233 ["IsSerializeBefore"]) --- 84 unchanged lines hidden (view full) --- 318 vmovRegQIop = InstObjParams("vmov", "VmovRegQ", "FpRegRegOp", 319 { "code": vmovRegQCode, 320 "predicate_test": predicateTest, 321 "op_class": "SimdFloatMiscOp" }, []) 322 header_output += FpRegRegOpDeclare.subst(vmovRegQIop); 323 decoder_output += FpRegRegOpConstructor.subst(vmovRegQIop); 324 exec_output += PredOpExecute.subst(vmovRegQIop); 325 | 251 exec_output += PredOpExecute.subst(vmrsIop); 252 253 vmrsFpscrIop = InstObjParams("vmrs", "VmrsFpscr", "FpRegRegOp", 254 { "code": vmrsEnabledCheckCode + \ 255 "Dest = Fpscr | FpCondCodes;", 256 "predicate_test": predicateTest, 257 "op_class": "SimdFloatMiscOp" }, 258 ["IsSerializeBefore"]) --- 84 unchanged lines hidden (view full) --- 343 vmovRegQIop = InstObjParams("vmov", "VmovRegQ", "FpRegRegOp", 344 { "code": vmovRegQCode, 345 "predicate_test": predicateTest, 346 "op_class": "SimdFloatMiscOp" }, []) 347 header_output += FpRegRegOpDeclare.subst(vmovRegQIop); 348 decoder_output += FpRegRegOpConstructor.subst(vmovRegQIop); 349 exec_output += PredOpExecute.subst(vmovRegQIop); 350 |
326 vmovCoreRegBCode = vfpEnabledCheckCode + ''' | 351 vmovCoreRegBCode = simdEnabledCheckCode + ''' |
327 FpDest_uw = insertBits(FpDest_uw, imm * 8 + 7, imm * 8, Op1_ub); 328 ''' 329 vmovCoreRegBIop = InstObjParams("vmov", "VmovCoreRegB", "FpRegRegImmOp", 330 { "code": vmovCoreRegBCode, 331 "predicate_test": predicateTest, 332 "op_class": "SimdFloatMiscOp" }, []) 333 header_output += FpRegRegImmOpDeclare.subst(vmovCoreRegBIop); 334 decoder_output += FpRegRegImmOpConstructor.subst(vmovCoreRegBIop); 335 exec_output += PredOpExecute.subst(vmovCoreRegBIop); 336 | 352 FpDest_uw = insertBits(FpDest_uw, imm * 8 + 7, imm * 8, Op1_ub); 353 ''' 354 vmovCoreRegBIop = InstObjParams("vmov", "VmovCoreRegB", "FpRegRegImmOp", 355 { "code": vmovCoreRegBCode, 356 "predicate_test": predicateTest, 357 "op_class": "SimdFloatMiscOp" }, []) 358 header_output += FpRegRegImmOpDeclare.subst(vmovCoreRegBIop); 359 decoder_output += FpRegRegImmOpConstructor.subst(vmovCoreRegBIop); 360 exec_output += PredOpExecute.subst(vmovCoreRegBIop); 361 |
337 vmovCoreRegHCode = vfpEnabledCheckCode + ''' | 362 vmovCoreRegHCode = simdEnabledCheckCode + ''' |
338 FpDest_uw = insertBits(FpDest_uw, imm * 16 + 15, imm * 16, Op1_uh); 339 ''' 340 vmovCoreRegHIop = InstObjParams("vmov", "VmovCoreRegH", "FpRegRegImmOp", 341 { "code": vmovCoreRegHCode, 342 "predicate_test": predicateTest, 343 "op_class": "SimdFloatMiscOp" }, []) 344 header_output += FpRegRegImmOpDeclare.subst(vmovCoreRegHIop); 345 decoder_output += FpRegRegImmOpConstructor.subst(vmovCoreRegHIop); --- 102 unchanged lines hidden (view full) --- 448 449 singleSimpleCode = vfpEnabledCheckCode + ''' 450 FPSCR fpscr M5_VAR_USED = (FPSCR) FpscrExc; 451 FpDest = %(op)s; 452 ''' 453 singleCode = singleSimpleCode + ''' 454 FpscrExc = fpscr; 455 ''' | 363 FpDest_uw = insertBits(FpDest_uw, imm * 16 + 15, imm * 16, Op1_uh); 364 ''' 365 vmovCoreRegHIop = InstObjParams("vmov", "VmovCoreRegH", "FpRegRegImmOp", 366 { "code": vmovCoreRegHCode, 367 "predicate_test": predicateTest, 368 "op_class": "SimdFloatMiscOp" }, []) 369 header_output += FpRegRegImmOpDeclare.subst(vmovCoreRegHIop); 370 decoder_output += FpRegRegImmOpConstructor.subst(vmovCoreRegHIop); --- 102 unchanged lines hidden (view full) --- 473 474 singleSimpleCode = vfpEnabledCheckCode + ''' 475 FPSCR fpscr M5_VAR_USED = (FPSCR) FpscrExc; 476 FpDest = %(op)s; 477 ''' 478 singleCode = singleSimpleCode + ''' 479 FpscrExc = fpscr; 480 ''' |
481 singleTernOp = vfpEnabledCheckCode + ''' 482 FPSCR fpscr = (FPSCR) FpscrExc; 483 VfpSavedState state = prepFpState(fpscr.rMode); 484 float cOp1 = FpOp1; 485 float cOp2 = FpOp2; 486 float cOp3 = FpDestP0; 487 FpDestP0 = ternaryOp(fpscr, %(palam)s, %(op)s, 488 fpscr.fz, fpscr.dn, fpscr.rMode); 489 finishVfp(fpscr, state, fpscr.fz); 490 FpscrExc = fpscr; 491 ''' |
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456 singleBinOp = "binaryOp(fpscr, FpOp1, FpOp2," + \ 457 "%(func)s, fpscr.fz, fpscr.dn, fpscr.rMode)" 458 singleUnaryOp = "unaryOp(fpscr, FpOp1, %(func)s, fpscr.fz, fpscr.rMode)" 459 doubleCode = vfpEnabledCheckCode + ''' 460 FPSCR fpscr M5_VAR_USED = (FPSCR) FpscrExc; 461 double dest = %(op)s; 462 FpDestP0_uw = dblLow(dest); 463 FpDestP1_uw = dblHi(dest); 464 FpscrExc = fpscr; 465 ''' | 492 singleBinOp = "binaryOp(fpscr, FpOp1, FpOp2," + \ 493 "%(func)s, fpscr.fz, fpscr.dn, fpscr.rMode)" 494 singleUnaryOp = "unaryOp(fpscr, FpOp1, %(func)s, fpscr.fz, fpscr.rMode)" 495 doubleCode = vfpEnabledCheckCode + ''' 496 FPSCR fpscr M5_VAR_USED = (FPSCR) FpscrExc; 497 double dest = %(op)s; 498 FpDestP0_uw = dblLow(dest); 499 FpDestP1_uw = dblHi(dest); 500 FpscrExc = fpscr; 501 ''' |
502 doubleTernOp = vfpEnabledCheckCode + ''' 503 FPSCR fpscr = (FPSCR) FpscrExc; 504 VfpSavedState state = prepFpState(fpscr.rMode); 505 double cOp1 = dbl(FpOp1P0_uw, FpOp1P1_uw); 506 double cOp2 = dbl(FpOp2P0_uw, FpOp2P1_uw); 507 double cOp3 = dbl(FpDestP0_uw, FpDestP1_uw); 508 double cDest = ternaryOp(fpscr, %(palam)s, %(op)s, 509 fpscr.fz, fpscr.dn, fpscr.rMode); 510 FpDestP0_uw = dblLow(cDest); 511 FpDestP1_uw = dblHi(cDest); 512 finishVfp(fpscr, state, fpscr.fz); 513 FpscrExc = fpscr; 514 ''' |
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466 doubleBinOp = ''' 467 binaryOp(fpscr, dbl(FpOp1P0_uw, FpOp1P1_uw), 468 dbl(FpOp2P0_uw, FpOp2P1_uw), 469 %(func)s, fpscr.fz, fpscr.dn, fpscr.rMode); 470 ''' 471 doubleUnaryOp = ''' 472 unaryOp(fpscr, dbl(FpOp1P0_uw, FpOp1P1_uw), %(func)s, 473 fpscr.fz, fpscr.rMode) 474 ''' 475 | 515 doubleBinOp = ''' 516 binaryOp(fpscr, dbl(FpOp1P0_uw, FpOp1P1_uw), 517 dbl(FpOp2P0_uw, FpOp2P1_uw), 518 %(func)s, fpscr.fz, fpscr.dn, fpscr.rMode); 519 ''' 520 doubleUnaryOp = ''' 521 unaryOp(fpscr, dbl(FpOp1P0_uw, FpOp1P1_uw), %(func)s, 522 fpscr.fz, fpscr.rMode) 523 ''' 524 |
525 def buildTernaryFpOp(Name, base, opClass, singleOp, doubleOp, paramStr): 526 global header_output, decoder_output, exec_output 527 528 code = singleTernOp % { "op": singleOp, "palam": paramStr } 529 sIop = InstObjParams(Name.lower() + "s", Name + "S", base, 530 { "code": code, 531 "predicate_test": predicateTest, 532 "op_class": opClass }, []) 533 code = doubleTernOp % { "op": doubleOp, "palam": paramStr } 534 dIop = InstObjParams(Name.lower() + "d", Name + "D", base, 535 { "code": code, 536 "predicate_test": predicateTest, 537 "op_class": opClass }, []) 538 539 declareTempl = eval(base + "Declare"); 540 constructorTempl = eval(base + "Constructor"); 541 542 for iop in sIop, dIop: 543 header_output += declareTempl.subst(iop) 544 decoder_output += constructorTempl.subst(iop) 545 exec_output += PredOpExecute.subst(iop) 546 547 buildTernaryFpOp("Vfma", "FpRegRegRegOp", "SimdFloatMultAccOp", 548 "fpMulAdd<float>", "fpMulAdd<double>", " cOp1, cOp2, cOp3" ) 549 buildTernaryFpOp("Vfms", "FpRegRegRegOp", "SimdFloatMultAccOp", 550 "fpMulAdd<float>", "fpMulAdd<double>", "-cOp1, cOp2, cOp3" ) 551 buildTernaryFpOp("Vfnma", "FpRegRegRegOp", "SimdFloatMultAccOp", 552 "fpMulAdd<float>", "fpMulAdd<double>", "-cOp1, cOp2, -cOp3" ) 553 buildTernaryFpOp("Vfnms", "FpRegRegRegOp", "SimdFloatMultAccOp", 554 "fpMulAdd<float>", "fpMulAdd<double>", " cOp1, cOp2, -cOp3" ) 555 |
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476 def buildBinFpOp(name, Name, base, opClass, singleOp, doubleOp): 477 global header_output, decoder_output, exec_output 478 479 code = singleCode % { "op": singleBinOp } 480 code = code % { "func": singleOp } 481 sIop = InstObjParams(name + "s", Name + "S", base, 482 { "code": code, 483 "predicate_test": predicateTest, --- 341 unchanged lines hidden (view full) --- 825 decoder_output += FpRegRegOpConstructor.subst(vcvtSIntFpDIop); 826 exec_output += PredOpExecute.subst(vcvtSIntFpDIop); 827 828 vcvtFpUIntSRCode = vfpEnabledCheckCode + ''' 829 FPSCR fpscr = (FPSCR) FpscrExc; 830 VfpSavedState state = prepFpState(fpscr.rMode); 831 vfpFlushToZero(fpscr, FpOp1); 832 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); | 556 def buildBinFpOp(name, Name, base, opClass, singleOp, doubleOp): 557 global header_output, decoder_output, exec_output 558 559 code = singleCode % { "op": singleBinOp } 560 code = code % { "func": singleOp } 561 sIop = InstObjParams(name + "s", Name + "S", base, 562 { "code": code, 563 "predicate_test": predicateTest, --- 341 unchanged lines hidden (view full) --- 905 decoder_output += FpRegRegOpConstructor.subst(vcvtSIntFpDIop); 906 exec_output += PredOpExecute.subst(vcvtSIntFpDIop); 907 908 vcvtFpUIntSRCode = vfpEnabledCheckCode + ''' 909 FPSCR fpscr = (FPSCR) FpscrExc; 910 VfpSavedState state = prepFpState(fpscr.rMode); 911 vfpFlushToZero(fpscr, FpOp1); 912 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); |
833 FpDest_uw = vfpFpSToFixed(FpOp1, false, false, 0, false); | 913 FpDest_uw = vfpFpToFixed<float>(FpOp1, false, 32, 0, false); |
834 __asm__ __volatile__("" :: "m" (FpDest_uw)); 835 finishVfp(fpscr, state, fpscr.fz); 836 FpscrExc = fpscr; 837 ''' 838 vcvtFpUIntSRIop = InstObjParams("vcvt", "VcvtFpUIntSR", "FpRegRegOp", 839 { "code": vcvtFpUIntSRCode, 840 "predicate_test": predicateTest, 841 "op_class": "SimdFloatCvtOp" }, []) 842 header_output += FpRegRegOpDeclare.subst(vcvtFpUIntSRIop); 843 decoder_output += FpRegRegOpConstructor.subst(vcvtFpUIntSRIop); 844 exec_output += PredOpExecute.subst(vcvtFpUIntSRIop); 845 846 vcvtFpUIntDRCode = vfpEnabledCheckCode + ''' 847 FPSCR fpscr = (FPSCR) FpscrExc; 848 double cOp1 = dbl(FpOp1P0_uw, FpOp1P1_uw); 849 vfpFlushToZero(fpscr, cOp1); 850 VfpSavedState state = prepFpState(fpscr.rMode); 851 __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); | 914 __asm__ __volatile__("" :: "m" (FpDest_uw)); 915 finishVfp(fpscr, state, fpscr.fz); 916 FpscrExc = fpscr; 917 ''' 918 vcvtFpUIntSRIop = InstObjParams("vcvt", "VcvtFpUIntSR", "FpRegRegOp", 919 { "code": vcvtFpUIntSRCode, 920 "predicate_test": predicateTest, 921 "op_class": "SimdFloatCvtOp" }, []) 922 header_output += FpRegRegOpDeclare.subst(vcvtFpUIntSRIop); 923 decoder_output += FpRegRegOpConstructor.subst(vcvtFpUIntSRIop); 924 exec_output += PredOpExecute.subst(vcvtFpUIntSRIop); 925 926 vcvtFpUIntDRCode = vfpEnabledCheckCode + ''' 927 FPSCR fpscr = (FPSCR) FpscrExc; 928 double cOp1 = dbl(FpOp1P0_uw, FpOp1P1_uw); 929 vfpFlushToZero(fpscr, cOp1); 930 VfpSavedState state = prepFpState(fpscr.rMode); 931 __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); |
852 uint64_t result = vfpFpDToFixed(cOp1, false, false, 0, false); | 932 uint64_t result = vfpFpToFixed<double>(cOp1, false, 32, 0, false); |
853 __asm__ __volatile__("" :: "m" (result)); 854 finishVfp(fpscr, state, fpscr.fz); 855 FpDestP0_uw = result; 856 FpscrExc = fpscr; 857 ''' 858 vcvtFpUIntDRIop = InstObjParams("vcvtr", "VcvtFpUIntDR", "FpRegRegOp", 859 { "code": vcvtFpUIntDRCode, 860 "predicate_test": predicateTest, 861 "op_class": "SimdFloatCvtOp" }, []) 862 header_output += FpRegRegOpDeclare.subst(vcvtFpUIntDRIop); 863 decoder_output += FpRegRegOpConstructor.subst(vcvtFpUIntDRIop); 864 exec_output += PredOpExecute.subst(vcvtFpUIntDRIop); 865 866 vcvtFpSIntSRCode = vfpEnabledCheckCode + ''' 867 FPSCR fpscr = (FPSCR) FpscrExc; 868 VfpSavedState state = prepFpState(fpscr.rMode); 869 vfpFlushToZero(fpscr, FpOp1); 870 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); | 933 __asm__ __volatile__("" :: "m" (result)); 934 finishVfp(fpscr, state, fpscr.fz); 935 FpDestP0_uw = result; 936 FpscrExc = fpscr; 937 ''' 938 vcvtFpUIntDRIop = InstObjParams("vcvtr", "VcvtFpUIntDR", "FpRegRegOp", 939 { "code": vcvtFpUIntDRCode, 940 "predicate_test": predicateTest, 941 "op_class": "SimdFloatCvtOp" }, []) 942 header_output += FpRegRegOpDeclare.subst(vcvtFpUIntDRIop); 943 decoder_output += FpRegRegOpConstructor.subst(vcvtFpUIntDRIop); 944 exec_output += PredOpExecute.subst(vcvtFpUIntDRIop); 945 946 vcvtFpSIntSRCode = vfpEnabledCheckCode + ''' 947 FPSCR fpscr = (FPSCR) FpscrExc; 948 VfpSavedState state = prepFpState(fpscr.rMode); 949 vfpFlushToZero(fpscr, FpOp1); 950 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); |
871 FpDest_sw = vfpFpSToFixed(FpOp1, true, false, 0, false); | 951 FpDest_sw = vfpFpToFixed<float>(FpOp1, true, 32, 0, false); |
872 __asm__ __volatile__("" :: "m" (FpDest_sw)); 873 finishVfp(fpscr, state, fpscr.fz); 874 FpscrExc = fpscr; 875 ''' 876 vcvtFpSIntSRIop = InstObjParams("vcvtr", "VcvtFpSIntSR", "FpRegRegOp", 877 { "code": vcvtFpSIntSRCode, 878 "predicate_test": predicateTest, 879 "op_class": "SimdFloatCvtOp" }, []) 880 header_output += FpRegRegOpDeclare.subst(vcvtFpSIntSRIop); 881 decoder_output += FpRegRegOpConstructor.subst(vcvtFpSIntSRIop); 882 exec_output += PredOpExecute.subst(vcvtFpSIntSRIop); 883 884 vcvtFpSIntDRCode = vfpEnabledCheckCode + ''' 885 FPSCR fpscr = (FPSCR) FpscrExc; 886 double cOp1 = dbl(FpOp1P0_uw, FpOp1P1_uw); 887 vfpFlushToZero(fpscr, cOp1); 888 VfpSavedState state = prepFpState(fpscr.rMode); 889 __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); | 952 __asm__ __volatile__("" :: "m" (FpDest_sw)); 953 finishVfp(fpscr, state, fpscr.fz); 954 FpscrExc = fpscr; 955 ''' 956 vcvtFpSIntSRIop = InstObjParams("vcvtr", "VcvtFpSIntSR", "FpRegRegOp", 957 { "code": vcvtFpSIntSRCode, 958 "predicate_test": predicateTest, 959 "op_class": "SimdFloatCvtOp" }, []) 960 header_output += FpRegRegOpDeclare.subst(vcvtFpSIntSRIop); 961 decoder_output += FpRegRegOpConstructor.subst(vcvtFpSIntSRIop); 962 exec_output += PredOpExecute.subst(vcvtFpSIntSRIop); 963 964 vcvtFpSIntDRCode = vfpEnabledCheckCode + ''' 965 FPSCR fpscr = (FPSCR) FpscrExc; 966 double cOp1 = dbl(FpOp1P0_uw, FpOp1P1_uw); 967 vfpFlushToZero(fpscr, cOp1); 968 VfpSavedState state = prepFpState(fpscr.rMode); 969 __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); |
890 int64_t result = vfpFpDToFixed(cOp1, true, false, 0, false); | 970 int64_t result = vfpFpToFixed<double>(cOp1, true, 32, 0, false); |
891 __asm__ __volatile__("" :: "m" (result)); 892 finishVfp(fpscr, state, fpscr.fz); 893 FpDestP0_uw = result; 894 FpscrExc = fpscr; 895 ''' 896 vcvtFpSIntDRIop = InstObjParams("vcvtr", "VcvtFpSIntDR", "FpRegRegOp", 897 { "code": vcvtFpSIntDRCode, 898 "predicate_test": predicateTest, 899 "op_class": "SimdFloatCvtOp" }, []) 900 header_output += FpRegRegOpDeclare.subst(vcvtFpSIntDRIop); 901 decoder_output += FpRegRegOpConstructor.subst(vcvtFpSIntDRIop); 902 exec_output += PredOpExecute.subst(vcvtFpSIntDRIop); 903 904 vcvtFpUIntSCode = vfpEnabledCheckCode + ''' 905 FPSCR fpscr = (FPSCR) FpscrExc; 906 vfpFlushToZero(fpscr, FpOp1); 907 VfpSavedState state = prepFpState(fpscr.rMode); 908 fesetround(FeRoundZero); 909 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); | 971 __asm__ __volatile__("" :: "m" (result)); 972 finishVfp(fpscr, state, fpscr.fz); 973 FpDestP0_uw = result; 974 FpscrExc = fpscr; 975 ''' 976 vcvtFpSIntDRIop = InstObjParams("vcvtr", "VcvtFpSIntDR", "FpRegRegOp", 977 { "code": vcvtFpSIntDRCode, 978 "predicate_test": predicateTest, 979 "op_class": "SimdFloatCvtOp" }, []) 980 header_output += FpRegRegOpDeclare.subst(vcvtFpSIntDRIop); 981 decoder_output += FpRegRegOpConstructor.subst(vcvtFpSIntDRIop); 982 exec_output += PredOpExecute.subst(vcvtFpSIntDRIop); 983 984 vcvtFpUIntSCode = vfpEnabledCheckCode + ''' 985 FPSCR fpscr = (FPSCR) FpscrExc; 986 vfpFlushToZero(fpscr, FpOp1); 987 VfpSavedState state = prepFpState(fpscr.rMode); 988 fesetround(FeRoundZero); 989 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); |
910 FpDest_uw = vfpFpSToFixed(FpOp1, false, false, 0); | 990 FpDest_uw = vfpFpToFixed<float>(FpOp1, false, 32, 0); |
911 __asm__ __volatile__("" :: "m" (FpDest_uw)); 912 finishVfp(fpscr, state, fpscr.fz); 913 FpscrExc = fpscr; 914 ''' 915 vcvtFpUIntSIop = InstObjParams("vcvt", "VcvtFpUIntS", "FpRegRegOp", 916 { "code": vcvtFpUIntSCode, 917 "predicate_test": predicateTest, 918 "op_class": "SimdFloatCvtOp" }, []) 919 header_output += FpRegRegOpDeclare.subst(vcvtFpUIntSIop); 920 decoder_output += FpRegRegOpConstructor.subst(vcvtFpUIntSIop); 921 exec_output += PredOpExecute.subst(vcvtFpUIntSIop); 922 923 vcvtFpUIntDCode = vfpEnabledCheckCode + ''' 924 FPSCR fpscr = (FPSCR) FpscrExc; 925 double cOp1 = dbl(FpOp1P0_uw, FpOp1P1_uw); 926 vfpFlushToZero(fpscr, cOp1); 927 VfpSavedState state = prepFpState(fpscr.rMode); 928 fesetround(FeRoundZero); 929 __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); | 991 __asm__ __volatile__("" :: "m" (FpDest_uw)); 992 finishVfp(fpscr, state, fpscr.fz); 993 FpscrExc = fpscr; 994 ''' 995 vcvtFpUIntSIop = InstObjParams("vcvt", "VcvtFpUIntS", "FpRegRegOp", 996 { "code": vcvtFpUIntSCode, 997 "predicate_test": predicateTest, 998 "op_class": "SimdFloatCvtOp" }, []) 999 header_output += FpRegRegOpDeclare.subst(vcvtFpUIntSIop); 1000 decoder_output += FpRegRegOpConstructor.subst(vcvtFpUIntSIop); 1001 exec_output += PredOpExecute.subst(vcvtFpUIntSIop); 1002 1003 vcvtFpUIntDCode = vfpEnabledCheckCode + ''' 1004 FPSCR fpscr = (FPSCR) FpscrExc; 1005 double cOp1 = dbl(FpOp1P0_uw, FpOp1P1_uw); 1006 vfpFlushToZero(fpscr, cOp1); 1007 VfpSavedState state = prepFpState(fpscr.rMode); 1008 fesetround(FeRoundZero); 1009 __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); |
930 uint64_t result = vfpFpDToFixed(cOp1, false, false, 0); | 1010 uint64_t result = vfpFpToFixed<double>(cOp1, false, 32, 0); |
931 __asm__ __volatile__("" :: "m" (result)); 932 finishVfp(fpscr, state, fpscr.fz); 933 FpDestP0_uw = result; 934 FpscrExc = fpscr; 935 ''' 936 vcvtFpUIntDIop = InstObjParams("vcvt", "VcvtFpUIntD", "FpRegRegOp", 937 { "code": vcvtFpUIntDCode, 938 "predicate_test": predicateTest, 939 "op_class": "SimdFloatCvtOp" }, []) 940 header_output += FpRegRegOpDeclare.subst(vcvtFpUIntDIop); 941 decoder_output += FpRegRegOpConstructor.subst(vcvtFpUIntDIop); 942 exec_output += PredOpExecute.subst(vcvtFpUIntDIop); 943 944 vcvtFpSIntSCode = vfpEnabledCheckCode + ''' 945 FPSCR fpscr = (FPSCR) FpscrExc; 946 vfpFlushToZero(fpscr, FpOp1); 947 VfpSavedState state = prepFpState(fpscr.rMode); 948 fesetround(FeRoundZero); 949 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); | 1011 __asm__ __volatile__("" :: "m" (result)); 1012 finishVfp(fpscr, state, fpscr.fz); 1013 FpDestP0_uw = result; 1014 FpscrExc = fpscr; 1015 ''' 1016 vcvtFpUIntDIop = InstObjParams("vcvt", "VcvtFpUIntD", "FpRegRegOp", 1017 { "code": vcvtFpUIntDCode, 1018 "predicate_test": predicateTest, 1019 "op_class": "SimdFloatCvtOp" }, []) 1020 header_output += FpRegRegOpDeclare.subst(vcvtFpUIntDIop); 1021 decoder_output += FpRegRegOpConstructor.subst(vcvtFpUIntDIop); 1022 exec_output += PredOpExecute.subst(vcvtFpUIntDIop); 1023 1024 vcvtFpSIntSCode = vfpEnabledCheckCode + ''' 1025 FPSCR fpscr = (FPSCR) FpscrExc; 1026 vfpFlushToZero(fpscr, FpOp1); 1027 VfpSavedState state = prepFpState(fpscr.rMode); 1028 fesetround(FeRoundZero); 1029 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); |
950 FpDest_sw = vfpFpSToFixed(FpOp1, true, false, 0); | 1030 FpDest_sw = vfpFpToFixed<float>(FpOp1, true, 32, 0); |
951 __asm__ __volatile__("" :: "m" (FpDest_sw)); 952 finishVfp(fpscr, state, fpscr.fz); 953 FpscrExc = fpscr; 954 ''' 955 vcvtFpSIntSIop = InstObjParams("vcvt", "VcvtFpSIntS", "FpRegRegOp", 956 { "code": vcvtFpSIntSCode, 957 "predicate_test": predicateTest, 958 "op_class": "SimdFloatCvtOp" }, []) 959 header_output += FpRegRegOpDeclare.subst(vcvtFpSIntSIop); 960 decoder_output += FpRegRegOpConstructor.subst(vcvtFpSIntSIop); 961 exec_output += PredOpExecute.subst(vcvtFpSIntSIop); 962 963 vcvtFpSIntDCode = vfpEnabledCheckCode + ''' 964 FPSCR fpscr = (FPSCR) FpscrExc; 965 double cOp1 = dbl(FpOp1P0_uw, FpOp1P1_uw); 966 vfpFlushToZero(fpscr, cOp1); 967 VfpSavedState state = prepFpState(fpscr.rMode); 968 fesetround(FeRoundZero); 969 __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); | 1031 __asm__ __volatile__("" :: "m" (FpDest_sw)); 1032 finishVfp(fpscr, state, fpscr.fz); 1033 FpscrExc = fpscr; 1034 ''' 1035 vcvtFpSIntSIop = InstObjParams("vcvt", "VcvtFpSIntS", "FpRegRegOp", 1036 { "code": vcvtFpSIntSCode, 1037 "predicate_test": predicateTest, 1038 "op_class": "SimdFloatCvtOp" }, []) 1039 header_output += FpRegRegOpDeclare.subst(vcvtFpSIntSIop); 1040 decoder_output += FpRegRegOpConstructor.subst(vcvtFpSIntSIop); 1041 exec_output += PredOpExecute.subst(vcvtFpSIntSIop); 1042 1043 vcvtFpSIntDCode = vfpEnabledCheckCode + ''' 1044 FPSCR fpscr = (FPSCR) FpscrExc; 1045 double cOp1 = dbl(FpOp1P0_uw, FpOp1P1_uw); 1046 vfpFlushToZero(fpscr, cOp1); 1047 VfpSavedState state = prepFpState(fpscr.rMode); 1048 fesetround(FeRoundZero); 1049 __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); |
970 int64_t result = vfpFpDToFixed(cOp1, true, false, 0); | 1050 int64_t result = vfpFpToFixed<double>(cOp1, true, 32, 0); |
971 __asm__ __volatile__("" :: "m" (result)); 972 finishVfp(fpscr, state, fpscr.fz); 973 FpDestP0_uw = result; 974 FpscrExc = fpscr; 975 ''' 976 vcvtFpSIntDIop = InstObjParams("vcvt", "VcvtFpSIntD", "FpRegRegOp", 977 { "code": vcvtFpSIntDCode, 978 "predicate_test": predicateTest, --- 349 unchanged lines hidden (view full) --- 1328 decoder_output = "" 1329 exec_output = "" 1330 1331 vcvtFpSFixedSCode = vfpEnabledCheckCode + ''' 1332 FPSCR fpscr = (FPSCR) FpscrExc; 1333 vfpFlushToZero(fpscr, FpOp1); 1334 VfpSavedState state = prepFpState(fpscr.rMode); 1335 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); | 1051 __asm__ __volatile__("" :: "m" (result)); 1052 finishVfp(fpscr, state, fpscr.fz); 1053 FpDestP0_uw = result; 1054 FpscrExc = fpscr; 1055 ''' 1056 vcvtFpSIntDIop = InstObjParams("vcvt", "VcvtFpSIntD", "FpRegRegOp", 1057 { "code": vcvtFpSIntDCode, 1058 "predicate_test": predicateTest, --- 349 unchanged lines hidden (view full) --- 1408 decoder_output = "" 1409 exec_output = "" 1410 1411 vcvtFpSFixedSCode = vfpEnabledCheckCode + ''' 1412 FPSCR fpscr = (FPSCR) FpscrExc; 1413 vfpFlushToZero(fpscr, FpOp1); 1414 VfpSavedState state = prepFpState(fpscr.rMode); 1415 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); |
1336 FpDest_sw = vfpFpSToFixed(FpOp1, true, false, imm); | 1416 FpDest_sw = vfpFpToFixed<float>(FpOp1, true, 32, imm); |
1337 __asm__ __volatile__("" :: "m" (FpDest_sw)); 1338 finishVfp(fpscr, state, fpscr.fz); 1339 FpscrExc = fpscr; 1340 ''' 1341 vcvtFpSFixedSIop = InstObjParams("vcvt", "VcvtFpSFixedS", "FpRegRegImmOp", 1342 { "code": vcvtFpSFixedSCode, 1343 "predicate_test": predicateTest, 1344 "op_class": "SimdFloatCvtOp" }, []) 1345 header_output += FpRegRegImmOpDeclare.subst(vcvtFpSFixedSIop); 1346 decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpSFixedSIop); 1347 exec_output += PredOpExecute.subst(vcvtFpSFixedSIop); 1348 1349 vcvtFpSFixedDCode = vfpEnabledCheckCode + ''' 1350 FPSCR fpscr = (FPSCR) FpscrExc; 1351 double cOp1 = dbl(FpOp1P0_uw, FpOp1P1_uw); 1352 vfpFlushToZero(fpscr, cOp1); 1353 VfpSavedState state = prepFpState(fpscr.rMode); 1354 __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); | 1417 __asm__ __volatile__("" :: "m" (FpDest_sw)); 1418 finishVfp(fpscr, state, fpscr.fz); 1419 FpscrExc = fpscr; 1420 ''' 1421 vcvtFpSFixedSIop = InstObjParams("vcvt", "VcvtFpSFixedS", "FpRegRegImmOp", 1422 { "code": vcvtFpSFixedSCode, 1423 "predicate_test": predicateTest, 1424 "op_class": "SimdFloatCvtOp" }, []) 1425 header_output += FpRegRegImmOpDeclare.subst(vcvtFpSFixedSIop); 1426 decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpSFixedSIop); 1427 exec_output += PredOpExecute.subst(vcvtFpSFixedSIop); 1428 1429 vcvtFpSFixedDCode = vfpEnabledCheckCode + ''' 1430 FPSCR fpscr = (FPSCR) FpscrExc; 1431 double cOp1 = dbl(FpOp1P0_uw, FpOp1P1_uw); 1432 vfpFlushToZero(fpscr, cOp1); 1433 VfpSavedState state = prepFpState(fpscr.rMode); 1434 __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); |
1355 uint64_t mid = vfpFpDToFixed(cOp1, true, false, imm); | 1435 uint64_t mid = vfpFpToFixed<double>(cOp1, true, 32, imm); |
1356 __asm__ __volatile__("" :: "m" (mid)); 1357 finishVfp(fpscr, state, fpscr.fz); 1358 FpDestP0_uw = mid; 1359 FpDestP1_uw = mid >> 32; 1360 FpscrExc = fpscr; 1361 ''' 1362 vcvtFpSFixedDIop = InstObjParams("vcvt", "VcvtFpSFixedD", "FpRegRegImmOp", 1363 { "code": vcvtFpSFixedDCode, 1364 "predicate_test": predicateTest, 1365 "op_class": "SimdFloatCvtOp" }, []) 1366 header_output += FpRegRegImmOpDeclare.subst(vcvtFpSFixedDIop); 1367 decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpSFixedDIop); 1368 exec_output += PredOpExecute.subst(vcvtFpSFixedDIop); 1369 1370 vcvtFpUFixedSCode = vfpEnabledCheckCode + ''' 1371 FPSCR fpscr = (FPSCR) FpscrExc; 1372 vfpFlushToZero(fpscr, FpOp1); 1373 VfpSavedState state = prepFpState(fpscr.rMode); 1374 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); | 1436 __asm__ __volatile__("" :: "m" (mid)); 1437 finishVfp(fpscr, state, fpscr.fz); 1438 FpDestP0_uw = mid; 1439 FpDestP1_uw = mid >> 32; 1440 FpscrExc = fpscr; 1441 ''' 1442 vcvtFpSFixedDIop = InstObjParams("vcvt", "VcvtFpSFixedD", "FpRegRegImmOp", 1443 { "code": vcvtFpSFixedDCode, 1444 "predicate_test": predicateTest, 1445 "op_class": "SimdFloatCvtOp" }, []) 1446 header_output += FpRegRegImmOpDeclare.subst(vcvtFpSFixedDIop); 1447 decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpSFixedDIop); 1448 exec_output += PredOpExecute.subst(vcvtFpSFixedDIop); 1449 1450 vcvtFpUFixedSCode = vfpEnabledCheckCode + ''' 1451 FPSCR fpscr = (FPSCR) FpscrExc; 1452 vfpFlushToZero(fpscr, FpOp1); 1453 VfpSavedState state = prepFpState(fpscr.rMode); 1454 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); |
1375 FpDest_uw = vfpFpSToFixed(FpOp1, false, false, imm); | 1455 FpDest_uw = vfpFpToFixed<float>(FpOp1, false, 32, imm); |
1376 __asm__ __volatile__("" :: "m" (FpDest_uw)); 1377 finishVfp(fpscr, state, fpscr.fz); 1378 FpscrExc = fpscr; 1379 ''' 1380 vcvtFpUFixedSIop = InstObjParams("vcvt", "VcvtFpUFixedS", "FpRegRegImmOp", 1381 { "code": vcvtFpUFixedSCode, 1382 "predicate_test": predicateTest, 1383 "op_class": "SimdFloatCvtOp" }, []) 1384 header_output += FpRegRegImmOpDeclare.subst(vcvtFpUFixedSIop); 1385 decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpUFixedSIop); 1386 exec_output += PredOpExecute.subst(vcvtFpUFixedSIop); 1387 1388 vcvtFpUFixedDCode = vfpEnabledCheckCode + ''' 1389 FPSCR fpscr = (FPSCR) FpscrExc; 1390 double cOp1 = dbl(FpOp1P0_uw, FpOp1P1_uw); 1391 vfpFlushToZero(fpscr, cOp1); 1392 VfpSavedState state = prepFpState(fpscr.rMode); 1393 __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); | 1456 __asm__ __volatile__("" :: "m" (FpDest_uw)); 1457 finishVfp(fpscr, state, fpscr.fz); 1458 FpscrExc = fpscr; 1459 ''' 1460 vcvtFpUFixedSIop = InstObjParams("vcvt", "VcvtFpUFixedS", "FpRegRegImmOp", 1461 { "code": vcvtFpUFixedSCode, 1462 "predicate_test": predicateTest, 1463 "op_class": "SimdFloatCvtOp" }, []) 1464 header_output += FpRegRegImmOpDeclare.subst(vcvtFpUFixedSIop); 1465 decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpUFixedSIop); 1466 exec_output += PredOpExecute.subst(vcvtFpUFixedSIop); 1467 1468 vcvtFpUFixedDCode = vfpEnabledCheckCode + ''' 1469 FPSCR fpscr = (FPSCR) FpscrExc; 1470 double cOp1 = dbl(FpOp1P0_uw, FpOp1P1_uw); 1471 vfpFlushToZero(fpscr, cOp1); 1472 VfpSavedState state = prepFpState(fpscr.rMode); 1473 __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); |
1394 uint64_t mid = vfpFpDToFixed(cOp1, false, false, imm); | 1474 uint64_t mid = vfpFpToFixed<double>(cOp1, false, 32, imm); |
1395 __asm__ __volatile__("" :: "m" (mid)); 1396 finishVfp(fpscr, state, fpscr.fz); 1397 FpDestP0_uw = mid; 1398 FpDestP1_uw = mid >> 32; 1399 FpscrExc = fpscr; 1400 ''' 1401 vcvtFpUFixedDIop = InstObjParams("vcvt", "VcvtFpUFixedD", "FpRegRegImmOp", 1402 { "code": vcvtFpUFixedDCode, 1403 "predicate_test": predicateTest, 1404 "op_class": "SimdFloatCvtOp" }, []) 1405 header_output += FpRegRegImmOpDeclare.subst(vcvtFpUFixedDIop); 1406 decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpUFixedDIop); 1407 exec_output += PredOpExecute.subst(vcvtFpUFixedDIop); 1408 1409 vcvtSFixedFpSCode = vfpEnabledCheckCode + ''' 1410 FPSCR fpscr = (FPSCR) FpscrExc; 1411 VfpSavedState state = prepFpState(fpscr.rMode); 1412 __asm__ __volatile__("" : "=m" (FpOp1_sw) : "m" (FpOp1_sw)); | 1475 __asm__ __volatile__("" :: "m" (mid)); 1476 finishVfp(fpscr, state, fpscr.fz); 1477 FpDestP0_uw = mid; 1478 FpDestP1_uw = mid >> 32; 1479 FpscrExc = fpscr; 1480 ''' 1481 vcvtFpUFixedDIop = InstObjParams("vcvt", "VcvtFpUFixedD", "FpRegRegImmOp", 1482 { "code": vcvtFpUFixedDCode, 1483 "predicate_test": predicateTest, 1484 "op_class": "SimdFloatCvtOp" }, []) 1485 header_output += FpRegRegImmOpDeclare.subst(vcvtFpUFixedDIop); 1486 decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpUFixedDIop); 1487 exec_output += PredOpExecute.subst(vcvtFpUFixedDIop); 1488 1489 vcvtSFixedFpSCode = vfpEnabledCheckCode + ''' 1490 FPSCR fpscr = (FPSCR) FpscrExc; 1491 VfpSavedState state = prepFpState(fpscr.rMode); 1492 __asm__ __volatile__("" : "=m" (FpOp1_sw) : "m" (FpOp1_sw)); |
1413 FpDest = vfpSFixedToFpS(fpscr.fz, fpscr.dn, FpOp1_sw, false, imm); | 1493 FpDest = vfpSFixedToFpS(fpscr.fz, fpscr.dn, FpOp1_sw, 32, imm); |
1414 __asm__ __volatile__("" :: "m" (FpDest)); 1415 finishVfp(fpscr, state, fpscr.fz); 1416 FpscrExc = fpscr; 1417 ''' 1418 vcvtSFixedFpSIop = InstObjParams("vcvt", "VcvtSFixedFpS", "FpRegRegImmOp", 1419 { "code": vcvtSFixedFpSCode, 1420 "predicate_test": predicateTest, 1421 "op_class": "SimdFloatCvtOp" }, []) 1422 header_output += FpRegRegImmOpDeclare.subst(vcvtSFixedFpSIop); 1423 decoder_output += FpRegRegImmOpConstructor.subst(vcvtSFixedFpSIop); 1424 exec_output += PredOpExecute.subst(vcvtSFixedFpSIop); 1425 1426 vcvtSFixedFpDCode = vfpEnabledCheckCode + ''' 1427 FPSCR fpscr = (FPSCR) FpscrExc; 1428 uint64_t mid = ((uint64_t)FpOp1P0_uw | ((uint64_t)FpOp1P1_uw << 32)); 1429 VfpSavedState state = prepFpState(fpscr.rMode); 1430 __asm__ __volatile__("" : "=m" (mid) : "m" (mid)); | 1494 __asm__ __volatile__("" :: "m" (FpDest)); 1495 finishVfp(fpscr, state, fpscr.fz); 1496 FpscrExc = fpscr; 1497 ''' 1498 vcvtSFixedFpSIop = InstObjParams("vcvt", "VcvtSFixedFpS", "FpRegRegImmOp", 1499 { "code": vcvtSFixedFpSCode, 1500 "predicate_test": predicateTest, 1501 "op_class": "SimdFloatCvtOp" }, []) 1502 header_output += FpRegRegImmOpDeclare.subst(vcvtSFixedFpSIop); 1503 decoder_output += FpRegRegImmOpConstructor.subst(vcvtSFixedFpSIop); 1504 exec_output += PredOpExecute.subst(vcvtSFixedFpSIop); 1505 1506 vcvtSFixedFpDCode = vfpEnabledCheckCode + ''' 1507 FPSCR fpscr = (FPSCR) FpscrExc; 1508 uint64_t mid = ((uint64_t)FpOp1P0_uw | ((uint64_t)FpOp1P1_uw << 32)); 1509 VfpSavedState state = prepFpState(fpscr.rMode); 1510 __asm__ __volatile__("" : "=m" (mid) : "m" (mid)); |
1431 double cDest = vfpSFixedToFpD(fpscr.fz, fpscr.dn, mid, false, imm); | 1511 double cDest = vfpSFixedToFpD(fpscr.fz, fpscr.dn, mid, 32, imm); |
1432 __asm__ __volatile__("" :: "m" (cDest)); 1433 finishVfp(fpscr, state, fpscr.fz); 1434 FpDestP0_uw = dblLow(cDest); 1435 FpDestP1_uw = dblHi(cDest); 1436 FpscrExc = fpscr; 1437 ''' 1438 vcvtSFixedFpDIop = InstObjParams("vcvt", "VcvtSFixedFpD", "FpRegRegImmOp", 1439 { "code": vcvtSFixedFpDCode, 1440 "predicate_test": predicateTest, 1441 "op_class": "SimdFloatCvtOp" }, []) 1442 header_output += FpRegRegImmOpDeclare.subst(vcvtSFixedFpDIop); 1443 decoder_output += FpRegRegImmOpConstructor.subst(vcvtSFixedFpDIop); 1444 exec_output += PredOpExecute.subst(vcvtSFixedFpDIop); 1445 1446 vcvtUFixedFpSCode = vfpEnabledCheckCode + ''' 1447 FPSCR fpscr = (FPSCR) FpscrExc; 1448 VfpSavedState state = prepFpState(fpscr.rMode); 1449 __asm__ __volatile__("" : "=m" (FpOp1_uw) : "m" (FpOp1_uw)); | 1512 __asm__ __volatile__("" :: "m" (cDest)); 1513 finishVfp(fpscr, state, fpscr.fz); 1514 FpDestP0_uw = dblLow(cDest); 1515 FpDestP1_uw = dblHi(cDest); 1516 FpscrExc = fpscr; 1517 ''' 1518 vcvtSFixedFpDIop = InstObjParams("vcvt", "VcvtSFixedFpD", "FpRegRegImmOp", 1519 { "code": vcvtSFixedFpDCode, 1520 "predicate_test": predicateTest, 1521 "op_class": "SimdFloatCvtOp" }, []) 1522 header_output += FpRegRegImmOpDeclare.subst(vcvtSFixedFpDIop); 1523 decoder_output += FpRegRegImmOpConstructor.subst(vcvtSFixedFpDIop); 1524 exec_output += PredOpExecute.subst(vcvtSFixedFpDIop); 1525 1526 vcvtUFixedFpSCode = vfpEnabledCheckCode + ''' 1527 FPSCR fpscr = (FPSCR) FpscrExc; 1528 VfpSavedState state = prepFpState(fpscr.rMode); 1529 __asm__ __volatile__("" : "=m" (FpOp1_uw) : "m" (FpOp1_uw)); |
1450 FpDest = vfpUFixedToFpS(fpscr.fz, fpscr.dn, FpOp1_uw, false, imm); | 1530 FpDest = vfpUFixedToFpS(fpscr.fz, fpscr.dn, FpOp1_uw, 32, imm); |
1451 __asm__ __volatile__("" :: "m" (FpDest)); 1452 finishVfp(fpscr, state, fpscr.fz); 1453 FpscrExc = fpscr; 1454 ''' 1455 vcvtUFixedFpSIop = InstObjParams("vcvt", "VcvtUFixedFpS", "FpRegRegImmOp", 1456 { "code": vcvtUFixedFpSCode, 1457 "predicate_test": predicateTest, 1458 "op_class": "SimdFloatCvtOp" }, []) 1459 header_output += FpRegRegImmOpDeclare.subst(vcvtUFixedFpSIop); 1460 decoder_output += FpRegRegImmOpConstructor.subst(vcvtUFixedFpSIop); 1461 exec_output += PredOpExecute.subst(vcvtUFixedFpSIop); 1462 1463 vcvtUFixedFpDCode = vfpEnabledCheckCode + ''' 1464 FPSCR fpscr = (FPSCR) FpscrExc; 1465 uint64_t mid = ((uint64_t)FpOp1P0_uw | ((uint64_t)FpOp1P1_uw << 32)); 1466 VfpSavedState state = prepFpState(fpscr.rMode); 1467 __asm__ __volatile__("" : "=m" (mid) : "m" (mid)); | 1531 __asm__ __volatile__("" :: "m" (FpDest)); 1532 finishVfp(fpscr, state, fpscr.fz); 1533 FpscrExc = fpscr; 1534 ''' 1535 vcvtUFixedFpSIop = InstObjParams("vcvt", "VcvtUFixedFpS", "FpRegRegImmOp", 1536 { "code": vcvtUFixedFpSCode, 1537 "predicate_test": predicateTest, 1538 "op_class": "SimdFloatCvtOp" }, []) 1539 header_output += FpRegRegImmOpDeclare.subst(vcvtUFixedFpSIop); 1540 decoder_output += FpRegRegImmOpConstructor.subst(vcvtUFixedFpSIop); 1541 exec_output += PredOpExecute.subst(vcvtUFixedFpSIop); 1542 1543 vcvtUFixedFpDCode = vfpEnabledCheckCode + ''' 1544 FPSCR fpscr = (FPSCR) FpscrExc; 1545 uint64_t mid = ((uint64_t)FpOp1P0_uw | ((uint64_t)FpOp1P1_uw << 32)); 1546 VfpSavedState state = prepFpState(fpscr.rMode); 1547 __asm__ __volatile__("" : "=m" (mid) : "m" (mid)); |
1468 double cDest = vfpUFixedToFpD(fpscr.fz, fpscr.dn, mid, false, imm); | 1548 double cDest = vfpUFixedToFpD(fpscr.fz, fpscr.dn, mid, 32, imm); |
1469 __asm__ __volatile__("" :: "m" (cDest)); 1470 finishVfp(fpscr, state, fpscr.fz); 1471 FpDestP0_uw = dblLow(cDest); 1472 FpDestP1_uw = dblHi(cDest); 1473 FpscrExc = fpscr; 1474 ''' 1475 vcvtUFixedFpDIop = InstObjParams("vcvt", "VcvtUFixedFpD", "FpRegRegImmOp", 1476 { "code": vcvtUFixedFpDCode, 1477 "predicate_test": predicateTest, 1478 "op_class": "SimdFloatCvtOp" }, []) 1479 header_output += FpRegRegImmOpDeclare.subst(vcvtUFixedFpDIop); 1480 decoder_output += FpRegRegImmOpConstructor.subst(vcvtUFixedFpDIop); 1481 exec_output += PredOpExecute.subst(vcvtUFixedFpDIop); 1482 1483 vcvtFpSHFixedSCode = vfpEnabledCheckCode + ''' 1484 FPSCR fpscr = (FPSCR) FpscrExc; 1485 vfpFlushToZero(fpscr, FpOp1); 1486 VfpSavedState state = prepFpState(fpscr.rMode); 1487 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); | 1549 __asm__ __volatile__("" :: "m" (cDest)); 1550 finishVfp(fpscr, state, fpscr.fz); 1551 FpDestP0_uw = dblLow(cDest); 1552 FpDestP1_uw = dblHi(cDest); 1553 FpscrExc = fpscr; 1554 ''' 1555 vcvtUFixedFpDIop = InstObjParams("vcvt", "VcvtUFixedFpD", "FpRegRegImmOp", 1556 { "code": vcvtUFixedFpDCode, 1557 "predicate_test": predicateTest, 1558 "op_class": "SimdFloatCvtOp" }, []) 1559 header_output += FpRegRegImmOpDeclare.subst(vcvtUFixedFpDIop); 1560 decoder_output += FpRegRegImmOpConstructor.subst(vcvtUFixedFpDIop); 1561 exec_output += PredOpExecute.subst(vcvtUFixedFpDIop); 1562 1563 vcvtFpSHFixedSCode = vfpEnabledCheckCode + ''' 1564 FPSCR fpscr = (FPSCR) FpscrExc; 1565 vfpFlushToZero(fpscr, FpOp1); 1566 VfpSavedState state = prepFpState(fpscr.rMode); 1567 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); |
1488 FpDest_sh = vfpFpSToFixed(FpOp1, true, true, imm); | 1568 FpDest_sh = vfpFpToFixed<float>(FpOp1, true, 16, imm); |
1489 __asm__ __volatile__("" :: "m" (FpDest_sh)); 1490 finishVfp(fpscr, state, fpscr.fz); 1491 FpscrExc = fpscr; 1492 ''' 1493 vcvtFpSHFixedSIop = InstObjParams("vcvt", "VcvtFpSHFixedS", 1494 "FpRegRegImmOp", 1495 { "code": vcvtFpSHFixedSCode, 1496 "predicate_test": predicateTest, 1497 "op_class": "SimdFloatCvtOp" }, []) 1498 header_output += FpRegRegImmOpDeclare.subst(vcvtFpSHFixedSIop); 1499 decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpSHFixedSIop); 1500 exec_output += PredOpExecute.subst(vcvtFpSHFixedSIop); 1501 1502 vcvtFpSHFixedDCode = vfpEnabledCheckCode + ''' 1503 FPSCR fpscr = (FPSCR) FpscrExc; 1504 double cOp1 = dbl(FpOp1P0_uw, FpOp1P1_uw); 1505 vfpFlushToZero(fpscr, cOp1); 1506 VfpSavedState state = prepFpState(fpscr.rMode); 1507 __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); | 1569 __asm__ __volatile__("" :: "m" (FpDest_sh)); 1570 finishVfp(fpscr, state, fpscr.fz); 1571 FpscrExc = fpscr; 1572 ''' 1573 vcvtFpSHFixedSIop = InstObjParams("vcvt", "VcvtFpSHFixedS", 1574 "FpRegRegImmOp", 1575 { "code": vcvtFpSHFixedSCode, 1576 "predicate_test": predicateTest, 1577 "op_class": "SimdFloatCvtOp" }, []) 1578 header_output += FpRegRegImmOpDeclare.subst(vcvtFpSHFixedSIop); 1579 decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpSHFixedSIop); 1580 exec_output += PredOpExecute.subst(vcvtFpSHFixedSIop); 1581 1582 vcvtFpSHFixedDCode = vfpEnabledCheckCode + ''' 1583 FPSCR fpscr = (FPSCR) FpscrExc; 1584 double cOp1 = dbl(FpOp1P0_uw, FpOp1P1_uw); 1585 vfpFlushToZero(fpscr, cOp1); 1586 VfpSavedState state = prepFpState(fpscr.rMode); 1587 __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); |
1508 uint64_t result = vfpFpDToFixed(cOp1, true, true, imm); | 1588 uint64_t result = vfpFpToFixed<double>(cOp1, true, 16, imm); |
1509 __asm__ __volatile__("" :: "m" (result)); 1510 finishVfp(fpscr, state, fpscr.fz); 1511 FpDestP0_uw = result; 1512 FpDestP1_uw = result >> 32; 1513 FpscrExc = fpscr; 1514 ''' 1515 vcvtFpSHFixedDIop = InstObjParams("vcvt", "VcvtFpSHFixedD", 1516 "FpRegRegImmOp", --- 4 unchanged lines hidden (view full) --- 1521 decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpSHFixedDIop); 1522 exec_output += PredOpExecute.subst(vcvtFpSHFixedDIop); 1523 1524 vcvtFpUHFixedSCode = vfpEnabledCheckCode + ''' 1525 FPSCR fpscr = (FPSCR) FpscrExc; 1526 vfpFlushToZero(fpscr, FpOp1); 1527 VfpSavedState state = prepFpState(fpscr.rMode); 1528 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); | 1589 __asm__ __volatile__("" :: "m" (result)); 1590 finishVfp(fpscr, state, fpscr.fz); 1591 FpDestP0_uw = result; 1592 FpDestP1_uw = result >> 32; 1593 FpscrExc = fpscr; 1594 ''' 1595 vcvtFpSHFixedDIop = InstObjParams("vcvt", "VcvtFpSHFixedD", 1596 "FpRegRegImmOp", --- 4 unchanged lines hidden (view full) --- 1601 decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpSHFixedDIop); 1602 exec_output += PredOpExecute.subst(vcvtFpSHFixedDIop); 1603 1604 vcvtFpUHFixedSCode = vfpEnabledCheckCode + ''' 1605 FPSCR fpscr = (FPSCR) FpscrExc; 1606 vfpFlushToZero(fpscr, FpOp1); 1607 VfpSavedState state = prepFpState(fpscr.rMode); 1608 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); |
1529 FpDest_uh = vfpFpSToFixed(FpOp1, false, true, imm); | 1609 FpDest_uh = vfpFpToFixed<float>(FpOp1, false, 16, imm); |
1530 __asm__ __volatile__("" :: "m" (FpDest_uh)); 1531 finishVfp(fpscr, state, fpscr.fz); 1532 FpscrExc = fpscr; 1533 ''' 1534 vcvtFpUHFixedSIop = InstObjParams("vcvt", "VcvtFpUHFixedS", 1535 "FpRegRegImmOp", 1536 { "code": vcvtFpUHFixedSCode, 1537 "predicate_test": predicateTest, 1538 "op_class": "SimdFloatCvtOp" }, []) 1539 header_output += FpRegRegImmOpDeclare.subst(vcvtFpUHFixedSIop); 1540 decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpUHFixedSIop); 1541 exec_output += PredOpExecute.subst(vcvtFpUHFixedSIop); 1542 1543 vcvtFpUHFixedDCode = vfpEnabledCheckCode + ''' 1544 FPSCR fpscr = (FPSCR) FpscrExc; 1545 double cOp1 = dbl(FpOp1P0_uw, FpOp1P1_uw); 1546 vfpFlushToZero(fpscr, cOp1); 1547 VfpSavedState state = prepFpState(fpscr.rMode); 1548 __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); | 1610 __asm__ __volatile__("" :: "m" (FpDest_uh)); 1611 finishVfp(fpscr, state, fpscr.fz); 1612 FpscrExc = fpscr; 1613 ''' 1614 vcvtFpUHFixedSIop = InstObjParams("vcvt", "VcvtFpUHFixedS", 1615 "FpRegRegImmOp", 1616 { "code": vcvtFpUHFixedSCode, 1617 "predicate_test": predicateTest, 1618 "op_class": "SimdFloatCvtOp" }, []) 1619 header_output += FpRegRegImmOpDeclare.subst(vcvtFpUHFixedSIop); 1620 decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpUHFixedSIop); 1621 exec_output += PredOpExecute.subst(vcvtFpUHFixedSIop); 1622 1623 vcvtFpUHFixedDCode = vfpEnabledCheckCode + ''' 1624 FPSCR fpscr = (FPSCR) FpscrExc; 1625 double cOp1 = dbl(FpOp1P0_uw, FpOp1P1_uw); 1626 vfpFlushToZero(fpscr, cOp1); 1627 VfpSavedState state = prepFpState(fpscr.rMode); 1628 __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); |
1549 uint64_t mid = vfpFpDToFixed(cOp1, false, true, imm); | 1629 uint64_t mid = vfpFpToFixed<double>(cOp1, false, 16, imm); |
1550 __asm__ __volatile__("" :: "m" (mid)); 1551 finishVfp(fpscr, state, fpscr.fz); 1552 FpDestP0_uw = mid; 1553 FpDestP1_uw = mid >> 32; 1554 FpscrExc = fpscr; 1555 ''' 1556 vcvtFpUHFixedDIop = InstObjParams("vcvt", "VcvtFpUHFixedD", 1557 "FpRegRegImmOp", 1558 { "code": vcvtFpUHFixedDCode, 1559 "predicate_test": predicateTest, 1560 "op_class": "SimdFloatCvtOp" }, []) 1561 header_output += FpRegRegImmOpDeclare.subst(vcvtFpUHFixedDIop); 1562 decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpUHFixedDIop); 1563 exec_output += PredOpExecute.subst(vcvtFpUHFixedDIop); 1564 1565 vcvtSHFixedFpSCode = vfpEnabledCheckCode + ''' 1566 FPSCR fpscr = (FPSCR) FpscrExc; 1567 VfpSavedState state = prepFpState(fpscr.rMode); 1568 __asm__ __volatile__("" : "=m" (FpOp1_sh) : "m" (FpOp1_sh)); | 1630 __asm__ __volatile__("" :: "m" (mid)); 1631 finishVfp(fpscr, state, fpscr.fz); 1632 FpDestP0_uw = mid; 1633 FpDestP1_uw = mid >> 32; 1634 FpscrExc = fpscr; 1635 ''' 1636 vcvtFpUHFixedDIop = InstObjParams("vcvt", "VcvtFpUHFixedD", 1637 "FpRegRegImmOp", 1638 { "code": vcvtFpUHFixedDCode, 1639 "predicate_test": predicateTest, 1640 "op_class": "SimdFloatCvtOp" }, []) 1641 header_output += FpRegRegImmOpDeclare.subst(vcvtFpUHFixedDIop); 1642 decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpUHFixedDIop); 1643 exec_output += PredOpExecute.subst(vcvtFpUHFixedDIop); 1644 1645 vcvtSHFixedFpSCode = vfpEnabledCheckCode + ''' 1646 FPSCR fpscr = (FPSCR) FpscrExc; 1647 VfpSavedState state = prepFpState(fpscr.rMode); 1648 __asm__ __volatile__("" : "=m" (FpOp1_sh) : "m" (FpOp1_sh)); |
1569 FpDest = vfpSFixedToFpS(fpscr.fz, fpscr.dn, FpOp1_sh, true, imm); | 1649 FpDest = vfpSFixedToFpS(fpscr.fz, fpscr.dn, FpOp1_sh, 16, imm); |
1570 __asm__ __volatile__("" :: "m" (FpDest)); 1571 finishVfp(fpscr, state, fpscr.fz); 1572 FpscrExc = fpscr; 1573 ''' 1574 vcvtSHFixedFpSIop = InstObjParams("vcvt", "VcvtSHFixedFpS", 1575 "FpRegRegImmOp", 1576 { "code": vcvtSHFixedFpSCode, 1577 "predicate_test": predicateTest, 1578 "op_class": "SimdFloatCvtOp" }, []) 1579 header_output += FpRegRegImmOpDeclare.subst(vcvtSHFixedFpSIop); 1580 decoder_output += FpRegRegImmOpConstructor.subst(vcvtSHFixedFpSIop); 1581 exec_output += PredOpExecute.subst(vcvtSHFixedFpSIop); 1582 1583 vcvtSHFixedFpDCode = vfpEnabledCheckCode + ''' 1584 FPSCR fpscr = (FPSCR) FpscrExc; 1585 uint64_t mid = ((uint64_t)FpOp1P0_uw | ((uint64_t)FpOp1P1_uw << 32)); 1586 VfpSavedState state = prepFpState(fpscr.rMode); 1587 __asm__ __volatile__("" : "=m" (mid) : "m" (mid)); | 1650 __asm__ __volatile__("" :: "m" (FpDest)); 1651 finishVfp(fpscr, state, fpscr.fz); 1652 FpscrExc = fpscr; 1653 ''' 1654 vcvtSHFixedFpSIop = InstObjParams("vcvt", "VcvtSHFixedFpS", 1655 "FpRegRegImmOp", 1656 { "code": vcvtSHFixedFpSCode, 1657 "predicate_test": predicateTest, 1658 "op_class": "SimdFloatCvtOp" }, []) 1659 header_output += FpRegRegImmOpDeclare.subst(vcvtSHFixedFpSIop); 1660 decoder_output += FpRegRegImmOpConstructor.subst(vcvtSHFixedFpSIop); 1661 exec_output += PredOpExecute.subst(vcvtSHFixedFpSIop); 1662 1663 vcvtSHFixedFpDCode = vfpEnabledCheckCode + ''' 1664 FPSCR fpscr = (FPSCR) FpscrExc; 1665 uint64_t mid = ((uint64_t)FpOp1P0_uw | ((uint64_t)FpOp1P1_uw << 32)); 1666 VfpSavedState state = prepFpState(fpscr.rMode); 1667 __asm__ __volatile__("" : "=m" (mid) : "m" (mid)); |
1588 double cDest = vfpSFixedToFpD(fpscr.fz, fpscr.dn, mid, true, imm); | 1668 double cDest = vfpSFixedToFpD(fpscr.fz, fpscr.dn, mid, 16, imm); |
1589 __asm__ __volatile__("" :: "m" (cDest)); 1590 finishVfp(fpscr, state, fpscr.fz); 1591 FpDestP0_uw = dblLow(cDest); 1592 FpDestP1_uw = dblHi(cDest); 1593 FpscrExc = fpscr; 1594 ''' 1595 vcvtSHFixedFpDIop = InstObjParams("vcvt", "VcvtSHFixedFpD", 1596 "FpRegRegImmOp", 1597 { "code": vcvtSHFixedFpDCode, 1598 "predicate_test": predicateTest, 1599 "op_class": "SimdFloatCvtOp" }, []) 1600 header_output += FpRegRegImmOpDeclare.subst(vcvtSHFixedFpDIop); 1601 decoder_output += FpRegRegImmOpConstructor.subst(vcvtSHFixedFpDIop); 1602 exec_output += PredOpExecute.subst(vcvtSHFixedFpDIop); 1603 1604 vcvtUHFixedFpSCode = vfpEnabledCheckCode + ''' 1605 FPSCR fpscr = (FPSCR) FpscrExc; 1606 VfpSavedState state = prepFpState(fpscr.rMode); 1607 __asm__ __volatile__("" : "=m" (FpOp1_uh) : "m" (FpOp1_uh)); | 1669 __asm__ __volatile__("" :: "m" (cDest)); 1670 finishVfp(fpscr, state, fpscr.fz); 1671 FpDestP0_uw = dblLow(cDest); 1672 FpDestP1_uw = dblHi(cDest); 1673 FpscrExc = fpscr; 1674 ''' 1675 vcvtSHFixedFpDIop = InstObjParams("vcvt", "VcvtSHFixedFpD", 1676 "FpRegRegImmOp", 1677 { "code": vcvtSHFixedFpDCode, 1678 "predicate_test": predicateTest, 1679 "op_class": "SimdFloatCvtOp" }, []) 1680 header_output += FpRegRegImmOpDeclare.subst(vcvtSHFixedFpDIop); 1681 decoder_output += FpRegRegImmOpConstructor.subst(vcvtSHFixedFpDIop); 1682 exec_output += PredOpExecute.subst(vcvtSHFixedFpDIop); 1683 1684 vcvtUHFixedFpSCode = vfpEnabledCheckCode + ''' 1685 FPSCR fpscr = (FPSCR) FpscrExc; 1686 VfpSavedState state = prepFpState(fpscr.rMode); 1687 __asm__ __volatile__("" : "=m" (FpOp1_uh) : "m" (FpOp1_uh)); |
1608 FpDest = vfpUFixedToFpS(fpscr.fz, fpscr.dn, FpOp1_uh, true, imm); | 1688 FpDest = vfpUFixedToFpS(fpscr.fz, fpscr.dn, FpOp1_uh, 16, imm); |
1609 __asm__ __volatile__("" :: "m" (FpDest)); 1610 finishVfp(fpscr, state, fpscr.fz); 1611 FpscrExc = fpscr; 1612 ''' 1613 vcvtUHFixedFpSIop = InstObjParams("vcvt", "VcvtUHFixedFpS", 1614 "FpRegRegImmOp", 1615 { "code": vcvtUHFixedFpSCode, 1616 "predicate_test": predicateTest, 1617 "op_class": "SimdFloatCvtOp" }, []) 1618 header_output += FpRegRegImmOpDeclare.subst(vcvtUHFixedFpSIop); 1619 decoder_output += FpRegRegImmOpConstructor.subst(vcvtUHFixedFpSIop); 1620 exec_output += PredOpExecute.subst(vcvtUHFixedFpSIop); 1621 1622 vcvtUHFixedFpDCode = vfpEnabledCheckCode + ''' 1623 FPSCR fpscr = (FPSCR) FpscrExc; 1624 uint64_t mid = ((uint64_t)FpOp1P0_uw | ((uint64_t)FpOp1P1_uw << 32)); 1625 VfpSavedState state = prepFpState(fpscr.rMode); 1626 __asm__ __volatile__("" : "=m" (mid) : "m" (mid)); | 1689 __asm__ __volatile__("" :: "m" (FpDest)); 1690 finishVfp(fpscr, state, fpscr.fz); 1691 FpscrExc = fpscr; 1692 ''' 1693 vcvtUHFixedFpSIop = InstObjParams("vcvt", "VcvtUHFixedFpS", 1694 "FpRegRegImmOp", 1695 { "code": vcvtUHFixedFpSCode, 1696 "predicate_test": predicateTest, 1697 "op_class": "SimdFloatCvtOp" }, []) 1698 header_output += FpRegRegImmOpDeclare.subst(vcvtUHFixedFpSIop); 1699 decoder_output += FpRegRegImmOpConstructor.subst(vcvtUHFixedFpSIop); 1700 exec_output += PredOpExecute.subst(vcvtUHFixedFpSIop); 1701 1702 vcvtUHFixedFpDCode = vfpEnabledCheckCode + ''' 1703 FPSCR fpscr = (FPSCR) FpscrExc; 1704 uint64_t mid = ((uint64_t)FpOp1P0_uw | ((uint64_t)FpOp1P1_uw << 32)); 1705 VfpSavedState state = prepFpState(fpscr.rMode); 1706 __asm__ __volatile__("" : "=m" (mid) : "m" (mid)); |
1627 double cDest = vfpUFixedToFpD(fpscr.fz, fpscr.dn, mid, true, imm); | 1707 double cDest = vfpUFixedToFpD(fpscr.fz, fpscr.dn, mid, 16, imm); |
1628 __asm__ __volatile__("" :: "m" (cDest)); 1629 finishVfp(fpscr, state, fpscr.fz); 1630 FpDestP0_uw = dblLow(cDest); 1631 FpDestP1_uw = dblHi(cDest); 1632 FpscrExc = fpscr; 1633 ''' 1634 vcvtUHFixedFpDIop = InstObjParams("vcvt", "VcvtUHFixedFpD", 1635 "FpRegRegImmOp", 1636 { "code": vcvtUHFixedFpDCode, 1637 "predicate_test": predicateTest, 1638 "op_class": "SimdFloatCvtOp" }, []) 1639 header_output += FpRegRegImmOpDeclare.subst(vcvtUHFixedFpDIop); 1640 decoder_output += FpRegRegImmOpConstructor.subst(vcvtUHFixedFpDIop); 1641 exec_output += PredOpExecute.subst(vcvtUHFixedFpDIop); 1642}}; | 1708 __asm__ __volatile__("" :: "m" (cDest)); 1709 finishVfp(fpscr, state, fpscr.fz); 1710 FpDestP0_uw = dblLow(cDest); 1711 FpDestP1_uw = dblHi(cDest); 1712 FpscrExc = fpscr; 1713 ''' 1714 vcvtUHFixedFpDIop = InstObjParams("vcvt", "VcvtUHFixedFpD", 1715 "FpRegRegImmOp", 1716 { "code": vcvtUHFixedFpDCode, 1717 "predicate_test": predicateTest, 1718 "op_class": "SimdFloatCvtOp" }, []) 1719 header_output += FpRegRegImmOpDeclare.subst(vcvtUHFixedFpDIop); 1720 decoder_output += FpRegRegImmOpConstructor.subst(vcvtUHFixedFpDIop); 1721 exec_output += PredOpExecute.subst(vcvtUHFixedFpDIop); 1722}}; |