fp.isa (8070:af0d29feb39d) fp.isa (8301:858384f3af1c)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 221 unchanged lines hidden (view full) ---

230 "Dest = Fpscr | FpCondCodes;",
231 "predicate_test": predicateTest,
232 "op_class": "SimdFloatMiscOp" },
233 ["IsSerializeBefore"])
234 header_output += FpRegRegOpDeclare.subst(vmrsFpscrIop);
235 decoder_output += FpRegRegOpConstructor.subst(vmrsFpscrIop);
236 exec_output += PredOpExecute.subst(vmrsFpscrIop);
237
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 221 unchanged lines hidden (view full) ---

230 "Dest = Fpscr | FpCondCodes;",
231 "predicate_test": predicateTest,
232 "op_class": "SimdFloatMiscOp" },
233 ["IsSerializeBefore"])
234 header_output += FpRegRegOpDeclare.subst(vmrsFpscrIop);
235 decoder_output += FpRegRegOpConstructor.subst(vmrsFpscrIop);
236 exec_output += PredOpExecute.subst(vmrsFpscrIop);
237
238 vmrsApsrCode = vmrsEnabledCheckCode + '''
239 Dest = (MiscOp1 & imm) | (Dest & ~imm);
240 '''
241 vmrsApsrIop = InstObjParams("vmrs", "VmrsApsr", "FpRegRegImmOp",
242 { "code": vmrsApsrCode,
243 "predicate_test": predicateTest,
244 "op_class": "SimdFloatMiscOp" },
245 ["IsSerializeBefore"])
246 header_output += FpRegRegImmOpDeclare.subst(vmrsApsrIop);
247 decoder_output += FpRegRegImmOpConstructor.subst(vmrsApsrIop);
248 exec_output += PredOpExecute.subst(vmrsApsrIop);
249
250 vmrsApsrFpscrCode = vmrsEnabledCheckCode + '''
238 vmrsApsrFpscrCode = vmrsEnabledCheckCode + '''
251 assert((imm & ~FpCondCodesMask) == 0);
252 Dest = (FpCondCodes & imm) | (Dest & ~imm);
239 Dest = FpCondCodes & FpCondCodesMask;
253 '''
254 vmrsApsrFpscrIop = InstObjParams("vmrs", "VmrsApsrFpscr", "FpRegRegImmOp",
255 { "code": vmrsApsrFpscrCode,
256 "predicate_test": predicateTest,
257 "op_class": "SimdFloatMiscOp" },
258 ["IsSerializeBefore"])
259 header_output += FpRegRegImmOpDeclare.subst(vmrsApsrFpscrIop);
260 decoder_output += FpRegRegImmOpConstructor.subst(vmrsApsrFpscrIop);

--- 1393 unchanged lines hidden --- 		240 '''
241 vmrsApsrFpscrIop = InstObjParams("vmrs", "VmrsApsrFpscr", "FpRegRegImmOp",
242 { "code": vmrsApsrFpscrCode,
243 "predicate_test": predicateTest,
244 "op_class": "SimdFloatMiscOp" },
245 ["IsSerializeBefore"])
246 header_output += FpRegRegImmOpDeclare.subst(vmrsApsrFpscrIop);
247 decoder_output += FpRegRegImmOpConstructor.subst(vmrsApsrFpscrIop);

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