fp.isa (7644:62873d5c2bfc) fp.isa (7648:3e561a5c0456)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 180 unchanged lines hidden (view full) ---

189
190 header_output = ""
191 decoder_output = ""
192 exec_output = ""
193
194 vmsrIop = InstObjParams("vmsr", "Vmsr", "FpRegRegOp",
195 { "code": vmsrEnabledCheckCode + \
196 "MiscDest = Op1;",
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 180 unchanged lines hidden (view full) ---

189
190 header_output = ""
191 decoder_output = ""
192 exec_output = ""
193
194 vmsrIop = InstObjParams("vmsr", "Vmsr", "FpRegRegOp",
195 { "code": vmsrEnabledCheckCode + \
196 "MiscDest = Op1;",
197 "predicate_test": predicateTest }, [])
197 "predicate_test": predicateTest },
198 ["IsSerializeAfter","IsNonSpeculative"])
198 header_output += FpRegRegOpDeclare.subst(vmsrIop);
199 decoder_output += FpRegRegOpConstructor.subst(vmsrIop);
200 exec_output += PredOpExecute.subst(vmsrIop);
201
202 vmsrFpscrCode = vmsrEnabledCheckCode + '''
203 Fpscr = Op1 & ~FpCondCodesMask;
204 FpCondCodes = Op1 & FpCondCodesMask;
205 '''

--- 1341 unchanged lines hidden --- 		199 header_output += FpRegRegOpDeclare.subst(vmsrIop);
200 decoder_output += FpRegRegOpConstructor.subst(vmsrIop);
201 exec_output += PredOpExecute.subst(vmsrIop);
202
203 vmsrFpscrCode = vmsrEnabledCheckCode + '''
204 Fpscr = Op1 & ~FpCondCodesMask;
205 FpCondCodes = Op1 & FpCondCodesMask;
206 '''

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