| fp.isa (7643:775ccd204013) | fp.isa (7644:62873d5c2bfc) |
|---|---|
| 1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating --- 178 unchanged lines hidden (view full) --- 187 188let {{ 189 190 header_output = "" 191 decoder_output = "" 192 exec_output = "" 193 194 vmsrIop = InstObjParams("vmsr", "Vmsr", "FpRegRegOp", | 1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating --- 178 unchanged lines hidden (view full) --- 187 188let {{ 189 190 header_output = "" 191 decoder_output = "" 192 exec_output = "" 193 194 vmsrIop = InstObjParams("vmsr", "Vmsr", "FpRegRegOp", |
| 195 { "code": vmsrrsEnabledCheckCode + \ | 195 { "code": vmsrEnabledCheckCode + \ |
| 196 "MiscDest = Op1;", 197 "predicate_test": predicateTest }, []) 198 header_output += FpRegRegOpDeclare.subst(vmsrIop); 199 decoder_output += FpRegRegOpConstructor.subst(vmsrIop); 200 exec_output += PredOpExecute.subst(vmsrIop); 201 | 196 "MiscDest = Op1;", 197 "predicate_test": predicateTest }, []) 198 header_output += FpRegRegOpDeclare.subst(vmsrIop); 199 decoder_output += FpRegRegOpConstructor.subst(vmsrIop); 200 exec_output += PredOpExecute.subst(vmsrIop); 201 |
| 202 vmsrFpscrCode = vmsrrsEnabledCheckCode + ''' | 202 vmsrFpscrCode = vmsrEnabledCheckCode + ''' |
| 203 Fpscr = Op1 & ~FpCondCodesMask; 204 FpCondCodes = Op1 & FpCondCodesMask; 205 ''' 206 vmsrFpscrIop = InstObjParams("vmsr", "VmsrFpscr", "FpRegRegOp", 207 { "code": vmsrFpscrCode, 208 "predicate_test": predicateTest }, []) 209 header_output += FpRegRegOpDeclare.subst(vmsrFpscrIop); 210 decoder_output += FpRegRegOpConstructor.subst(vmsrFpscrIop); 211 exec_output += PredOpExecute.subst(vmsrFpscrIop); 212 213 vmrsIop = InstObjParams("vmrs", "Vmrs", "FpRegRegOp", | 203 Fpscr = Op1 & ~FpCondCodesMask; 204 FpCondCodes = Op1 & FpCondCodesMask; 205 ''' 206 vmsrFpscrIop = InstObjParams("vmsr", "VmsrFpscr", "FpRegRegOp", 207 { "code": vmsrFpscrCode, 208 "predicate_test": predicateTest }, []) 209 header_output += FpRegRegOpDeclare.subst(vmsrFpscrIop); 210 decoder_output += FpRegRegOpConstructor.subst(vmsrFpscrIop); 211 exec_output += PredOpExecute.subst(vmsrFpscrIop); 212 213 vmrsIop = InstObjParams("vmrs", "Vmrs", "FpRegRegOp", |
| 214 { "code": vmsrrsEnabledCheckCode + \ | 214 { "code": vmrsEnabledCheckCode + \ |
| 215 "Dest = MiscOp1;", 216 "predicate_test": predicateTest }, []) 217 header_output += FpRegRegOpDeclare.subst(vmrsIop); 218 decoder_output += FpRegRegOpConstructor.subst(vmrsIop); 219 exec_output += PredOpExecute.subst(vmrsIop); 220 221 vmrsFpscrIop = InstObjParams("vmrs", "VmrsFpscr", "FpRegRegOp", | 215 "Dest = MiscOp1;", 216 "predicate_test": predicateTest }, []) 217 header_output += FpRegRegOpDeclare.subst(vmrsIop); 218 decoder_output += FpRegRegOpConstructor.subst(vmrsIop); 219 exec_output += PredOpExecute.subst(vmrsIop); 220 221 vmrsFpscrIop = InstObjParams("vmrs", "VmrsFpscr", "FpRegRegOp", |
| 222 { "code": vmsrrsEnabledCheckCode + \ | 222 { "code": vmrsEnabledCheckCode + \ |
| 223 "Dest = Fpscr | FpCondCodes;", 224 "predicate_test": predicateTest }, []) 225 header_output += FpRegRegOpDeclare.subst(vmrsFpscrIop); 226 decoder_output += FpRegRegOpConstructor.subst(vmrsFpscrIop); 227 exec_output += PredOpExecute.subst(vmrsFpscrIop); 228 | 223 "Dest = Fpscr | FpCondCodes;", 224 "predicate_test": predicateTest }, []) 225 header_output += FpRegRegOpDeclare.subst(vmrsFpscrIop); 226 decoder_output += FpRegRegOpConstructor.subst(vmrsFpscrIop); 227 exec_output += PredOpExecute.subst(vmrsFpscrIop); 228 |
| 229 vmrsApsrCode = vmsrrsEnabledCheckCode + ''' | 229 vmrsApsrCode = vmrsEnabledCheckCode + ''' |
| 230 Dest = (MiscOp1 & imm) | (Dest & ~imm); 231 ''' 232 vmrsApsrIop = InstObjParams("vmrs", "VmrsApsr", "FpRegRegImmOp", 233 { "code": vmrsApsrCode, 234 "predicate_test": predicateTest }, []) 235 header_output += FpRegRegImmOpDeclare.subst(vmrsApsrIop); 236 decoder_output += FpRegRegImmOpConstructor.subst(vmrsApsrIop); 237 exec_output += PredOpExecute.subst(vmrsApsrIop); 238 | 230 Dest = (MiscOp1 & imm) | (Dest & ~imm); 231 ''' 232 vmrsApsrIop = InstObjParams("vmrs", "VmrsApsr", "FpRegRegImmOp", 233 { "code": vmrsApsrCode, 234 "predicate_test": predicateTest }, []) 235 header_output += FpRegRegImmOpDeclare.subst(vmrsApsrIop); 236 decoder_output += FpRegRegImmOpConstructor.subst(vmrsApsrIop); 237 exec_output += PredOpExecute.subst(vmrsApsrIop); 238 |
| 239 vmrsApsrFpscrCode = vmsrrsEnabledCheckCode + ''' | 239 vmrsApsrFpscrCode = vmrsEnabledCheckCode + ''' |
| 240 assert((imm & ~FpCondCodesMask) == 0); 241 Dest = (FpCondCodes & imm) | (Dest & ~imm); 242 ''' 243 vmrsApsrFpscrIop = InstObjParams("vmrs", "VmrsApsrFpscr", "FpRegRegImmOp", 244 { "code": vmrsApsrFpscrCode, 245 "predicate_test": predicateTest }, []) 246 header_output += FpRegRegImmOpDeclare.subst(vmrsApsrFpscrIop); 247 decoder_output += FpRegRegImmOpConstructor.subst(vmrsApsrFpscrIop); --- 1299 unchanged lines hidden --- | 240 assert((imm & ~FpCondCodesMask) == 0); 241 Dest = (FpCondCodes & imm) | (Dest & ~imm); 242 ''' 243 vmrsApsrFpscrIop = InstObjParams("vmrs", "VmrsApsrFpscr", "FpRegRegImmOp", 244 { "code": vmrsApsrFpscrCode, 245 "predicate_test": predicateTest }, []) 246 header_output += FpRegRegImmOpDeclare.subst(vmrsApsrFpscrIop); 247 decoder_output += FpRegRegImmOpConstructor.subst(vmrsApsrFpscrIop); --- 1299 unchanged lines hidden --- |