fp.isa (7640:5286a8a469c5) | fp.isa (7643:775ccd204013) |
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1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating --- 185 unchanged lines hidden (view full) --- 194 vmsrIop = InstObjParams("vmsr", "Vmsr", "FpRegRegOp", 195 { "code": vmsrrsEnabledCheckCode + \ 196 "MiscDest = Op1;", 197 "predicate_test": predicateTest }, []) 198 header_output += FpRegRegOpDeclare.subst(vmsrIop); 199 decoder_output += FpRegRegOpConstructor.subst(vmsrIop); 200 exec_output += PredOpExecute.subst(vmsrIop); 201 | 1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating --- 185 unchanged lines hidden (view full) --- 194 vmsrIop = InstObjParams("vmsr", "Vmsr", "FpRegRegOp", 195 { "code": vmsrrsEnabledCheckCode + \ 196 "MiscDest = Op1;", 197 "predicate_test": predicateTest }, []) 198 header_output += FpRegRegOpDeclare.subst(vmsrIop); 199 decoder_output += FpRegRegOpConstructor.subst(vmsrIop); 200 exec_output += PredOpExecute.subst(vmsrIop); 201 |
202 vmsrFpscrCode = vmsrrsEnabledCheckCode + ''' 203 Fpscr = Op1 & ~FpCondCodesMask; 204 FpCondCodes = Op1 & FpCondCodesMask; 205 ''' 206 vmsrFpscrIop = InstObjParams("vmsr", "VmsrFpscr", "FpRegRegOp", 207 { "code": vmsrFpscrCode, 208 "predicate_test": predicateTest }, []) 209 header_output += FpRegRegOpDeclare.subst(vmsrFpscrIop); 210 decoder_output += FpRegRegOpConstructor.subst(vmsrFpscrIop); 211 exec_output += PredOpExecute.subst(vmsrFpscrIop); 212 |
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202 vmrsIop = InstObjParams("vmrs", "Vmrs", "FpRegRegOp", 203 { "code": vmsrrsEnabledCheckCode + \ 204 "Dest = MiscOp1;", 205 "predicate_test": predicateTest }, []) 206 header_output += FpRegRegOpDeclare.subst(vmrsIop); 207 decoder_output += FpRegRegOpConstructor.subst(vmrsIop); 208 exec_output += PredOpExecute.subst(vmrsIop); 209 | 213 vmrsIop = InstObjParams("vmrs", "Vmrs", "FpRegRegOp", 214 { "code": vmsrrsEnabledCheckCode + \ 215 "Dest = MiscOp1;", 216 "predicate_test": predicateTest }, []) 217 header_output += FpRegRegOpDeclare.subst(vmrsIop); 218 decoder_output += FpRegRegOpConstructor.subst(vmrsIop); 219 exec_output += PredOpExecute.subst(vmrsIop); 220 |
210 vmrsApsrCode = "Dest = (MiscOp1 & imm) | (Dest & ~imm);" | 221 vmrsFpscrIop = InstObjParams("vmrs", "VmrsFpscr", "FpRegRegOp", 222 { "code": vmsrrsEnabledCheckCode + \ 223 "Dest = Fpscr | FpCondCodes;", 224 "predicate_test": predicateTest }, []) 225 header_output += FpRegRegOpDeclare.subst(vmrsFpscrIop); 226 decoder_output += FpRegRegOpConstructor.subst(vmrsFpscrIop); 227 exec_output += PredOpExecute.subst(vmrsFpscrIop); 228 229 vmrsApsrCode = vmsrrsEnabledCheckCode + ''' 230 Dest = (MiscOp1 & imm) | (Dest & ~imm); 231 ''' |
211 vmrsApsrIop = InstObjParams("vmrs", "VmrsApsr", "FpRegRegImmOp", 212 { "code": vmrsApsrCode, 213 "predicate_test": predicateTest }, []) 214 header_output += FpRegRegImmOpDeclare.subst(vmrsApsrIop); 215 decoder_output += FpRegRegImmOpConstructor.subst(vmrsApsrIop); 216 exec_output += PredOpExecute.subst(vmrsApsrIop); 217 | 232 vmrsApsrIop = InstObjParams("vmrs", "VmrsApsr", "FpRegRegImmOp", 233 { "code": vmrsApsrCode, 234 "predicate_test": predicateTest }, []) 235 header_output += FpRegRegImmOpDeclare.subst(vmrsApsrIop); 236 decoder_output += FpRegRegImmOpConstructor.subst(vmrsApsrIop); 237 exec_output += PredOpExecute.subst(vmrsApsrIop); 238 |
239 vmrsApsrFpscrCode = vmsrrsEnabledCheckCode + ''' 240 assert((imm & ~FpCondCodesMask) == 0); 241 Dest = (FpCondCodes & imm) | (Dest & ~imm); 242 ''' 243 vmrsApsrFpscrIop = InstObjParams("vmrs", "VmrsApsrFpscr", "FpRegRegImmOp", 244 { "code": vmrsApsrFpscrCode, 245 "predicate_test": predicateTest }, []) 246 header_output += FpRegRegImmOpDeclare.subst(vmrsApsrFpscrIop); 247 decoder_output += FpRegRegImmOpConstructor.subst(vmrsApsrFpscrIop); 248 exec_output += PredOpExecute.subst(vmrsApsrFpscrIop); 249 |
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218 vmovImmSCode = vfpEnabledCheckCode + ''' 219 FpDest.uw = bits(imm, 31, 0); 220 ''' 221 vmovImmSIop = InstObjParams("vmov", "VmovImmS", "FpRegImmOp", 222 { "code": vmovImmSCode, 223 "predicate_test": predicateTest }, []) 224 header_output += FpRegImmOpDeclare.subst(vmovImmSIop); 225 decoder_output += FpRegImmOpConstructor.subst(vmovImmSIop); --- 166 unchanged lines hidden (view full) --- 392 393let {{ 394 395 header_output = "" 396 decoder_output = "" 397 exec_output = "" 398 399 singleCode = vfpEnabledCheckCode + ''' | 250 vmovImmSCode = vfpEnabledCheckCode + ''' 251 FpDest.uw = bits(imm, 31, 0); 252 ''' 253 vmovImmSIop = InstObjParams("vmov", "VmovImmS", "FpRegImmOp", 254 { "code": vmovImmSCode, 255 "predicate_test": predicateTest }, []) 256 header_output += FpRegImmOpDeclare.subst(vmovImmSIop); 257 decoder_output += FpRegImmOpConstructor.subst(vmovImmSIop); --- 166 unchanged lines hidden (view full) --- 424 425let {{ 426 427 header_output = "" 428 decoder_output = "" 429 exec_output = "" 430 431 singleCode = vfpEnabledCheckCode + ''' |
400 FPSCR fpscr = Fpscr; | 432 FPSCR fpscr = Fpscr | FpCondCodes; |
401 FpDest = %(op)s; | 433 FpDest = %(op)s; |
402 Fpscr = fpscr; | 434 FpCondCodes = fpscr & FpCondCodesMask; |
403 ''' 404 singleBinOp = "binaryOp(fpscr, FpOp1, FpOp2," + \ 405 "%(func)s, fpscr.fz, fpscr.dn, fpscr.rMode)" 406 singleUnaryOp = "unaryOp(fpscr, FpOp1, %(func)s, fpscr.fz, fpscr.rMode)" 407 doubleCode = vfpEnabledCheckCode + ''' | 435 ''' 436 singleBinOp = "binaryOp(fpscr, FpOp1, FpOp2," + \ 437 "%(func)s, fpscr.fz, fpscr.dn, fpscr.rMode)" 438 singleUnaryOp = "unaryOp(fpscr, FpOp1, %(func)s, fpscr.fz, fpscr.rMode)" 439 doubleCode = vfpEnabledCheckCode + ''' |
408 FPSCR fpscr = Fpscr; | 440 FPSCR fpscr = Fpscr | FpCondCodes; |
409 double dest = %(op)s; | 441 double dest = %(op)s; |
410 Fpscr = fpscr; | 442 FpCondCodes = fpscr & FpCondCodesMask; |
411 FpDestP0.uw = dblLow(dest); 412 FpDestP1.uw = dblHi(dest); 413 ''' 414 doubleBinOp = ''' 415 binaryOp(fpscr, dbl(FpOp1P0.uw, FpOp1P1.uw), 416 dbl(FpOp2P0.uw, FpOp2P1.uw), 417 %(func)s, fpscr.fz, fpscr.dn, fpscr.rMode); 418 ''' --- 79 unchanged lines hidden (view full) --- 498 499let {{ 500 501 header_output = "" 502 decoder_output = "" 503 exec_output = "" 504 505 vmlaSCode = vfpEnabledCheckCode + ''' | 443 FpDestP0.uw = dblLow(dest); 444 FpDestP1.uw = dblHi(dest); 445 ''' 446 doubleBinOp = ''' 447 binaryOp(fpscr, dbl(FpOp1P0.uw, FpOp1P1.uw), 448 dbl(FpOp2P0.uw, FpOp2P1.uw), 449 %(func)s, fpscr.fz, fpscr.dn, fpscr.rMode); 450 ''' --- 79 unchanged lines hidden (view full) --- 530 531let {{ 532 533 header_output = "" 534 decoder_output = "" 535 exec_output = "" 536 537 vmlaSCode = vfpEnabledCheckCode + ''' |
506 FPSCR fpscr = Fpscr; | 538 FPSCR fpscr = Fpscr | FpCondCodes; |
507 float mid = binaryOp(fpscr, FpOp1, FpOp2, 508 fpMulS, fpscr.fz, fpscr.dn, fpscr.rMode); 509 FpDest = binaryOp(fpscr, FpDest, mid, fpAddS, 510 fpscr.fz, fpscr.dn, fpscr.rMode); | 539 float mid = binaryOp(fpscr, FpOp1, FpOp2, 540 fpMulS, fpscr.fz, fpscr.dn, fpscr.rMode); 541 FpDest = binaryOp(fpscr, FpDest, mid, fpAddS, 542 fpscr.fz, fpscr.dn, fpscr.rMode); |
511 Fpscr = fpscr; | 543 FpCondCodes = fpscr & FpCondCodesMask; |
512 ''' 513 vmlaSIop = InstObjParams("vmlas", "VmlaS", "FpRegRegRegOp", 514 { "code": vmlaSCode, 515 "predicate_test": predicateTest }, []) 516 header_output += FpRegRegRegOpDeclare.subst(vmlaSIop); 517 decoder_output += FpRegRegRegOpConstructor.subst(vmlaSIop); 518 exec_output += PredOpExecute.subst(vmlaSIop); 519 520 vmlaDCode = vfpEnabledCheckCode + ''' | 544 ''' 545 vmlaSIop = InstObjParams("vmlas", "VmlaS", "FpRegRegRegOp", 546 { "code": vmlaSCode, 547 "predicate_test": predicateTest }, []) 548 header_output += FpRegRegRegOpDeclare.subst(vmlaSIop); 549 decoder_output += FpRegRegRegOpConstructor.subst(vmlaSIop); 550 exec_output += PredOpExecute.subst(vmlaSIop); 551 552 vmlaDCode = vfpEnabledCheckCode + ''' |
521 FPSCR fpscr = Fpscr; | 553 FPSCR fpscr = Fpscr | FpCondCodes; |
522 double mid = binaryOp(fpscr, dbl(FpOp1P0.uw, FpOp1P1.uw), 523 dbl(FpOp2P0.uw, FpOp2P1.uw), 524 fpMulD, fpscr.fz, fpscr.dn, fpscr.rMode); 525 double dest = binaryOp(fpscr, dbl(FpDestP0.uw, FpDestP1.uw), 526 mid, fpAddD, fpscr.fz, 527 fpscr.dn, fpscr.rMode); | 554 double mid = binaryOp(fpscr, dbl(FpOp1P0.uw, FpOp1P1.uw), 555 dbl(FpOp2P0.uw, FpOp2P1.uw), 556 fpMulD, fpscr.fz, fpscr.dn, fpscr.rMode); 557 double dest = binaryOp(fpscr, dbl(FpDestP0.uw, FpDestP1.uw), 558 mid, fpAddD, fpscr.fz, 559 fpscr.dn, fpscr.rMode); |
528 Fpscr = fpscr; | 560 FpCondCodes = fpscr & FpCondCodesMask; |
529 FpDestP0.uw = dblLow(dest); 530 FpDestP1.uw = dblHi(dest); 531 ''' 532 vmlaDIop = InstObjParams("vmlad", "VmlaD", "FpRegRegRegOp", 533 { "code": vmlaDCode, 534 "predicate_test": predicateTest }, []) 535 header_output += FpRegRegRegOpDeclare.subst(vmlaDIop); 536 decoder_output += FpRegRegRegOpConstructor.subst(vmlaDIop); 537 exec_output += PredOpExecute.subst(vmlaDIop); 538 539 vmlsSCode = vfpEnabledCheckCode + ''' | 561 FpDestP0.uw = dblLow(dest); 562 FpDestP1.uw = dblHi(dest); 563 ''' 564 vmlaDIop = InstObjParams("vmlad", "VmlaD", "FpRegRegRegOp", 565 { "code": vmlaDCode, 566 "predicate_test": predicateTest }, []) 567 header_output += FpRegRegRegOpDeclare.subst(vmlaDIop); 568 decoder_output += FpRegRegRegOpConstructor.subst(vmlaDIop); 569 exec_output += PredOpExecute.subst(vmlaDIop); 570 571 vmlsSCode = vfpEnabledCheckCode + ''' |
540 FPSCR fpscr = Fpscr; | 572 FPSCR fpscr = Fpscr | FpCondCodes; |
541 float mid = binaryOp(fpscr, FpOp1, FpOp2, 542 fpMulS, fpscr.fz, fpscr.dn, fpscr.rMode); 543 FpDest = binaryOp(fpscr, FpDest, -mid, fpAddS, 544 fpscr.fz, fpscr.dn, fpscr.rMode); | 573 float mid = binaryOp(fpscr, FpOp1, FpOp2, 574 fpMulS, fpscr.fz, fpscr.dn, fpscr.rMode); 575 FpDest = binaryOp(fpscr, FpDest, -mid, fpAddS, 576 fpscr.fz, fpscr.dn, fpscr.rMode); |
545 Fpscr = fpscr; | 577 FpCondCodes = fpscr & FpCondCodesMask; |
546 ''' 547 vmlsSIop = InstObjParams("vmlss", "VmlsS", "FpRegRegRegOp", 548 { "code": vmlsSCode, 549 "predicate_test": predicateTest }, []) 550 header_output += FpRegRegRegOpDeclare.subst(vmlsSIop); 551 decoder_output += FpRegRegRegOpConstructor.subst(vmlsSIop); 552 exec_output += PredOpExecute.subst(vmlsSIop); 553 554 vmlsDCode = vfpEnabledCheckCode + ''' | 578 ''' 579 vmlsSIop = InstObjParams("vmlss", "VmlsS", "FpRegRegRegOp", 580 { "code": vmlsSCode, 581 "predicate_test": predicateTest }, []) 582 header_output += FpRegRegRegOpDeclare.subst(vmlsSIop); 583 decoder_output += FpRegRegRegOpConstructor.subst(vmlsSIop); 584 exec_output += PredOpExecute.subst(vmlsSIop); 585 586 vmlsDCode = vfpEnabledCheckCode + ''' |
555 FPSCR fpscr = Fpscr; | 587 FPSCR fpscr = Fpscr | FpCondCodes; |
556 double mid = binaryOp(fpscr, dbl(FpOp1P0.uw, FpOp1P1.uw), 557 dbl(FpOp2P0.uw, FpOp2P1.uw), 558 fpMulD, fpscr.fz, fpscr.dn, fpscr.rMode); 559 double dest = binaryOp(fpscr, dbl(FpDestP0.uw, FpDestP1.uw), 560 -mid, fpAddD, fpscr.fz, 561 fpscr.dn, fpscr.rMode); | 588 double mid = binaryOp(fpscr, dbl(FpOp1P0.uw, FpOp1P1.uw), 589 dbl(FpOp2P0.uw, FpOp2P1.uw), 590 fpMulD, fpscr.fz, fpscr.dn, fpscr.rMode); 591 double dest = binaryOp(fpscr, dbl(FpDestP0.uw, FpDestP1.uw), 592 -mid, fpAddD, fpscr.fz, 593 fpscr.dn, fpscr.rMode); |
562 Fpscr = fpscr; | 594 FpCondCodes = fpscr & FpCondCodesMask; |
563 FpDestP0.uw = dblLow(dest); 564 FpDestP1.uw = dblHi(dest); 565 ''' 566 vmlsDIop = InstObjParams("vmlsd", "VmlsD", "FpRegRegRegOp", 567 { "code": vmlsDCode, 568 "predicate_test": predicateTest }, []) 569 header_output += FpRegRegRegOpDeclare.subst(vmlsDIop); 570 decoder_output += FpRegRegRegOpConstructor.subst(vmlsDIop); 571 exec_output += PredOpExecute.subst(vmlsDIop); 572 573 vnmlaSCode = vfpEnabledCheckCode + ''' | 595 FpDestP0.uw = dblLow(dest); 596 FpDestP1.uw = dblHi(dest); 597 ''' 598 vmlsDIop = InstObjParams("vmlsd", "VmlsD", "FpRegRegRegOp", 599 { "code": vmlsDCode, 600 "predicate_test": predicateTest }, []) 601 header_output += FpRegRegRegOpDeclare.subst(vmlsDIop); 602 decoder_output += FpRegRegRegOpConstructor.subst(vmlsDIop); 603 exec_output += PredOpExecute.subst(vmlsDIop); 604 605 vnmlaSCode = vfpEnabledCheckCode + ''' |
574 FPSCR fpscr = Fpscr; | 606 FPSCR fpscr = Fpscr | FpCondCodes; |
575 float mid = binaryOp(fpscr, FpOp1, FpOp2, 576 fpMulS, fpscr.fz, fpscr.dn, fpscr.rMode); 577 FpDest = binaryOp(fpscr, -FpDest, -mid, fpAddS, 578 fpscr.fz, fpscr.dn, fpscr.rMode); | 607 float mid = binaryOp(fpscr, FpOp1, FpOp2, 608 fpMulS, fpscr.fz, fpscr.dn, fpscr.rMode); 609 FpDest = binaryOp(fpscr, -FpDest, -mid, fpAddS, 610 fpscr.fz, fpscr.dn, fpscr.rMode); |
579 Fpscr = fpscr; | 611 FpCondCodes = fpscr & FpCondCodesMask; |
580 ''' 581 vnmlaSIop = InstObjParams("vnmlas", "VnmlaS", "FpRegRegRegOp", 582 { "code": vnmlaSCode, 583 "predicate_test": predicateTest }, []) 584 header_output += FpRegRegRegOpDeclare.subst(vnmlaSIop); 585 decoder_output += FpRegRegRegOpConstructor.subst(vnmlaSIop); 586 exec_output += PredOpExecute.subst(vnmlaSIop); 587 588 vnmlaDCode = vfpEnabledCheckCode + ''' | 612 ''' 613 vnmlaSIop = InstObjParams("vnmlas", "VnmlaS", "FpRegRegRegOp", 614 { "code": vnmlaSCode, 615 "predicate_test": predicateTest }, []) 616 header_output += FpRegRegRegOpDeclare.subst(vnmlaSIop); 617 decoder_output += FpRegRegRegOpConstructor.subst(vnmlaSIop); 618 exec_output += PredOpExecute.subst(vnmlaSIop); 619 620 vnmlaDCode = vfpEnabledCheckCode + ''' |
589 FPSCR fpscr = Fpscr; | 621 FPSCR fpscr = Fpscr | FpCondCodes; |
590 double mid = binaryOp(fpscr, dbl(FpOp1P0.uw, FpOp1P1.uw), 591 dbl(FpOp2P0.uw, FpOp2P1.uw), 592 fpMulD, fpscr.fz, fpscr.dn, fpscr.rMode); 593 double dest = binaryOp(fpscr, -dbl(FpDestP0.uw, FpDestP1.uw), 594 -mid, fpAddD, fpscr.fz, 595 fpscr.dn, fpscr.rMode); | 622 double mid = binaryOp(fpscr, dbl(FpOp1P0.uw, FpOp1P1.uw), 623 dbl(FpOp2P0.uw, FpOp2P1.uw), 624 fpMulD, fpscr.fz, fpscr.dn, fpscr.rMode); 625 double dest = binaryOp(fpscr, -dbl(FpDestP0.uw, FpDestP1.uw), 626 -mid, fpAddD, fpscr.fz, 627 fpscr.dn, fpscr.rMode); |
596 Fpscr = fpscr; | 628 FpCondCodes = fpscr & FpCondCodesMask; |
597 FpDestP0.uw = dblLow(dest); 598 FpDestP1.uw = dblHi(dest); 599 ''' 600 vnmlaDIop = InstObjParams("vnmlad", "VnmlaD", "FpRegRegRegOp", 601 { "code": vnmlaDCode, 602 "predicate_test": predicateTest }, []) 603 header_output += FpRegRegRegOpDeclare.subst(vnmlaDIop); 604 decoder_output += FpRegRegRegOpConstructor.subst(vnmlaDIop); 605 exec_output += PredOpExecute.subst(vnmlaDIop); 606 607 vnmlsSCode = vfpEnabledCheckCode + ''' | 629 FpDestP0.uw = dblLow(dest); 630 FpDestP1.uw = dblHi(dest); 631 ''' 632 vnmlaDIop = InstObjParams("vnmlad", "VnmlaD", "FpRegRegRegOp", 633 { "code": vnmlaDCode, 634 "predicate_test": predicateTest }, []) 635 header_output += FpRegRegRegOpDeclare.subst(vnmlaDIop); 636 decoder_output += FpRegRegRegOpConstructor.subst(vnmlaDIop); 637 exec_output += PredOpExecute.subst(vnmlaDIop); 638 639 vnmlsSCode = vfpEnabledCheckCode + ''' |
608 FPSCR fpscr = Fpscr; | 640 FPSCR fpscr = Fpscr | FpCondCodes; |
609 float mid = binaryOp(fpscr, FpOp1, FpOp2, 610 fpMulS, fpscr.fz, fpscr.dn, fpscr.rMode); 611 FpDest = binaryOp(fpscr, -FpDest, mid, fpAddS, 612 fpscr.fz, fpscr.dn, fpscr.rMode); | 641 float mid = binaryOp(fpscr, FpOp1, FpOp2, 642 fpMulS, fpscr.fz, fpscr.dn, fpscr.rMode); 643 FpDest = binaryOp(fpscr, -FpDest, mid, fpAddS, 644 fpscr.fz, fpscr.dn, fpscr.rMode); |
613 Fpscr = fpscr; | 645 FpCondCodes = fpscr & FpCondCodesMask; |
614 ''' 615 vnmlsSIop = InstObjParams("vnmlss", "VnmlsS", "FpRegRegRegOp", 616 { "code": vnmlsSCode, 617 "predicate_test": predicateTest }, []) 618 header_output += FpRegRegRegOpDeclare.subst(vnmlsSIop); 619 decoder_output += FpRegRegRegOpConstructor.subst(vnmlsSIop); 620 exec_output += PredOpExecute.subst(vnmlsSIop); 621 622 vnmlsDCode = vfpEnabledCheckCode + ''' | 646 ''' 647 vnmlsSIop = InstObjParams("vnmlss", "VnmlsS", "FpRegRegRegOp", 648 { "code": vnmlsSCode, 649 "predicate_test": predicateTest }, []) 650 header_output += FpRegRegRegOpDeclare.subst(vnmlsSIop); 651 decoder_output += FpRegRegRegOpConstructor.subst(vnmlsSIop); 652 exec_output += PredOpExecute.subst(vnmlsSIop); 653 654 vnmlsDCode = vfpEnabledCheckCode + ''' |
623 FPSCR fpscr = Fpscr; | 655 FPSCR fpscr = Fpscr | FpCondCodes; |
624 double mid = binaryOp(fpscr, dbl(FpOp1P0.uw, FpOp1P1.uw), 625 dbl(FpOp2P0.uw, FpOp2P1.uw), 626 fpMulD, fpscr.fz, fpscr.dn, fpscr.rMode); 627 double dest = binaryOp(fpscr, -dbl(FpDestP0.uw, FpDestP1.uw), 628 mid, fpAddD, fpscr.fz, 629 fpscr.dn, fpscr.rMode); | 656 double mid = binaryOp(fpscr, dbl(FpOp1P0.uw, FpOp1P1.uw), 657 dbl(FpOp2P0.uw, FpOp2P1.uw), 658 fpMulD, fpscr.fz, fpscr.dn, fpscr.rMode); 659 double dest = binaryOp(fpscr, -dbl(FpDestP0.uw, FpDestP1.uw), 660 mid, fpAddD, fpscr.fz, 661 fpscr.dn, fpscr.rMode); |
630 Fpscr = fpscr; | 662 FpCondCodes = fpscr & FpCondCodesMask; |
631 FpDestP0.uw = dblLow(dest); 632 FpDestP1.uw = dblHi(dest); 633 ''' 634 vnmlsDIop = InstObjParams("vnmlsd", "VnmlsD", "FpRegRegRegOp", 635 { "code": vnmlsDCode, 636 "predicate_test": predicateTest }, []) 637 header_output += FpRegRegRegOpDeclare.subst(vnmlsDIop); 638 decoder_output += FpRegRegRegOpConstructor.subst(vnmlsDIop); 639 exec_output += PredOpExecute.subst(vnmlsDIop); 640 641 vnmulSCode = vfpEnabledCheckCode + ''' | 663 FpDestP0.uw = dblLow(dest); 664 FpDestP1.uw = dblHi(dest); 665 ''' 666 vnmlsDIop = InstObjParams("vnmlsd", "VnmlsD", "FpRegRegRegOp", 667 { "code": vnmlsDCode, 668 "predicate_test": predicateTest }, []) 669 header_output += FpRegRegRegOpDeclare.subst(vnmlsDIop); 670 decoder_output += FpRegRegRegOpConstructor.subst(vnmlsDIop); 671 exec_output += PredOpExecute.subst(vnmlsDIop); 672 673 vnmulSCode = vfpEnabledCheckCode + ''' |
642 FPSCR fpscr = Fpscr; | 674 FPSCR fpscr = Fpscr | FpCondCodes; |
643 FpDest = -binaryOp(fpscr, FpOp1, FpOp2, fpMulS, 644 fpscr.fz, fpscr.dn, fpscr.rMode); | 675 FpDest = -binaryOp(fpscr, FpOp1, FpOp2, fpMulS, 676 fpscr.fz, fpscr.dn, fpscr.rMode); |
645 Fpscr = fpscr; | 677 FpCondCodes = fpscr & FpCondCodesMask; |
646 ''' 647 vnmulSIop = InstObjParams("vnmuls", "VnmulS", "FpRegRegRegOp", 648 { "code": vnmulSCode, 649 "predicate_test": predicateTest }, []) 650 header_output += FpRegRegRegOpDeclare.subst(vnmulSIop); 651 decoder_output += FpRegRegRegOpConstructor.subst(vnmulSIop); 652 exec_output += PredOpExecute.subst(vnmulSIop); 653 654 vnmulDCode = vfpEnabledCheckCode + ''' | 678 ''' 679 vnmulSIop = InstObjParams("vnmuls", "VnmulS", "FpRegRegRegOp", 680 { "code": vnmulSCode, 681 "predicate_test": predicateTest }, []) 682 header_output += FpRegRegRegOpDeclare.subst(vnmulSIop); 683 decoder_output += FpRegRegRegOpConstructor.subst(vnmulSIop); 684 exec_output += PredOpExecute.subst(vnmulSIop); 685 686 vnmulDCode = vfpEnabledCheckCode + ''' |
655 FPSCR fpscr = Fpscr; | 687 FPSCR fpscr = Fpscr | FpCondCodes; |
656 double dest = -binaryOp(fpscr, dbl(FpOp1P0.uw, FpOp1P1.uw), 657 dbl(FpOp2P0.uw, FpOp2P1.uw), 658 fpMulD, fpscr.fz, fpscr.dn, 659 fpscr.rMode); | 688 double dest = -binaryOp(fpscr, dbl(FpOp1P0.uw, FpOp1P1.uw), 689 dbl(FpOp2P0.uw, FpOp2P1.uw), 690 fpMulD, fpscr.fz, fpscr.dn, 691 fpscr.rMode); |
660 Fpscr = fpscr; | 692 FpCondCodes = fpscr & FpCondCodesMask; |
661 FpDestP0.uw = dblLow(dest); 662 FpDestP1.uw = dblHi(dest); 663 ''' 664 vnmulDIop = InstObjParams("vnmuld", "VnmulD", "FpRegRegRegOp", 665 { "code": vnmulDCode, 666 "predicate_test": predicateTest }, []) 667 header_output += FpRegRegRegOpDeclare.subst(vnmulDIop); 668 decoder_output += FpRegRegRegOpConstructor.subst(vnmulDIop); 669 exec_output += PredOpExecute.subst(vnmulDIop); 670}}; 671 672let {{ 673 674 header_output = "" 675 decoder_output = "" 676 exec_output = "" 677 678 vcvtUIntFpSCode = vfpEnabledCheckCode + ''' | 693 FpDestP0.uw = dblLow(dest); 694 FpDestP1.uw = dblHi(dest); 695 ''' 696 vnmulDIop = InstObjParams("vnmuld", "VnmulD", "FpRegRegRegOp", 697 { "code": vnmulDCode, 698 "predicate_test": predicateTest }, []) 699 header_output += FpRegRegRegOpDeclare.subst(vnmulDIop); 700 decoder_output += FpRegRegRegOpConstructor.subst(vnmulDIop); 701 exec_output += PredOpExecute.subst(vnmulDIop); 702}}; 703 704let {{ 705 706 header_output = "" 707 decoder_output = "" 708 exec_output = "" 709 710 vcvtUIntFpSCode = vfpEnabledCheckCode + ''' |
679 FPSCR fpscr = Fpscr; | 711 FPSCR fpscr = Fpscr | FpCondCodes; |
680 VfpSavedState state = prepFpState(fpscr.rMode); 681 __asm__ __volatile__("" : "=m" (FpOp1.uw) : "m" (FpOp1.uw)); 682 FpDest = FpOp1.uw; 683 __asm__ __volatile__("" :: "m" (FpDest)); 684 finishVfp(fpscr, state, fpscr.fz); | 712 VfpSavedState state = prepFpState(fpscr.rMode); 713 __asm__ __volatile__("" : "=m" (FpOp1.uw) : "m" (FpOp1.uw)); 714 FpDest = FpOp1.uw; 715 __asm__ __volatile__("" :: "m" (FpDest)); 716 finishVfp(fpscr, state, fpscr.fz); |
685 Fpscr = fpscr; | 717 FpCondCodes = fpscr & FpCondCodesMask; |
686 ''' 687 vcvtUIntFpSIop = InstObjParams("vcvt", "VcvtUIntFpS", "FpRegRegOp", 688 { "code": vcvtUIntFpSCode, 689 "predicate_test": predicateTest }, []) 690 header_output += FpRegRegOpDeclare.subst(vcvtUIntFpSIop); 691 decoder_output += FpRegRegOpConstructor.subst(vcvtUIntFpSIop); 692 exec_output += PredOpExecute.subst(vcvtUIntFpSIop); 693 694 vcvtUIntFpDCode = vfpEnabledCheckCode + ''' | 718 ''' 719 vcvtUIntFpSIop = InstObjParams("vcvt", "VcvtUIntFpS", "FpRegRegOp", 720 { "code": vcvtUIntFpSCode, 721 "predicate_test": predicateTest }, []) 722 header_output += FpRegRegOpDeclare.subst(vcvtUIntFpSIop); 723 decoder_output += FpRegRegOpConstructor.subst(vcvtUIntFpSIop); 724 exec_output += PredOpExecute.subst(vcvtUIntFpSIop); 725 726 vcvtUIntFpDCode = vfpEnabledCheckCode + ''' |
695 FPSCR fpscr = Fpscr; | 727 FPSCR fpscr = Fpscr | FpCondCodes; |
696 VfpSavedState state = prepFpState(fpscr.rMode); 697 __asm__ __volatile__("" : "=m" (FpOp1P0.uw) : "m" (FpOp1P0.uw)); 698 double cDest = (uint64_t)FpOp1P0.uw; 699 __asm__ __volatile__("" :: "m" (cDest)); 700 finishVfp(fpscr, state, fpscr.fz); | 728 VfpSavedState state = prepFpState(fpscr.rMode); 729 __asm__ __volatile__("" : "=m" (FpOp1P0.uw) : "m" (FpOp1P0.uw)); 730 double cDest = (uint64_t)FpOp1P0.uw; 731 __asm__ __volatile__("" :: "m" (cDest)); 732 finishVfp(fpscr, state, fpscr.fz); |
701 Fpscr = fpscr; | 733 FpCondCodes = fpscr & FpCondCodesMask; |
702 FpDestP0.uw = dblLow(cDest); 703 FpDestP1.uw = dblHi(cDest); 704 ''' 705 vcvtUIntFpDIop = InstObjParams("vcvt", "VcvtUIntFpD", "FpRegRegOp", 706 { "code": vcvtUIntFpDCode, 707 "predicate_test": predicateTest }, []) 708 header_output += FpRegRegOpDeclare.subst(vcvtUIntFpDIop); 709 decoder_output += FpRegRegOpConstructor.subst(vcvtUIntFpDIop); 710 exec_output += PredOpExecute.subst(vcvtUIntFpDIop); 711 712 vcvtSIntFpSCode = vfpEnabledCheckCode + ''' | 734 FpDestP0.uw = dblLow(cDest); 735 FpDestP1.uw = dblHi(cDest); 736 ''' 737 vcvtUIntFpDIop = InstObjParams("vcvt", "VcvtUIntFpD", "FpRegRegOp", 738 { "code": vcvtUIntFpDCode, 739 "predicate_test": predicateTest }, []) 740 header_output += FpRegRegOpDeclare.subst(vcvtUIntFpDIop); 741 decoder_output += FpRegRegOpConstructor.subst(vcvtUIntFpDIop); 742 exec_output += PredOpExecute.subst(vcvtUIntFpDIop); 743 744 vcvtSIntFpSCode = vfpEnabledCheckCode + ''' |
713 FPSCR fpscr = Fpscr; | 745 FPSCR fpscr = Fpscr | FpCondCodes; |
714 VfpSavedState state = prepFpState(fpscr.rMode); 715 __asm__ __volatile__("" : "=m" (FpOp1.sw) : "m" (FpOp1.sw)); 716 FpDest = FpOp1.sw; 717 __asm__ __volatile__("" :: "m" (FpDest)); 718 finishVfp(fpscr, state, fpscr.fz); | 746 VfpSavedState state = prepFpState(fpscr.rMode); 747 __asm__ __volatile__("" : "=m" (FpOp1.sw) : "m" (FpOp1.sw)); 748 FpDest = FpOp1.sw; 749 __asm__ __volatile__("" :: "m" (FpDest)); 750 finishVfp(fpscr, state, fpscr.fz); |
719 Fpscr = fpscr; | 751 FpCondCodes = fpscr & FpCondCodesMask; |
720 ''' 721 vcvtSIntFpSIop = InstObjParams("vcvt", "VcvtSIntFpS", "FpRegRegOp", 722 { "code": vcvtSIntFpSCode, 723 "predicate_test": predicateTest }, []) 724 header_output += FpRegRegOpDeclare.subst(vcvtSIntFpSIop); 725 decoder_output += FpRegRegOpConstructor.subst(vcvtSIntFpSIop); 726 exec_output += PredOpExecute.subst(vcvtSIntFpSIop); 727 728 vcvtSIntFpDCode = vfpEnabledCheckCode + ''' | 752 ''' 753 vcvtSIntFpSIop = InstObjParams("vcvt", "VcvtSIntFpS", "FpRegRegOp", 754 { "code": vcvtSIntFpSCode, 755 "predicate_test": predicateTest }, []) 756 header_output += FpRegRegOpDeclare.subst(vcvtSIntFpSIop); 757 decoder_output += FpRegRegOpConstructor.subst(vcvtSIntFpSIop); 758 exec_output += PredOpExecute.subst(vcvtSIntFpSIop); 759 760 vcvtSIntFpDCode = vfpEnabledCheckCode + ''' |
729 FPSCR fpscr = Fpscr; | 761 FPSCR fpscr = Fpscr | FpCondCodes; |
730 VfpSavedState state = prepFpState(fpscr.rMode); 731 __asm__ __volatile__("" : "=m" (FpOp1P0.sw) : "m" (FpOp1P0.sw)); 732 double cDest = FpOp1P0.sw; 733 __asm__ __volatile__("" :: "m" (cDest)); 734 finishVfp(fpscr, state, fpscr.fz); | 762 VfpSavedState state = prepFpState(fpscr.rMode); 763 __asm__ __volatile__("" : "=m" (FpOp1P0.sw) : "m" (FpOp1P0.sw)); 764 double cDest = FpOp1P0.sw; 765 __asm__ __volatile__("" :: "m" (cDest)); 766 finishVfp(fpscr, state, fpscr.fz); |
735 Fpscr = fpscr; | 767 FpCondCodes = fpscr & FpCondCodesMask; |
736 FpDestP0.uw = dblLow(cDest); 737 FpDestP1.uw = dblHi(cDest); 738 ''' 739 vcvtSIntFpDIop = InstObjParams("vcvt", "VcvtSIntFpD", "FpRegRegOp", 740 { "code": vcvtSIntFpDCode, 741 "predicate_test": predicateTest }, []) 742 header_output += FpRegRegOpDeclare.subst(vcvtSIntFpDIop); 743 decoder_output += FpRegRegOpConstructor.subst(vcvtSIntFpDIop); 744 exec_output += PredOpExecute.subst(vcvtSIntFpDIop); 745 746 vcvtFpUIntSRCode = vfpEnabledCheckCode + ''' | 768 FpDestP0.uw = dblLow(cDest); 769 FpDestP1.uw = dblHi(cDest); 770 ''' 771 vcvtSIntFpDIop = InstObjParams("vcvt", "VcvtSIntFpD", "FpRegRegOp", 772 { "code": vcvtSIntFpDCode, 773 "predicate_test": predicateTest }, []) 774 header_output += FpRegRegOpDeclare.subst(vcvtSIntFpDIop); 775 decoder_output += FpRegRegOpConstructor.subst(vcvtSIntFpDIop); 776 exec_output += PredOpExecute.subst(vcvtSIntFpDIop); 777 778 vcvtFpUIntSRCode = vfpEnabledCheckCode + ''' |
747 FPSCR fpscr = Fpscr; | 779 FPSCR fpscr = Fpscr | FpCondCodes; |
748 VfpSavedState state = prepFpState(fpscr.rMode); 749 vfpFlushToZero(fpscr, FpOp1); 750 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 751 FpDest.uw = vfpFpSToFixed(FpOp1, false, false, 0, false); 752 __asm__ __volatile__("" :: "m" (FpDest.uw)); 753 finishVfp(fpscr, state, fpscr.fz); | 780 VfpSavedState state = prepFpState(fpscr.rMode); 781 vfpFlushToZero(fpscr, FpOp1); 782 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 783 FpDest.uw = vfpFpSToFixed(FpOp1, false, false, 0, false); 784 __asm__ __volatile__("" :: "m" (FpDest.uw)); 785 finishVfp(fpscr, state, fpscr.fz); |
754 Fpscr = fpscr; | 786 FpCondCodes = fpscr & FpCondCodesMask; |
755 ''' 756 vcvtFpUIntSRIop = InstObjParams("vcvt", "VcvtFpUIntSR", "FpRegRegOp", 757 { "code": vcvtFpUIntSRCode, 758 "predicate_test": predicateTest }, []) 759 header_output += FpRegRegOpDeclare.subst(vcvtFpUIntSRIop); 760 decoder_output += FpRegRegOpConstructor.subst(vcvtFpUIntSRIop); 761 exec_output += PredOpExecute.subst(vcvtFpUIntSRIop); 762 763 vcvtFpUIntDRCode = vfpEnabledCheckCode + ''' | 787 ''' 788 vcvtFpUIntSRIop = InstObjParams("vcvt", "VcvtFpUIntSR", "FpRegRegOp", 789 { "code": vcvtFpUIntSRCode, 790 "predicate_test": predicateTest }, []) 791 header_output += FpRegRegOpDeclare.subst(vcvtFpUIntSRIop); 792 decoder_output += FpRegRegOpConstructor.subst(vcvtFpUIntSRIop); 793 exec_output += PredOpExecute.subst(vcvtFpUIntSRIop); 794 795 vcvtFpUIntDRCode = vfpEnabledCheckCode + ''' |
764 FPSCR fpscr = Fpscr; | 796 FPSCR fpscr = Fpscr | FpCondCodes; |
765 double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw); 766 vfpFlushToZero(fpscr, cOp1); 767 VfpSavedState state = prepFpState(fpscr.rMode); 768 __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); 769 uint64_t result = vfpFpDToFixed(cOp1, false, false, 0, false); 770 __asm__ __volatile__("" :: "m" (result)); 771 finishVfp(fpscr, state, fpscr.fz); | 797 double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw); 798 vfpFlushToZero(fpscr, cOp1); 799 VfpSavedState state = prepFpState(fpscr.rMode); 800 __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); 801 uint64_t result = vfpFpDToFixed(cOp1, false, false, 0, false); 802 __asm__ __volatile__("" :: "m" (result)); 803 finishVfp(fpscr, state, fpscr.fz); |
772 Fpscr = fpscr; | 804 FpCondCodes = fpscr & FpCondCodesMask; |
773 FpDestP0.uw = result; 774 ''' 775 vcvtFpUIntDRIop = InstObjParams("vcvtr", "VcvtFpUIntDR", "FpRegRegOp", 776 { "code": vcvtFpUIntDRCode, 777 "predicate_test": predicateTest }, []) 778 header_output += FpRegRegOpDeclare.subst(vcvtFpUIntDRIop); 779 decoder_output += FpRegRegOpConstructor.subst(vcvtFpUIntDRIop); 780 exec_output += PredOpExecute.subst(vcvtFpUIntDRIop); 781 782 vcvtFpSIntSRCode = vfpEnabledCheckCode + ''' | 805 FpDestP0.uw = result; 806 ''' 807 vcvtFpUIntDRIop = InstObjParams("vcvtr", "VcvtFpUIntDR", "FpRegRegOp", 808 { "code": vcvtFpUIntDRCode, 809 "predicate_test": predicateTest }, []) 810 header_output += FpRegRegOpDeclare.subst(vcvtFpUIntDRIop); 811 decoder_output += FpRegRegOpConstructor.subst(vcvtFpUIntDRIop); 812 exec_output += PredOpExecute.subst(vcvtFpUIntDRIop); 813 814 vcvtFpSIntSRCode = vfpEnabledCheckCode + ''' |
783 FPSCR fpscr = Fpscr; | 815 FPSCR fpscr = Fpscr | FpCondCodes; |
784 VfpSavedState state = prepFpState(fpscr.rMode); 785 vfpFlushToZero(fpscr, FpOp1); 786 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 787 FpDest.sw = vfpFpSToFixed(FpOp1, true, false, 0, false); 788 __asm__ __volatile__("" :: "m" (FpDest.sw)); 789 finishVfp(fpscr, state, fpscr.fz); | 816 VfpSavedState state = prepFpState(fpscr.rMode); 817 vfpFlushToZero(fpscr, FpOp1); 818 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 819 FpDest.sw = vfpFpSToFixed(FpOp1, true, false, 0, false); 820 __asm__ __volatile__("" :: "m" (FpDest.sw)); 821 finishVfp(fpscr, state, fpscr.fz); |
790 Fpscr = fpscr; | 822 FpCondCodes = fpscr & FpCondCodesMask; |
791 ''' 792 vcvtFpSIntSRIop = InstObjParams("vcvtr", "VcvtFpSIntSR", "FpRegRegOp", 793 { "code": vcvtFpSIntSRCode, 794 "predicate_test": predicateTest }, []) 795 header_output += FpRegRegOpDeclare.subst(vcvtFpSIntSRIop); 796 decoder_output += FpRegRegOpConstructor.subst(vcvtFpSIntSRIop); 797 exec_output += PredOpExecute.subst(vcvtFpSIntSRIop); 798 799 vcvtFpSIntDRCode = vfpEnabledCheckCode + ''' | 823 ''' 824 vcvtFpSIntSRIop = InstObjParams("vcvtr", "VcvtFpSIntSR", "FpRegRegOp", 825 { "code": vcvtFpSIntSRCode, 826 "predicate_test": predicateTest }, []) 827 header_output += FpRegRegOpDeclare.subst(vcvtFpSIntSRIop); 828 decoder_output += FpRegRegOpConstructor.subst(vcvtFpSIntSRIop); 829 exec_output += PredOpExecute.subst(vcvtFpSIntSRIop); 830 831 vcvtFpSIntDRCode = vfpEnabledCheckCode + ''' |
800 FPSCR fpscr = Fpscr; | 832 FPSCR fpscr = Fpscr | FpCondCodes; |
801 double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw); 802 vfpFlushToZero(fpscr, cOp1); 803 VfpSavedState state = prepFpState(fpscr.rMode); 804 __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); 805 int64_t result = vfpFpDToFixed(cOp1, true, false, 0, false); 806 __asm__ __volatile__("" :: "m" (result)); 807 finishVfp(fpscr, state, fpscr.fz); | 833 double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw); 834 vfpFlushToZero(fpscr, cOp1); 835 VfpSavedState state = prepFpState(fpscr.rMode); 836 __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); 837 int64_t result = vfpFpDToFixed(cOp1, true, false, 0, false); 838 __asm__ __volatile__("" :: "m" (result)); 839 finishVfp(fpscr, state, fpscr.fz); |
808 Fpscr = fpscr; | 840 FpCondCodes = fpscr & FpCondCodesMask; |
809 FpDestP0.uw = result; 810 ''' 811 vcvtFpSIntDRIop = InstObjParams("vcvtr", "VcvtFpSIntDR", "FpRegRegOp", 812 { "code": vcvtFpSIntDRCode, 813 "predicate_test": predicateTest }, []) 814 header_output += FpRegRegOpDeclare.subst(vcvtFpSIntDRIop); 815 decoder_output += FpRegRegOpConstructor.subst(vcvtFpSIntDRIop); 816 exec_output += PredOpExecute.subst(vcvtFpSIntDRIop); 817 818 vcvtFpUIntSCode = vfpEnabledCheckCode + ''' | 841 FpDestP0.uw = result; 842 ''' 843 vcvtFpSIntDRIop = InstObjParams("vcvtr", "VcvtFpSIntDR", "FpRegRegOp", 844 { "code": vcvtFpSIntDRCode, 845 "predicate_test": predicateTest }, []) 846 header_output += FpRegRegOpDeclare.subst(vcvtFpSIntDRIop); 847 decoder_output += FpRegRegOpConstructor.subst(vcvtFpSIntDRIop); 848 exec_output += PredOpExecute.subst(vcvtFpSIntDRIop); 849 850 vcvtFpUIntSCode = vfpEnabledCheckCode + ''' |
819 FPSCR fpscr = Fpscr; | 851 FPSCR fpscr = Fpscr | FpCondCodes; |
820 vfpFlushToZero(fpscr, FpOp1); 821 VfpSavedState state = prepFpState(fpscr.rMode); 822 fesetround(FeRoundZero); 823 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 824 FpDest.uw = vfpFpSToFixed(FpOp1, false, false, 0); 825 __asm__ __volatile__("" :: "m" (FpDest.uw)); 826 finishVfp(fpscr, state, fpscr.fz); | 852 vfpFlushToZero(fpscr, FpOp1); 853 VfpSavedState state = prepFpState(fpscr.rMode); 854 fesetround(FeRoundZero); 855 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 856 FpDest.uw = vfpFpSToFixed(FpOp1, false, false, 0); 857 __asm__ __volatile__("" :: "m" (FpDest.uw)); 858 finishVfp(fpscr, state, fpscr.fz); |
827 Fpscr = fpscr; | 859 FpCondCodes = fpscr & FpCondCodesMask; |
828 ''' 829 vcvtFpUIntSIop = InstObjParams("vcvt", "VcvtFpUIntS", "FpRegRegOp", 830 { "code": vcvtFpUIntSCode, 831 "predicate_test": predicateTest }, []) 832 header_output += FpRegRegOpDeclare.subst(vcvtFpUIntSIop); 833 decoder_output += FpRegRegOpConstructor.subst(vcvtFpUIntSIop); 834 exec_output += PredOpExecute.subst(vcvtFpUIntSIop); 835 836 vcvtFpUIntDCode = vfpEnabledCheckCode + ''' | 860 ''' 861 vcvtFpUIntSIop = InstObjParams("vcvt", "VcvtFpUIntS", "FpRegRegOp", 862 { "code": vcvtFpUIntSCode, 863 "predicate_test": predicateTest }, []) 864 header_output += FpRegRegOpDeclare.subst(vcvtFpUIntSIop); 865 decoder_output += FpRegRegOpConstructor.subst(vcvtFpUIntSIop); 866 exec_output += PredOpExecute.subst(vcvtFpUIntSIop); 867 868 vcvtFpUIntDCode = vfpEnabledCheckCode + ''' |
837 FPSCR fpscr = Fpscr; | 869 FPSCR fpscr = Fpscr | FpCondCodes; |
838 double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw); 839 vfpFlushToZero(fpscr, cOp1); 840 VfpSavedState state = prepFpState(fpscr.rMode); 841 fesetround(FeRoundZero); 842 __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); 843 uint64_t result = vfpFpDToFixed(cOp1, false, false, 0); 844 __asm__ __volatile__("" :: "m" (result)); 845 finishVfp(fpscr, state, fpscr.fz); | 870 double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw); 871 vfpFlushToZero(fpscr, cOp1); 872 VfpSavedState state = prepFpState(fpscr.rMode); 873 fesetround(FeRoundZero); 874 __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); 875 uint64_t result = vfpFpDToFixed(cOp1, false, false, 0); 876 __asm__ __volatile__("" :: "m" (result)); 877 finishVfp(fpscr, state, fpscr.fz); |
846 Fpscr = fpscr; | 878 FpCondCodes = fpscr & FpCondCodesMask; |
847 FpDestP0.uw = result; 848 ''' 849 vcvtFpUIntDIop = InstObjParams("vcvt", "VcvtFpUIntD", "FpRegRegOp", 850 { "code": vcvtFpUIntDCode, 851 "predicate_test": predicateTest }, []) 852 header_output += FpRegRegOpDeclare.subst(vcvtFpUIntDIop); 853 decoder_output += FpRegRegOpConstructor.subst(vcvtFpUIntDIop); 854 exec_output += PredOpExecute.subst(vcvtFpUIntDIop); 855 856 vcvtFpSIntSCode = vfpEnabledCheckCode + ''' | 879 FpDestP0.uw = result; 880 ''' 881 vcvtFpUIntDIop = InstObjParams("vcvt", "VcvtFpUIntD", "FpRegRegOp", 882 { "code": vcvtFpUIntDCode, 883 "predicate_test": predicateTest }, []) 884 header_output += FpRegRegOpDeclare.subst(vcvtFpUIntDIop); 885 decoder_output += FpRegRegOpConstructor.subst(vcvtFpUIntDIop); 886 exec_output += PredOpExecute.subst(vcvtFpUIntDIop); 887 888 vcvtFpSIntSCode = vfpEnabledCheckCode + ''' |
857 FPSCR fpscr = Fpscr; | 889 FPSCR fpscr = Fpscr | FpCondCodes; |
858 vfpFlushToZero(fpscr, FpOp1); 859 VfpSavedState state = prepFpState(fpscr.rMode); 860 fesetround(FeRoundZero); 861 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 862 FpDest.sw = vfpFpSToFixed(FpOp1, true, false, 0); 863 __asm__ __volatile__("" :: "m" (FpDest.sw)); 864 finishVfp(fpscr, state, fpscr.fz); | 890 vfpFlushToZero(fpscr, FpOp1); 891 VfpSavedState state = prepFpState(fpscr.rMode); 892 fesetround(FeRoundZero); 893 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 894 FpDest.sw = vfpFpSToFixed(FpOp1, true, false, 0); 895 __asm__ __volatile__("" :: "m" (FpDest.sw)); 896 finishVfp(fpscr, state, fpscr.fz); |
865 Fpscr = fpscr; | 897 FpCondCodes = fpscr & FpCondCodesMask; |
866 ''' 867 vcvtFpSIntSIop = InstObjParams("vcvt", "VcvtFpSIntS", "FpRegRegOp", 868 { "code": vcvtFpSIntSCode, 869 "predicate_test": predicateTest }, []) 870 header_output += FpRegRegOpDeclare.subst(vcvtFpSIntSIop); 871 decoder_output += FpRegRegOpConstructor.subst(vcvtFpSIntSIop); 872 exec_output += PredOpExecute.subst(vcvtFpSIntSIop); 873 874 vcvtFpSIntDCode = vfpEnabledCheckCode + ''' | 898 ''' 899 vcvtFpSIntSIop = InstObjParams("vcvt", "VcvtFpSIntS", "FpRegRegOp", 900 { "code": vcvtFpSIntSCode, 901 "predicate_test": predicateTest }, []) 902 header_output += FpRegRegOpDeclare.subst(vcvtFpSIntSIop); 903 decoder_output += FpRegRegOpConstructor.subst(vcvtFpSIntSIop); 904 exec_output += PredOpExecute.subst(vcvtFpSIntSIop); 905 906 vcvtFpSIntDCode = vfpEnabledCheckCode + ''' |
875 FPSCR fpscr = Fpscr; | 907 FPSCR fpscr = Fpscr | FpCondCodes; |
876 double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw); 877 vfpFlushToZero(fpscr, cOp1); 878 VfpSavedState state = prepFpState(fpscr.rMode); 879 fesetround(FeRoundZero); 880 __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); 881 int64_t result = vfpFpDToFixed(cOp1, true, false, 0); 882 __asm__ __volatile__("" :: "m" (result)); 883 finishVfp(fpscr, state, fpscr.fz); | 908 double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw); 909 vfpFlushToZero(fpscr, cOp1); 910 VfpSavedState state = prepFpState(fpscr.rMode); 911 fesetround(FeRoundZero); 912 __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); 913 int64_t result = vfpFpDToFixed(cOp1, true, false, 0); 914 __asm__ __volatile__("" :: "m" (result)); 915 finishVfp(fpscr, state, fpscr.fz); |
884 Fpscr = fpscr; | 916 FpCondCodes = fpscr & FpCondCodesMask; |
885 FpDestP0.uw = result; 886 ''' 887 vcvtFpSIntDIop = InstObjParams("vcvt", "VcvtFpSIntD", "FpRegRegOp", 888 { "code": vcvtFpSIntDCode, 889 "predicate_test": predicateTest }, []) 890 header_output += FpRegRegOpDeclare.subst(vcvtFpSIntDIop); 891 decoder_output += FpRegRegOpConstructor.subst(vcvtFpSIntDIop); 892 exec_output += PredOpExecute.subst(vcvtFpSIntDIop); 893 894 vcvtFpSFpDCode = vfpEnabledCheckCode + ''' | 917 FpDestP0.uw = result; 918 ''' 919 vcvtFpSIntDIop = InstObjParams("vcvt", "VcvtFpSIntD", "FpRegRegOp", 920 { "code": vcvtFpSIntDCode, 921 "predicate_test": predicateTest }, []) 922 header_output += FpRegRegOpDeclare.subst(vcvtFpSIntDIop); 923 decoder_output += FpRegRegOpConstructor.subst(vcvtFpSIntDIop); 924 exec_output += PredOpExecute.subst(vcvtFpSIntDIop); 925 926 vcvtFpSFpDCode = vfpEnabledCheckCode + ''' |
895 FPSCR fpscr = Fpscr; | 927 FPSCR fpscr = Fpscr | FpCondCodes; |
896 vfpFlushToZero(fpscr, FpOp1); 897 VfpSavedState state = prepFpState(fpscr.rMode); 898 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 899 double cDest = fixFpSFpDDest(Fpscr, FpOp1); 900 __asm__ __volatile__("" :: "m" (cDest)); 901 finishVfp(fpscr, state, fpscr.fz); | 928 vfpFlushToZero(fpscr, FpOp1); 929 VfpSavedState state = prepFpState(fpscr.rMode); 930 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 931 double cDest = fixFpSFpDDest(Fpscr, FpOp1); 932 __asm__ __volatile__("" :: "m" (cDest)); 933 finishVfp(fpscr, state, fpscr.fz); |
902 Fpscr = fpscr; | 934 FpCondCodes = fpscr & FpCondCodesMask; |
903 FpDestP0.uw = dblLow(cDest); 904 FpDestP1.uw = dblHi(cDest); 905 ''' 906 vcvtFpSFpDIop = InstObjParams("vcvt", "VcvtFpSFpD", "FpRegRegOp", 907 { "code": vcvtFpSFpDCode, 908 "predicate_test": predicateTest }, []) 909 header_output += FpRegRegOpDeclare.subst(vcvtFpSFpDIop); 910 decoder_output += FpRegRegOpConstructor.subst(vcvtFpSFpDIop); 911 exec_output += PredOpExecute.subst(vcvtFpSFpDIop); 912 913 vcvtFpDFpSCode = vfpEnabledCheckCode + ''' | 935 FpDestP0.uw = dblLow(cDest); 936 FpDestP1.uw = dblHi(cDest); 937 ''' 938 vcvtFpSFpDIop = InstObjParams("vcvt", "VcvtFpSFpD", "FpRegRegOp", 939 { "code": vcvtFpSFpDCode, 940 "predicate_test": predicateTest }, []) 941 header_output += FpRegRegOpDeclare.subst(vcvtFpSFpDIop); 942 decoder_output += FpRegRegOpConstructor.subst(vcvtFpSFpDIop); 943 exec_output += PredOpExecute.subst(vcvtFpSFpDIop); 944 945 vcvtFpDFpSCode = vfpEnabledCheckCode + ''' |
914 FPSCR fpscr = Fpscr; | 946 FPSCR fpscr = Fpscr | FpCondCodes; |
915 double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw); 916 vfpFlushToZero(fpscr, cOp1); 917 VfpSavedState state = prepFpState(fpscr.rMode); 918 __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); 919 FpDest = fixFpDFpSDest(Fpscr, cOp1); 920 __asm__ __volatile__("" :: "m" (FpDest)); 921 finishVfp(fpscr, state, fpscr.fz); | 947 double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw); 948 vfpFlushToZero(fpscr, cOp1); 949 VfpSavedState state = prepFpState(fpscr.rMode); 950 __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); 951 FpDest = fixFpDFpSDest(Fpscr, cOp1); 952 __asm__ __volatile__("" :: "m" (FpDest)); 953 finishVfp(fpscr, state, fpscr.fz); |
922 Fpscr = fpscr; | 954 FpCondCodes = fpscr & FpCondCodesMask; |
923 ''' 924 vcvtFpDFpSIop = InstObjParams("vcvt", "VcvtFpDFpS", "FpRegRegOp", 925 { "code": vcvtFpDFpSCode, 926 "predicate_test": predicateTest }, []) 927 header_output += FpRegRegOpDeclare.subst(vcvtFpDFpSIop); 928 decoder_output += FpRegRegOpConstructor.subst(vcvtFpDFpSIop); 929 exec_output += PredOpExecute.subst(vcvtFpDFpSIop); 930 931 vcvtFpHTFpSCode = vfpEnabledCheckCode + ''' | 955 ''' 956 vcvtFpDFpSIop = InstObjParams("vcvt", "VcvtFpDFpS", "FpRegRegOp", 957 { "code": vcvtFpDFpSCode, 958 "predicate_test": predicateTest }, []) 959 header_output += FpRegRegOpDeclare.subst(vcvtFpDFpSIop); 960 decoder_output += FpRegRegOpConstructor.subst(vcvtFpDFpSIop); 961 exec_output += PredOpExecute.subst(vcvtFpDFpSIop); 962 963 vcvtFpHTFpSCode = vfpEnabledCheckCode + ''' |
932 FPSCR fpscr = Fpscr; | 964 FPSCR fpscr = Fpscr | FpCondCodes; |
933 vfpFlushToZero(fpscr, FpOp1); 934 VfpSavedState state = prepFpState(fpscr.rMode); 935 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 936 FpDest = vcvtFpHFpS(fpscr, fpscr.dn, fpscr.ahp, 937 bits(fpToBits(FpOp1), 31, 16)); 938 __asm__ __volatile__("" :: "m" (FpDest)); 939 finishVfp(fpscr, state, fpscr.fz); | 965 vfpFlushToZero(fpscr, FpOp1); 966 VfpSavedState state = prepFpState(fpscr.rMode); 967 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 968 FpDest = vcvtFpHFpS(fpscr, fpscr.dn, fpscr.ahp, 969 bits(fpToBits(FpOp1), 31, 16)); 970 __asm__ __volatile__("" :: "m" (FpDest)); 971 finishVfp(fpscr, state, fpscr.fz); |
940 Fpscr = fpscr; | 972 FpCondCodes = fpscr & FpCondCodesMask; |
941 ''' 942 vcvtFpHTFpSIop = InstObjParams("vcvtt", "VcvtFpHTFpS", "FpRegRegOp", 943 { "code": vcvtFpHTFpSCode, 944 "predicate_test": predicateTest }, []) 945 header_output += FpRegRegOpDeclare.subst(vcvtFpHTFpSIop); 946 decoder_output += FpRegRegOpConstructor.subst(vcvtFpHTFpSIop); 947 exec_output += PredOpExecute.subst(vcvtFpHTFpSIop); 948 949 vcvtFpHBFpSCode = vfpEnabledCheckCode + ''' | 973 ''' 974 vcvtFpHTFpSIop = InstObjParams("vcvtt", "VcvtFpHTFpS", "FpRegRegOp", 975 { "code": vcvtFpHTFpSCode, 976 "predicate_test": predicateTest }, []) 977 header_output += FpRegRegOpDeclare.subst(vcvtFpHTFpSIop); 978 decoder_output += FpRegRegOpConstructor.subst(vcvtFpHTFpSIop); 979 exec_output += PredOpExecute.subst(vcvtFpHTFpSIop); 980 981 vcvtFpHBFpSCode = vfpEnabledCheckCode + ''' |
950 FPSCR fpscr = Fpscr; | 982 FPSCR fpscr = Fpscr | FpCondCodes; |
951 VfpSavedState state = prepFpState(fpscr.rMode); 952 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 953 FpDest = vcvtFpHFpS(fpscr, fpscr.dn, fpscr.ahp, 954 bits(fpToBits(FpOp1), 15, 0)); 955 __asm__ __volatile__("" :: "m" (FpDest)); 956 finishVfp(fpscr, state, fpscr.fz); | 983 VfpSavedState state = prepFpState(fpscr.rMode); 984 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 985 FpDest = vcvtFpHFpS(fpscr, fpscr.dn, fpscr.ahp, 986 bits(fpToBits(FpOp1), 15, 0)); 987 __asm__ __volatile__("" :: "m" (FpDest)); 988 finishVfp(fpscr, state, fpscr.fz); |
957 Fpscr = fpscr; | 989 FpCondCodes = fpscr & FpCondCodesMask; |
958 ''' 959 vcvtFpHBFpSIop = InstObjParams("vcvtb", "VcvtFpHBFpS", "FpRegRegOp", 960 { "code": vcvtFpHBFpSCode, 961 "predicate_test": predicateTest }, []) 962 header_output += FpRegRegOpDeclare.subst(vcvtFpHBFpSIop); 963 decoder_output += FpRegRegOpConstructor.subst(vcvtFpHBFpSIop); 964 exec_output += PredOpExecute.subst(vcvtFpHBFpSIop); 965 966 vcvtFpSFpHTCode = vfpEnabledCheckCode + ''' | 990 ''' 991 vcvtFpHBFpSIop = InstObjParams("vcvtb", "VcvtFpHBFpS", "FpRegRegOp", 992 { "code": vcvtFpHBFpSCode, 993 "predicate_test": predicateTest }, []) 994 header_output += FpRegRegOpDeclare.subst(vcvtFpHBFpSIop); 995 decoder_output += FpRegRegOpConstructor.subst(vcvtFpHBFpSIop); 996 exec_output += PredOpExecute.subst(vcvtFpHBFpSIop); 997 998 vcvtFpSFpHTCode = vfpEnabledCheckCode + ''' |
967 FPSCR fpscr = Fpscr; | 999 FPSCR fpscr = Fpscr | FpCondCodes; |
968 vfpFlushToZero(fpscr, FpOp1); 969 VfpSavedState state = prepFpState(fpscr.rMode); 970 __asm__ __volatile__("" : "=m" (FpOp1), "=m" (FpDest.uw) 971 : "m" (FpOp1), "m" (FpDest.uw)); 972 FpDest.uw = insertBits(FpDest.uw, 31, 16,, 973 vcvtFpSFpH(fpscr, fpscr.fz, fpscr.dn, 974 fpscr.rMode, fpscr.ahp, FpOp1)); 975 __asm__ __volatile__("" :: "m" (FpDest.uw)); 976 finishVfp(fpscr, state, fpscr.fz); | 1000 vfpFlushToZero(fpscr, FpOp1); 1001 VfpSavedState state = prepFpState(fpscr.rMode); 1002 __asm__ __volatile__("" : "=m" (FpOp1), "=m" (FpDest.uw) 1003 : "m" (FpOp1), "m" (FpDest.uw)); 1004 FpDest.uw = insertBits(FpDest.uw, 31, 16,, 1005 vcvtFpSFpH(fpscr, fpscr.fz, fpscr.dn, 1006 fpscr.rMode, fpscr.ahp, FpOp1)); 1007 __asm__ __volatile__("" :: "m" (FpDest.uw)); 1008 finishVfp(fpscr, state, fpscr.fz); |
977 Fpscr = fpscr; | 1009 FpCondCodes = fpscr & FpCondCodesMask; |
978 ''' 979 vcvtFpSFpHTIop = InstObjParams("vcvtt", "VcvtFpSFpHT", "FpRegRegOp", 980 { "code": vcvtFpHTFpSCode, 981 "predicate_test": predicateTest }, []) 982 header_output += FpRegRegOpDeclare.subst(vcvtFpSFpHTIop); 983 decoder_output += FpRegRegOpConstructor.subst(vcvtFpSFpHTIop); 984 exec_output += PredOpExecute.subst(vcvtFpSFpHTIop); 985 986 vcvtFpSFpHBCode = vfpEnabledCheckCode + ''' | 1010 ''' 1011 vcvtFpSFpHTIop = InstObjParams("vcvtt", "VcvtFpSFpHT", "FpRegRegOp", 1012 { "code": vcvtFpHTFpSCode, 1013 "predicate_test": predicateTest }, []) 1014 header_output += FpRegRegOpDeclare.subst(vcvtFpSFpHTIop); 1015 decoder_output += FpRegRegOpConstructor.subst(vcvtFpSFpHTIop); 1016 exec_output += PredOpExecute.subst(vcvtFpSFpHTIop); 1017 1018 vcvtFpSFpHBCode = vfpEnabledCheckCode + ''' |
987 FPSCR fpscr = Fpscr; | 1019 FPSCR fpscr = Fpscr | FpCondCodes; |
988 vfpFlushToZero(fpscr, FpOp1); 989 VfpSavedState state = prepFpState(fpscr.rMode); 990 __asm__ __volatile__("" : "=m" (FpOp1), "=m" (FpDest.uw) 991 : "m" (FpOp1), "m" (FpDest.uw)); 992 FpDest.uw = insertBits(FpDest.uw, 15, 0, 993 vcvtFpSFpH(fpscr, fpscr.fz, fpscr.dn, 994 fpscr.rMode, fpscr.ahp, FpOp1)); 995 __asm__ __volatile__("" :: "m" (FpDest.uw)); 996 finishVfp(fpscr, state, fpscr.fz); | 1020 vfpFlushToZero(fpscr, FpOp1); 1021 VfpSavedState state = prepFpState(fpscr.rMode); 1022 __asm__ __volatile__("" : "=m" (FpOp1), "=m" (FpDest.uw) 1023 : "m" (FpOp1), "m" (FpDest.uw)); 1024 FpDest.uw = insertBits(FpDest.uw, 15, 0, 1025 vcvtFpSFpH(fpscr, fpscr.fz, fpscr.dn, 1026 fpscr.rMode, fpscr.ahp, FpOp1)); 1027 __asm__ __volatile__("" :: "m" (FpDest.uw)); 1028 finishVfp(fpscr, state, fpscr.fz); |
997 Fpscr = fpscr; | 1029 FpCondCodes = fpscr & FpCondCodesMask; |
998 ''' 999 vcvtFpSFpHBIop = InstObjParams("vcvtb", "VcvtFpSFpHB", "FpRegRegOp", 1000 { "code": vcvtFpSFpHBCode, 1001 "predicate_test": predicateTest }, []) 1002 header_output += FpRegRegOpDeclare.subst(vcvtFpSFpHBIop); 1003 decoder_output += FpRegRegOpConstructor.subst(vcvtFpSFpHBIop); 1004 exec_output += PredOpExecute.subst(vcvtFpSFpHBIop); 1005 1006 vcmpSCode = vfpEnabledCheckCode + ''' | 1030 ''' 1031 vcvtFpSFpHBIop = InstObjParams("vcvtb", "VcvtFpSFpHB", "FpRegRegOp", 1032 { "code": vcvtFpSFpHBCode, 1033 "predicate_test": predicateTest }, []) 1034 header_output += FpRegRegOpDeclare.subst(vcvtFpSFpHBIop); 1035 decoder_output += FpRegRegOpConstructor.subst(vcvtFpSFpHBIop); 1036 exec_output += PredOpExecute.subst(vcvtFpSFpHBIop); 1037 1038 vcmpSCode = vfpEnabledCheckCode + ''' |
1007 FPSCR fpscr = Fpscr; | 1039 FPSCR fpscr = Fpscr | FpCondCodes; |
1008 vfpFlushToZero(fpscr, FpDest, FpOp1); 1009 if (FpDest == FpOp1) { 1010 fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 1011 } else if (FpDest < FpOp1) { 1012 fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 1013 } else if (FpDest > FpOp1) { 1014 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 1015 } else { 1016 const uint32_t qnan = 0x7fc00000; 1017 const bool nan1 = std::isnan(FpDest); 1018 const bool signal1 = nan1 && ((fpToBits(FpDest) & qnan) != qnan); 1019 const bool nan2 = std::isnan(FpOp1); 1020 const bool signal2 = nan2 && ((fpToBits(FpOp1) & qnan) != qnan); 1021 if (signal1 || signal2) 1022 fpscr.ioc = 1; 1023 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 1024 } | 1040 vfpFlushToZero(fpscr, FpDest, FpOp1); 1041 if (FpDest == FpOp1) { 1042 fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 1043 } else if (FpDest < FpOp1) { 1044 fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 1045 } else if (FpDest > FpOp1) { 1046 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 1047 } else { 1048 const uint32_t qnan = 0x7fc00000; 1049 const bool nan1 = std::isnan(FpDest); 1050 const bool signal1 = nan1 && ((fpToBits(FpDest) & qnan) != qnan); 1051 const bool nan2 = std::isnan(FpOp1); 1052 const bool signal2 = nan2 && ((fpToBits(FpOp1) & qnan) != qnan); 1053 if (signal1 || signal2) 1054 fpscr.ioc = 1; 1055 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 1056 } |
1025 Fpscr = fpscr; | 1057 FpCondCodes = fpscr & FpCondCodesMask; |
1026 ''' 1027 vcmpSIop = InstObjParams("vcmps", "VcmpS", "FpRegRegOp", 1028 { "code": vcmpSCode, 1029 "predicate_test": predicateTest }, []) 1030 header_output += FpRegRegOpDeclare.subst(vcmpSIop); 1031 decoder_output += FpRegRegOpConstructor.subst(vcmpSIop); 1032 exec_output += PredOpExecute.subst(vcmpSIop); 1033 1034 vcmpDCode = vfpEnabledCheckCode + ''' 1035 double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw); 1036 double cDest = dbl(FpDestP0.uw, FpDestP1.uw); | 1058 ''' 1059 vcmpSIop = InstObjParams("vcmps", "VcmpS", "FpRegRegOp", 1060 { "code": vcmpSCode, 1061 "predicate_test": predicateTest }, []) 1062 header_output += FpRegRegOpDeclare.subst(vcmpSIop); 1063 decoder_output += FpRegRegOpConstructor.subst(vcmpSIop); 1064 exec_output += PredOpExecute.subst(vcmpSIop); 1065 1066 vcmpDCode = vfpEnabledCheckCode + ''' 1067 double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw); 1068 double cDest = dbl(FpDestP0.uw, FpDestP1.uw); |
1037 FPSCR fpscr = Fpscr; | 1069 FPSCR fpscr = Fpscr | FpCondCodes; |
1038 vfpFlushToZero(fpscr, cDest, cOp1); 1039 if (cDest == cOp1) { 1040 fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 1041 } else if (cDest < cOp1) { 1042 fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 1043 } else if (cDest > cOp1) { 1044 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 1045 } else { 1046 const uint64_t qnan = ULL(0x7ff8000000000000); 1047 const bool nan1 = std::isnan(cDest); 1048 const bool signal1 = nan1 && ((fpToBits(cDest) & qnan) != qnan); 1049 const bool nan2 = std::isnan(cOp1); 1050 const bool signal2 = nan2 && ((fpToBits(cOp1) & qnan) != qnan); 1051 if (signal1 || signal2) 1052 fpscr.ioc = 1; 1053 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 1054 } | 1070 vfpFlushToZero(fpscr, cDest, cOp1); 1071 if (cDest == cOp1) { 1072 fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 1073 } else if (cDest < cOp1) { 1074 fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 1075 } else if (cDest > cOp1) { 1076 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 1077 } else { 1078 const uint64_t qnan = ULL(0x7ff8000000000000); 1079 const bool nan1 = std::isnan(cDest); 1080 const bool signal1 = nan1 && ((fpToBits(cDest) & qnan) != qnan); 1081 const bool nan2 = std::isnan(cOp1); 1082 const bool signal2 = nan2 && ((fpToBits(cOp1) & qnan) != qnan); 1083 if (signal1 || signal2) 1084 fpscr.ioc = 1; 1085 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 1086 } |
1055 Fpscr = fpscr; | 1087 FpCondCodes = fpscr & FpCondCodesMask; |
1056 ''' 1057 vcmpDIop = InstObjParams("vcmpd", "VcmpD", "FpRegRegOp", 1058 { "code": vcmpDCode, 1059 "predicate_test": predicateTest }, []) 1060 header_output += FpRegRegOpDeclare.subst(vcmpDIop); 1061 decoder_output += FpRegRegOpConstructor.subst(vcmpDIop); 1062 exec_output += PredOpExecute.subst(vcmpDIop); 1063 1064 vcmpZeroSCode = vfpEnabledCheckCode + ''' | 1088 ''' 1089 vcmpDIop = InstObjParams("vcmpd", "VcmpD", "FpRegRegOp", 1090 { "code": vcmpDCode, 1091 "predicate_test": predicateTest }, []) 1092 header_output += FpRegRegOpDeclare.subst(vcmpDIop); 1093 decoder_output += FpRegRegOpConstructor.subst(vcmpDIop); 1094 exec_output += PredOpExecute.subst(vcmpDIop); 1095 1096 vcmpZeroSCode = vfpEnabledCheckCode + ''' |
1065 FPSCR fpscr = Fpscr; | 1097 FPSCR fpscr = Fpscr | FpCondCodes; |
1066 vfpFlushToZero(fpscr, FpDest); 1067 // This only handles imm == 0 for now. 1068 assert(imm == 0); 1069 if (FpDest == imm) { 1070 fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 1071 } else if (FpDest < imm) { 1072 fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 1073 } else if (FpDest > imm) { 1074 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 1075 } else { 1076 const uint32_t qnan = 0x7fc00000; 1077 const bool nan = std::isnan(FpDest); 1078 const bool signal = nan && ((fpToBits(FpDest) & qnan) != qnan); 1079 if (signal) 1080 fpscr.ioc = 1; 1081 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 1082 } | 1098 vfpFlushToZero(fpscr, FpDest); 1099 // This only handles imm == 0 for now. 1100 assert(imm == 0); 1101 if (FpDest == imm) { 1102 fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 1103 } else if (FpDest < imm) { 1104 fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 1105 } else if (FpDest > imm) { 1106 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 1107 } else { 1108 const uint32_t qnan = 0x7fc00000; 1109 const bool nan = std::isnan(FpDest); 1110 const bool signal = nan && ((fpToBits(FpDest) & qnan) != qnan); 1111 if (signal) 1112 fpscr.ioc = 1; 1113 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 1114 } |
1083 Fpscr = fpscr; | 1115 FpCondCodes = fpscr & FpCondCodesMask; |
1084 ''' 1085 vcmpZeroSIop = InstObjParams("vcmpZeros", "VcmpZeroS", "FpRegImmOp", 1086 { "code": vcmpZeroSCode, 1087 "predicate_test": predicateTest }, []) 1088 header_output += FpRegImmOpDeclare.subst(vcmpZeroSIop); 1089 decoder_output += FpRegImmOpConstructor.subst(vcmpZeroSIop); 1090 exec_output += PredOpExecute.subst(vcmpZeroSIop); 1091 1092 vcmpZeroDCode = vfpEnabledCheckCode + ''' 1093 // This only handles imm == 0 for now. 1094 assert(imm == 0); 1095 double cDest = dbl(FpDestP0.uw, FpDestP1.uw); | 1116 ''' 1117 vcmpZeroSIop = InstObjParams("vcmpZeros", "VcmpZeroS", "FpRegImmOp", 1118 { "code": vcmpZeroSCode, 1119 "predicate_test": predicateTest }, []) 1120 header_output += FpRegImmOpDeclare.subst(vcmpZeroSIop); 1121 decoder_output += FpRegImmOpConstructor.subst(vcmpZeroSIop); 1122 exec_output += PredOpExecute.subst(vcmpZeroSIop); 1123 1124 vcmpZeroDCode = vfpEnabledCheckCode + ''' 1125 // This only handles imm == 0 for now. 1126 assert(imm == 0); 1127 double cDest = dbl(FpDestP0.uw, FpDestP1.uw); |
1096 FPSCR fpscr = Fpscr; | 1128 FPSCR fpscr = Fpscr | FpCondCodes; |
1097 vfpFlushToZero(fpscr, cDest); 1098 if (cDest == imm) { 1099 fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 1100 } else if (cDest < imm) { 1101 fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 1102 } else if (cDest > imm) { 1103 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 1104 } else { 1105 const uint64_t qnan = ULL(0x7ff8000000000000); 1106 const bool nan = std::isnan(cDest); 1107 const bool signal = nan && ((fpToBits(cDest) & qnan) != qnan); 1108 if (signal) 1109 fpscr.ioc = 1; 1110 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 1111 } | 1129 vfpFlushToZero(fpscr, cDest); 1130 if (cDest == imm) { 1131 fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 1132 } else if (cDest < imm) { 1133 fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 1134 } else if (cDest > imm) { 1135 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 1136 } else { 1137 const uint64_t qnan = ULL(0x7ff8000000000000); 1138 const bool nan = std::isnan(cDest); 1139 const bool signal = nan && ((fpToBits(cDest) & qnan) != qnan); 1140 if (signal) 1141 fpscr.ioc = 1; 1142 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 1143 } |
1112 Fpscr = fpscr; | 1144 FpCondCodes = fpscr & FpCondCodesMask; |
1113 ''' 1114 vcmpZeroDIop = InstObjParams("vcmpZerod", "VcmpZeroD", "FpRegImmOp", 1115 { "code": vcmpZeroDCode, 1116 "predicate_test": predicateTest }, []) 1117 header_output += FpRegImmOpDeclare.subst(vcmpZeroDIop); 1118 decoder_output += FpRegImmOpConstructor.subst(vcmpZeroDIop); 1119 exec_output += PredOpExecute.subst(vcmpZeroDIop); 1120 1121 vcmpeSCode = vfpEnabledCheckCode + ''' | 1145 ''' 1146 vcmpZeroDIop = InstObjParams("vcmpZerod", "VcmpZeroD", "FpRegImmOp", 1147 { "code": vcmpZeroDCode, 1148 "predicate_test": predicateTest }, []) 1149 header_output += FpRegImmOpDeclare.subst(vcmpZeroDIop); 1150 decoder_output += FpRegImmOpConstructor.subst(vcmpZeroDIop); 1151 exec_output += PredOpExecute.subst(vcmpZeroDIop); 1152 1153 vcmpeSCode = vfpEnabledCheckCode + ''' |
1122 FPSCR fpscr = Fpscr; | 1154 FPSCR fpscr = Fpscr | FpCondCodes; |
1123 vfpFlushToZero(fpscr, FpDest, FpOp1); 1124 if (FpDest == FpOp1) { 1125 fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 1126 } else if (FpDest < FpOp1) { 1127 fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 1128 } else if (FpDest > FpOp1) { 1129 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 1130 } else { 1131 fpscr.ioc = 1; 1132 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 1133 } | 1155 vfpFlushToZero(fpscr, FpDest, FpOp1); 1156 if (FpDest == FpOp1) { 1157 fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 1158 } else if (FpDest < FpOp1) { 1159 fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 1160 } else if (FpDest > FpOp1) { 1161 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 1162 } else { 1163 fpscr.ioc = 1; 1164 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 1165 } |
1134 Fpscr = fpscr; | 1166 FpCondCodes = fpscr & FpCondCodesMask; |
1135 ''' 1136 vcmpeSIop = InstObjParams("vcmpes", "VcmpeS", "FpRegRegOp", 1137 { "code": vcmpeSCode, 1138 "predicate_test": predicateTest }, []) 1139 header_output += FpRegRegOpDeclare.subst(vcmpeSIop); 1140 decoder_output += FpRegRegOpConstructor.subst(vcmpeSIop); 1141 exec_output += PredOpExecute.subst(vcmpeSIop); 1142 1143 vcmpeDCode = vfpEnabledCheckCode + ''' 1144 double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw); 1145 double cDest = dbl(FpDestP0.uw, FpDestP1.uw); | 1167 ''' 1168 vcmpeSIop = InstObjParams("vcmpes", "VcmpeS", "FpRegRegOp", 1169 { "code": vcmpeSCode, 1170 "predicate_test": predicateTest }, []) 1171 header_output += FpRegRegOpDeclare.subst(vcmpeSIop); 1172 decoder_output += FpRegRegOpConstructor.subst(vcmpeSIop); 1173 exec_output += PredOpExecute.subst(vcmpeSIop); 1174 1175 vcmpeDCode = vfpEnabledCheckCode + ''' 1176 double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw); 1177 double cDest = dbl(FpDestP0.uw, FpDestP1.uw); |
1146 FPSCR fpscr = Fpscr; | 1178 FPSCR fpscr = Fpscr | FpCondCodes; |
1147 vfpFlushToZero(fpscr, cDest, cOp1); 1148 if (cDest == cOp1) { 1149 fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 1150 } else if (cDest < cOp1) { 1151 fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 1152 } else if (cDest > cOp1) { 1153 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 1154 } else { 1155 fpscr.ioc = 1; 1156 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 1157 } | 1179 vfpFlushToZero(fpscr, cDest, cOp1); 1180 if (cDest == cOp1) { 1181 fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 1182 } else if (cDest < cOp1) { 1183 fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 1184 } else if (cDest > cOp1) { 1185 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 1186 } else { 1187 fpscr.ioc = 1; 1188 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 1189 } |
1158 Fpscr = fpscr; | 1190 FpCondCodes = fpscr & FpCondCodesMask; |
1159 ''' 1160 vcmpeDIop = InstObjParams("vcmped", "VcmpeD", "FpRegRegOp", 1161 { "code": vcmpeDCode, 1162 "predicate_test": predicateTest }, []) 1163 header_output += FpRegRegOpDeclare.subst(vcmpeDIop); 1164 decoder_output += FpRegRegOpConstructor.subst(vcmpeDIop); 1165 exec_output += PredOpExecute.subst(vcmpeDIop); 1166 1167 vcmpeZeroSCode = vfpEnabledCheckCode + ''' | 1191 ''' 1192 vcmpeDIop = InstObjParams("vcmped", "VcmpeD", "FpRegRegOp", 1193 { "code": vcmpeDCode, 1194 "predicate_test": predicateTest }, []) 1195 header_output += FpRegRegOpDeclare.subst(vcmpeDIop); 1196 decoder_output += FpRegRegOpConstructor.subst(vcmpeDIop); 1197 exec_output += PredOpExecute.subst(vcmpeDIop); 1198 1199 vcmpeZeroSCode = vfpEnabledCheckCode + ''' |
1168 FPSCR fpscr = Fpscr; | 1200 FPSCR fpscr = Fpscr | FpCondCodes; |
1169 vfpFlushToZero(fpscr, FpDest); 1170 if (FpDest == imm) { 1171 fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 1172 } else if (FpDest < imm) { 1173 fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 1174 } else if (FpDest > imm) { 1175 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 1176 } else { 1177 fpscr.ioc = 1; 1178 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 1179 } | 1201 vfpFlushToZero(fpscr, FpDest); 1202 if (FpDest == imm) { 1203 fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 1204 } else if (FpDest < imm) { 1205 fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 1206 } else if (FpDest > imm) { 1207 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 1208 } else { 1209 fpscr.ioc = 1; 1210 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 1211 } |
1180 Fpscr = fpscr; | 1212 FpCondCodes = fpscr & FpCondCodesMask; |
1181 ''' 1182 vcmpeZeroSIop = InstObjParams("vcmpeZeros", "VcmpeZeroS", "FpRegImmOp", 1183 { "code": vcmpeZeroSCode, 1184 "predicate_test": predicateTest }, []) 1185 header_output += FpRegImmOpDeclare.subst(vcmpeZeroSIop); 1186 decoder_output += FpRegImmOpConstructor.subst(vcmpeZeroSIop); 1187 exec_output += PredOpExecute.subst(vcmpeZeroSIop); 1188 1189 vcmpeZeroDCode = vfpEnabledCheckCode + ''' 1190 double cDest = dbl(FpDestP0.uw, FpDestP1.uw); | 1213 ''' 1214 vcmpeZeroSIop = InstObjParams("vcmpeZeros", "VcmpeZeroS", "FpRegImmOp", 1215 { "code": vcmpeZeroSCode, 1216 "predicate_test": predicateTest }, []) 1217 header_output += FpRegImmOpDeclare.subst(vcmpeZeroSIop); 1218 decoder_output += FpRegImmOpConstructor.subst(vcmpeZeroSIop); 1219 exec_output += PredOpExecute.subst(vcmpeZeroSIop); 1220 1221 vcmpeZeroDCode = vfpEnabledCheckCode + ''' 1222 double cDest = dbl(FpDestP0.uw, FpDestP1.uw); |
1191 FPSCR fpscr = Fpscr; | 1223 FPSCR fpscr = Fpscr | FpCondCodes; |
1192 vfpFlushToZero(fpscr, cDest); 1193 if (cDest == imm) { 1194 fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 1195 } else if (cDest < imm) { 1196 fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 1197 } else if (cDest > imm) { 1198 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 1199 } else { 1200 fpscr.ioc = 1; 1201 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 1202 } | 1224 vfpFlushToZero(fpscr, cDest); 1225 if (cDest == imm) { 1226 fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 1227 } else if (cDest < imm) { 1228 fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 1229 } else if (cDest > imm) { 1230 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 1231 } else { 1232 fpscr.ioc = 1; 1233 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 1234 } |
1203 Fpscr = fpscr; | 1235 FpCondCodes = fpscr & FpCondCodesMask; |
1204 ''' 1205 vcmpeZeroDIop = InstObjParams("vcmpeZerod", "VcmpeZeroD", "FpRegImmOp", 1206 { "code": vcmpeZeroDCode, 1207 "predicate_test": predicateTest }, []) 1208 header_output += FpRegImmOpDeclare.subst(vcmpeZeroDIop); 1209 decoder_output += FpRegImmOpConstructor.subst(vcmpeZeroDIop); 1210 exec_output += PredOpExecute.subst(vcmpeZeroDIop); 1211}}; 1212 1213let {{ 1214 1215 header_output = "" 1216 decoder_output = "" 1217 exec_output = "" 1218 1219 vcvtFpSFixedSCode = vfpEnabledCheckCode + ''' | 1236 ''' 1237 vcmpeZeroDIop = InstObjParams("vcmpeZerod", "VcmpeZeroD", "FpRegImmOp", 1238 { "code": vcmpeZeroDCode, 1239 "predicate_test": predicateTest }, []) 1240 header_output += FpRegImmOpDeclare.subst(vcmpeZeroDIop); 1241 decoder_output += FpRegImmOpConstructor.subst(vcmpeZeroDIop); 1242 exec_output += PredOpExecute.subst(vcmpeZeroDIop); 1243}}; 1244 1245let {{ 1246 1247 header_output = "" 1248 decoder_output = "" 1249 exec_output = "" 1250 1251 vcvtFpSFixedSCode = vfpEnabledCheckCode + ''' |
1220 FPSCR fpscr = Fpscr; | 1252 FPSCR fpscr = Fpscr | FpCondCodes; |
1221 vfpFlushToZero(fpscr, FpOp1); 1222 VfpSavedState state = prepFpState(fpscr.rMode); 1223 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 1224 FpDest.sw = vfpFpSToFixed(FpOp1, true, false, imm); 1225 __asm__ __volatile__("" :: "m" (FpDest.sw)); 1226 finishVfp(fpscr, state, fpscr.fz); | 1253 vfpFlushToZero(fpscr, FpOp1); 1254 VfpSavedState state = prepFpState(fpscr.rMode); 1255 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 1256 FpDest.sw = vfpFpSToFixed(FpOp1, true, false, imm); 1257 __asm__ __volatile__("" :: "m" (FpDest.sw)); 1258 finishVfp(fpscr, state, fpscr.fz); |
1227 Fpscr = fpscr; | 1259 FpCondCodes = fpscr & FpCondCodesMask; |
1228 ''' 1229 vcvtFpSFixedSIop = InstObjParams("vcvt", "VcvtFpSFixedS", "FpRegRegImmOp", 1230 { "code": vcvtFpSFixedSCode, 1231 "predicate_test": predicateTest }, []) 1232 header_output += FpRegRegImmOpDeclare.subst(vcvtFpSFixedSIop); 1233 decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpSFixedSIop); 1234 exec_output += PredOpExecute.subst(vcvtFpSFixedSIop); 1235 1236 vcvtFpSFixedDCode = vfpEnabledCheckCode + ''' | 1260 ''' 1261 vcvtFpSFixedSIop = InstObjParams("vcvt", "VcvtFpSFixedS", "FpRegRegImmOp", 1262 { "code": vcvtFpSFixedSCode, 1263 "predicate_test": predicateTest }, []) 1264 header_output += FpRegRegImmOpDeclare.subst(vcvtFpSFixedSIop); 1265 decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpSFixedSIop); 1266 exec_output += PredOpExecute.subst(vcvtFpSFixedSIop); 1267 1268 vcvtFpSFixedDCode = vfpEnabledCheckCode + ''' |
1237 FPSCR fpscr = Fpscr; | 1269 FPSCR fpscr = Fpscr | FpCondCodes; |
1238 double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw); 1239 vfpFlushToZero(fpscr, cOp1); 1240 VfpSavedState state = prepFpState(fpscr.rMode); 1241 __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); 1242 uint64_t mid = vfpFpDToFixed(cOp1, true, false, imm); 1243 __asm__ __volatile__("" :: "m" (mid)); 1244 finishVfp(fpscr, state, fpscr.fz); | 1270 double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw); 1271 vfpFlushToZero(fpscr, cOp1); 1272 VfpSavedState state = prepFpState(fpscr.rMode); 1273 __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); 1274 uint64_t mid = vfpFpDToFixed(cOp1, true, false, imm); 1275 __asm__ __volatile__("" :: "m" (mid)); 1276 finishVfp(fpscr, state, fpscr.fz); |
1245 Fpscr = fpscr; | 1277 FpCondCodes = fpscr & FpCondCodesMask; |
1246 FpDestP0.uw = mid; 1247 FpDestP1.uw = mid >> 32; 1248 ''' 1249 vcvtFpSFixedDIop = InstObjParams("vcvt", "VcvtFpSFixedD", "FpRegRegImmOp", 1250 { "code": vcvtFpSFixedDCode, 1251 "predicate_test": predicateTest }, []) 1252 header_output += FpRegRegImmOpDeclare.subst(vcvtFpSFixedDIop); 1253 decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpSFixedDIop); 1254 exec_output += PredOpExecute.subst(vcvtFpSFixedDIop); 1255 1256 vcvtFpUFixedSCode = vfpEnabledCheckCode + ''' | 1278 FpDestP0.uw = mid; 1279 FpDestP1.uw = mid >> 32; 1280 ''' 1281 vcvtFpSFixedDIop = InstObjParams("vcvt", "VcvtFpSFixedD", "FpRegRegImmOp", 1282 { "code": vcvtFpSFixedDCode, 1283 "predicate_test": predicateTest }, []) 1284 header_output += FpRegRegImmOpDeclare.subst(vcvtFpSFixedDIop); 1285 decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpSFixedDIop); 1286 exec_output += PredOpExecute.subst(vcvtFpSFixedDIop); 1287 1288 vcvtFpUFixedSCode = vfpEnabledCheckCode + ''' |
1257 FPSCR fpscr = Fpscr; | 1289 FPSCR fpscr = Fpscr | FpCondCodes; |
1258 vfpFlushToZero(fpscr, FpOp1); 1259 VfpSavedState state = prepFpState(fpscr.rMode); 1260 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 1261 FpDest.uw = vfpFpSToFixed(FpOp1, false, false, imm); 1262 __asm__ __volatile__("" :: "m" (FpDest.uw)); 1263 finishVfp(fpscr, state, fpscr.fz); | 1290 vfpFlushToZero(fpscr, FpOp1); 1291 VfpSavedState state = prepFpState(fpscr.rMode); 1292 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 1293 FpDest.uw = vfpFpSToFixed(FpOp1, false, false, imm); 1294 __asm__ __volatile__("" :: "m" (FpDest.uw)); 1295 finishVfp(fpscr, state, fpscr.fz); |
1264 Fpscr = fpscr; | 1296 FpCondCodes = fpscr & FpCondCodesMask; |
1265 ''' 1266 vcvtFpUFixedSIop = InstObjParams("vcvt", "VcvtFpUFixedS", "FpRegRegImmOp", 1267 { "code": vcvtFpUFixedSCode, 1268 "predicate_test": predicateTest }, []) 1269 header_output += FpRegRegImmOpDeclare.subst(vcvtFpUFixedSIop); 1270 decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpUFixedSIop); 1271 exec_output += PredOpExecute.subst(vcvtFpUFixedSIop); 1272 1273 vcvtFpUFixedDCode = vfpEnabledCheckCode + ''' | 1297 ''' 1298 vcvtFpUFixedSIop = InstObjParams("vcvt", "VcvtFpUFixedS", "FpRegRegImmOp", 1299 { "code": vcvtFpUFixedSCode, 1300 "predicate_test": predicateTest }, []) 1301 header_output += FpRegRegImmOpDeclare.subst(vcvtFpUFixedSIop); 1302 decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpUFixedSIop); 1303 exec_output += PredOpExecute.subst(vcvtFpUFixedSIop); 1304 1305 vcvtFpUFixedDCode = vfpEnabledCheckCode + ''' |
1274 FPSCR fpscr = Fpscr; | 1306 FPSCR fpscr = Fpscr | FpCondCodes; |
1275 double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw); 1276 vfpFlushToZero(fpscr, cOp1); 1277 VfpSavedState state = prepFpState(fpscr.rMode); 1278 __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); 1279 uint64_t mid = vfpFpDToFixed(cOp1, false, false, imm); 1280 __asm__ __volatile__("" :: "m" (mid)); 1281 finishVfp(fpscr, state, fpscr.fz); | 1307 double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw); 1308 vfpFlushToZero(fpscr, cOp1); 1309 VfpSavedState state = prepFpState(fpscr.rMode); 1310 __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); 1311 uint64_t mid = vfpFpDToFixed(cOp1, false, false, imm); 1312 __asm__ __volatile__("" :: "m" (mid)); 1313 finishVfp(fpscr, state, fpscr.fz); |
1282 Fpscr = fpscr; | 1314 FpCondCodes = fpscr & FpCondCodesMask; |
1283 FpDestP0.uw = mid; 1284 FpDestP1.uw = mid >> 32; 1285 ''' 1286 vcvtFpUFixedDIop = InstObjParams("vcvt", "VcvtFpUFixedD", "FpRegRegImmOp", 1287 { "code": vcvtFpUFixedDCode, 1288 "predicate_test": predicateTest }, []) 1289 header_output += FpRegRegImmOpDeclare.subst(vcvtFpUFixedDIop); 1290 decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpUFixedDIop); 1291 exec_output += PredOpExecute.subst(vcvtFpUFixedDIop); 1292 1293 vcvtSFixedFpSCode = vfpEnabledCheckCode + ''' | 1315 FpDestP0.uw = mid; 1316 FpDestP1.uw = mid >> 32; 1317 ''' 1318 vcvtFpUFixedDIop = InstObjParams("vcvt", "VcvtFpUFixedD", "FpRegRegImmOp", 1319 { "code": vcvtFpUFixedDCode, 1320 "predicate_test": predicateTest }, []) 1321 header_output += FpRegRegImmOpDeclare.subst(vcvtFpUFixedDIop); 1322 decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpUFixedDIop); 1323 exec_output += PredOpExecute.subst(vcvtFpUFixedDIop); 1324 1325 vcvtSFixedFpSCode = vfpEnabledCheckCode + ''' |
1294 FPSCR fpscr = Fpscr; | 1326 FPSCR fpscr = Fpscr | FpCondCodes; |
1295 VfpSavedState state = prepFpState(fpscr.rMode); 1296 __asm__ __volatile__("" : "=m" (FpOp1.sw) : "m" (FpOp1.sw)); 1297 FpDest = vfpSFixedToFpS(fpscr.fz, fpscr.dn, FpOp1.sw, false, imm); 1298 __asm__ __volatile__("" :: "m" (FpDest)); 1299 finishVfp(fpscr, state, fpscr.fz); | 1327 VfpSavedState state = prepFpState(fpscr.rMode); 1328 __asm__ __volatile__("" : "=m" (FpOp1.sw) : "m" (FpOp1.sw)); 1329 FpDest = vfpSFixedToFpS(fpscr.fz, fpscr.dn, FpOp1.sw, false, imm); 1330 __asm__ __volatile__("" :: "m" (FpDest)); 1331 finishVfp(fpscr, state, fpscr.fz); |
1300 Fpscr = fpscr; | 1332 FpCondCodes = fpscr & FpCondCodesMask; |
1301 ''' 1302 vcvtSFixedFpSIop = InstObjParams("vcvt", "VcvtSFixedFpS", "FpRegRegImmOp", 1303 { "code": vcvtSFixedFpSCode, 1304 "predicate_test": predicateTest }, []) 1305 header_output += FpRegRegImmOpDeclare.subst(vcvtSFixedFpSIop); 1306 decoder_output += FpRegRegImmOpConstructor.subst(vcvtSFixedFpSIop); 1307 exec_output += PredOpExecute.subst(vcvtSFixedFpSIop); 1308 1309 vcvtSFixedFpDCode = vfpEnabledCheckCode + ''' | 1333 ''' 1334 vcvtSFixedFpSIop = InstObjParams("vcvt", "VcvtSFixedFpS", "FpRegRegImmOp", 1335 { "code": vcvtSFixedFpSCode, 1336 "predicate_test": predicateTest }, []) 1337 header_output += FpRegRegImmOpDeclare.subst(vcvtSFixedFpSIop); 1338 decoder_output += FpRegRegImmOpConstructor.subst(vcvtSFixedFpSIop); 1339 exec_output += PredOpExecute.subst(vcvtSFixedFpSIop); 1340 1341 vcvtSFixedFpDCode = vfpEnabledCheckCode + ''' |
1310 FPSCR fpscr = Fpscr; | 1342 FPSCR fpscr = Fpscr | FpCondCodes; |
1311 uint64_t mid = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 1312 VfpSavedState state = prepFpState(fpscr.rMode); 1313 __asm__ __volatile__("" : "=m" (mid) : "m" (mid)); 1314 double cDest = vfpSFixedToFpD(fpscr.fz, fpscr.dn, mid, false, imm); 1315 __asm__ __volatile__("" :: "m" (cDest)); 1316 finishVfp(fpscr, state, fpscr.fz); | 1343 uint64_t mid = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 1344 VfpSavedState state = prepFpState(fpscr.rMode); 1345 __asm__ __volatile__("" : "=m" (mid) : "m" (mid)); 1346 double cDest = vfpSFixedToFpD(fpscr.fz, fpscr.dn, mid, false, imm); 1347 __asm__ __volatile__("" :: "m" (cDest)); 1348 finishVfp(fpscr, state, fpscr.fz); |
1317 Fpscr = fpscr; | 1349 FpCondCodes = fpscr & FpCondCodesMask; |
1318 FpDestP0.uw = dblLow(cDest); 1319 FpDestP1.uw = dblHi(cDest); 1320 ''' 1321 vcvtSFixedFpDIop = InstObjParams("vcvt", "VcvtSFixedFpD", "FpRegRegImmOp", 1322 { "code": vcvtSFixedFpDCode, 1323 "predicate_test": predicateTest }, []) 1324 header_output += FpRegRegImmOpDeclare.subst(vcvtSFixedFpDIop); 1325 decoder_output += FpRegRegImmOpConstructor.subst(vcvtSFixedFpDIop); 1326 exec_output += PredOpExecute.subst(vcvtSFixedFpDIop); 1327 1328 vcvtUFixedFpSCode = vfpEnabledCheckCode + ''' | 1350 FpDestP0.uw = dblLow(cDest); 1351 FpDestP1.uw = dblHi(cDest); 1352 ''' 1353 vcvtSFixedFpDIop = InstObjParams("vcvt", "VcvtSFixedFpD", "FpRegRegImmOp", 1354 { "code": vcvtSFixedFpDCode, 1355 "predicate_test": predicateTest }, []) 1356 header_output += FpRegRegImmOpDeclare.subst(vcvtSFixedFpDIop); 1357 decoder_output += FpRegRegImmOpConstructor.subst(vcvtSFixedFpDIop); 1358 exec_output += PredOpExecute.subst(vcvtSFixedFpDIop); 1359 1360 vcvtUFixedFpSCode = vfpEnabledCheckCode + ''' |
1329 FPSCR fpscr = Fpscr; | 1361 FPSCR fpscr = Fpscr | FpCondCodes; |
1330 VfpSavedState state = prepFpState(fpscr.rMode); 1331 __asm__ __volatile__("" : "=m" (FpOp1.uw) : "m" (FpOp1.uw)); 1332 FpDest = vfpUFixedToFpS(fpscr.fz, fpscr.dn, FpOp1.uw, false, imm); 1333 __asm__ __volatile__("" :: "m" (FpDest)); 1334 finishVfp(fpscr, state, fpscr.fz); | 1362 VfpSavedState state = prepFpState(fpscr.rMode); 1363 __asm__ __volatile__("" : "=m" (FpOp1.uw) : "m" (FpOp1.uw)); 1364 FpDest = vfpUFixedToFpS(fpscr.fz, fpscr.dn, FpOp1.uw, false, imm); 1365 __asm__ __volatile__("" :: "m" (FpDest)); 1366 finishVfp(fpscr, state, fpscr.fz); |
1335 Fpscr = fpscr; | 1367 FpCondCodes = fpscr & FpCondCodesMask; |
1336 ''' 1337 vcvtUFixedFpSIop = InstObjParams("vcvt", "VcvtUFixedFpS", "FpRegRegImmOp", 1338 { "code": vcvtUFixedFpSCode, 1339 "predicate_test": predicateTest }, []) 1340 header_output += FpRegRegImmOpDeclare.subst(vcvtUFixedFpSIop); 1341 decoder_output += FpRegRegImmOpConstructor.subst(vcvtUFixedFpSIop); 1342 exec_output += PredOpExecute.subst(vcvtUFixedFpSIop); 1343 1344 vcvtUFixedFpDCode = vfpEnabledCheckCode + ''' | 1368 ''' 1369 vcvtUFixedFpSIop = InstObjParams("vcvt", "VcvtUFixedFpS", "FpRegRegImmOp", 1370 { "code": vcvtUFixedFpSCode, 1371 "predicate_test": predicateTest }, []) 1372 header_output += FpRegRegImmOpDeclare.subst(vcvtUFixedFpSIop); 1373 decoder_output += FpRegRegImmOpConstructor.subst(vcvtUFixedFpSIop); 1374 exec_output += PredOpExecute.subst(vcvtUFixedFpSIop); 1375 1376 vcvtUFixedFpDCode = vfpEnabledCheckCode + ''' |
1345 FPSCR fpscr = Fpscr; | 1377 FPSCR fpscr = Fpscr | FpCondCodes; |
1346 uint64_t mid = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 1347 VfpSavedState state = prepFpState(fpscr.rMode); 1348 __asm__ __volatile__("" : "=m" (mid) : "m" (mid)); 1349 double cDest = vfpUFixedToFpD(fpscr.fz, fpscr.dn, mid, false, imm); 1350 __asm__ __volatile__("" :: "m" (cDest)); 1351 finishVfp(fpscr, state, fpscr.fz); | 1378 uint64_t mid = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 1379 VfpSavedState state = prepFpState(fpscr.rMode); 1380 __asm__ __volatile__("" : "=m" (mid) : "m" (mid)); 1381 double cDest = vfpUFixedToFpD(fpscr.fz, fpscr.dn, mid, false, imm); 1382 __asm__ __volatile__("" :: "m" (cDest)); 1383 finishVfp(fpscr, state, fpscr.fz); |
1352 Fpscr = fpscr; | 1384 FpCondCodes = fpscr & FpCondCodesMask; |
1353 FpDestP0.uw = dblLow(cDest); 1354 FpDestP1.uw = dblHi(cDest); 1355 ''' 1356 vcvtUFixedFpDIop = InstObjParams("vcvt", "VcvtUFixedFpD", "FpRegRegImmOp", 1357 { "code": vcvtUFixedFpDCode, 1358 "predicate_test": predicateTest }, []) 1359 header_output += FpRegRegImmOpDeclare.subst(vcvtUFixedFpDIop); 1360 decoder_output += FpRegRegImmOpConstructor.subst(vcvtUFixedFpDIop); 1361 exec_output += PredOpExecute.subst(vcvtUFixedFpDIop); 1362 1363 vcvtFpSHFixedSCode = vfpEnabledCheckCode + ''' | 1385 FpDestP0.uw = dblLow(cDest); 1386 FpDestP1.uw = dblHi(cDest); 1387 ''' 1388 vcvtUFixedFpDIop = InstObjParams("vcvt", "VcvtUFixedFpD", "FpRegRegImmOp", 1389 { "code": vcvtUFixedFpDCode, 1390 "predicate_test": predicateTest }, []) 1391 header_output += FpRegRegImmOpDeclare.subst(vcvtUFixedFpDIop); 1392 decoder_output += FpRegRegImmOpConstructor.subst(vcvtUFixedFpDIop); 1393 exec_output += PredOpExecute.subst(vcvtUFixedFpDIop); 1394 1395 vcvtFpSHFixedSCode = vfpEnabledCheckCode + ''' |
1364 FPSCR fpscr = Fpscr; | 1396 FPSCR fpscr = Fpscr | FpCondCodes; |
1365 vfpFlushToZero(fpscr, FpOp1); 1366 VfpSavedState state = prepFpState(fpscr.rMode); 1367 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 1368 FpDest.sh = vfpFpSToFixed(FpOp1, true, true, imm); 1369 __asm__ __volatile__("" :: "m" (FpDest.sh)); 1370 finishVfp(fpscr, state, fpscr.fz); | 1397 vfpFlushToZero(fpscr, FpOp1); 1398 VfpSavedState state = prepFpState(fpscr.rMode); 1399 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 1400 FpDest.sh = vfpFpSToFixed(FpOp1, true, true, imm); 1401 __asm__ __volatile__("" :: "m" (FpDest.sh)); 1402 finishVfp(fpscr, state, fpscr.fz); |
1371 Fpscr = fpscr; | 1403 FpCondCodes = fpscr & FpCondCodesMask; |
1372 ''' 1373 vcvtFpSHFixedSIop = InstObjParams("vcvt", "VcvtFpSHFixedS", 1374 "FpRegRegImmOp", 1375 { "code": vcvtFpSHFixedSCode, 1376 "predicate_test": predicateTest }, []) 1377 header_output += FpRegRegImmOpDeclare.subst(vcvtFpSHFixedSIop); 1378 decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpSHFixedSIop); 1379 exec_output += PredOpExecute.subst(vcvtFpSHFixedSIop); 1380 1381 vcvtFpSHFixedDCode = vfpEnabledCheckCode + ''' | 1404 ''' 1405 vcvtFpSHFixedSIop = InstObjParams("vcvt", "VcvtFpSHFixedS", 1406 "FpRegRegImmOp", 1407 { "code": vcvtFpSHFixedSCode, 1408 "predicate_test": predicateTest }, []) 1409 header_output += FpRegRegImmOpDeclare.subst(vcvtFpSHFixedSIop); 1410 decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpSHFixedSIop); 1411 exec_output += PredOpExecute.subst(vcvtFpSHFixedSIop); 1412 1413 vcvtFpSHFixedDCode = vfpEnabledCheckCode + ''' |
1382 FPSCR fpscr = Fpscr; | 1414 FPSCR fpscr = Fpscr | FpCondCodes; |
1383 double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw); 1384 vfpFlushToZero(fpscr, cOp1); 1385 VfpSavedState state = prepFpState(fpscr.rMode); 1386 __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); 1387 uint64_t result = vfpFpDToFixed(cOp1, true, true, imm); 1388 __asm__ __volatile__("" :: "m" (result)); 1389 finishVfp(fpscr, state, fpscr.fz); | 1415 double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw); 1416 vfpFlushToZero(fpscr, cOp1); 1417 VfpSavedState state = prepFpState(fpscr.rMode); 1418 __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); 1419 uint64_t result = vfpFpDToFixed(cOp1, true, true, imm); 1420 __asm__ __volatile__("" :: "m" (result)); 1421 finishVfp(fpscr, state, fpscr.fz); |
1390 Fpscr = fpscr; | 1422 FpCondCodes = fpscr & FpCondCodesMask; |
1391 FpDestP0.uw = result; 1392 FpDestP1.uw = result >> 32; 1393 ''' 1394 vcvtFpSHFixedDIop = InstObjParams("vcvt", "VcvtFpSHFixedD", 1395 "FpRegRegImmOp", 1396 { "code": vcvtFpSHFixedDCode, 1397 "predicate_test": predicateTest }, []) 1398 header_output += FpRegRegImmOpDeclare.subst(vcvtFpSHFixedDIop); 1399 decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpSHFixedDIop); 1400 exec_output += PredOpExecute.subst(vcvtFpSHFixedDIop); 1401 1402 vcvtFpUHFixedSCode = vfpEnabledCheckCode + ''' | 1423 FpDestP0.uw = result; 1424 FpDestP1.uw = result >> 32; 1425 ''' 1426 vcvtFpSHFixedDIop = InstObjParams("vcvt", "VcvtFpSHFixedD", 1427 "FpRegRegImmOp", 1428 { "code": vcvtFpSHFixedDCode, 1429 "predicate_test": predicateTest }, []) 1430 header_output += FpRegRegImmOpDeclare.subst(vcvtFpSHFixedDIop); 1431 decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpSHFixedDIop); 1432 exec_output += PredOpExecute.subst(vcvtFpSHFixedDIop); 1433 1434 vcvtFpUHFixedSCode = vfpEnabledCheckCode + ''' |
1403 FPSCR fpscr = Fpscr; | 1435 FPSCR fpscr = Fpscr | FpCondCodes; |
1404 vfpFlushToZero(fpscr, FpOp1); 1405 VfpSavedState state = prepFpState(fpscr.rMode); 1406 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 1407 FpDest.uh = vfpFpSToFixed(FpOp1, false, true, imm); 1408 __asm__ __volatile__("" :: "m" (FpDest.uh)); 1409 finishVfp(fpscr, state, fpscr.fz); | 1436 vfpFlushToZero(fpscr, FpOp1); 1437 VfpSavedState state = prepFpState(fpscr.rMode); 1438 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 1439 FpDest.uh = vfpFpSToFixed(FpOp1, false, true, imm); 1440 __asm__ __volatile__("" :: "m" (FpDest.uh)); 1441 finishVfp(fpscr, state, fpscr.fz); |
1410 Fpscr = fpscr; | 1442 FpCondCodes = fpscr & FpCondCodesMask; |
1411 ''' 1412 vcvtFpUHFixedSIop = InstObjParams("vcvt", "VcvtFpUHFixedS", 1413 "FpRegRegImmOp", 1414 { "code": vcvtFpUHFixedSCode, 1415 "predicate_test": predicateTest }, []) 1416 header_output += FpRegRegImmOpDeclare.subst(vcvtFpUHFixedSIop); 1417 decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpUHFixedSIop); 1418 exec_output += PredOpExecute.subst(vcvtFpUHFixedSIop); 1419 1420 vcvtFpUHFixedDCode = vfpEnabledCheckCode + ''' | 1443 ''' 1444 vcvtFpUHFixedSIop = InstObjParams("vcvt", "VcvtFpUHFixedS", 1445 "FpRegRegImmOp", 1446 { "code": vcvtFpUHFixedSCode, 1447 "predicate_test": predicateTest }, []) 1448 header_output += FpRegRegImmOpDeclare.subst(vcvtFpUHFixedSIop); 1449 decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpUHFixedSIop); 1450 exec_output += PredOpExecute.subst(vcvtFpUHFixedSIop); 1451 1452 vcvtFpUHFixedDCode = vfpEnabledCheckCode + ''' |
1421 FPSCR fpscr = Fpscr; | 1453 FPSCR fpscr = Fpscr | FpCondCodes; |
1422 double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw); 1423 vfpFlushToZero(fpscr, cOp1); 1424 VfpSavedState state = prepFpState(fpscr.rMode); 1425 __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); 1426 uint64_t mid = vfpFpDToFixed(cOp1, false, true, imm); 1427 __asm__ __volatile__("" :: "m" (mid)); 1428 finishVfp(fpscr, state, fpscr.fz); | 1454 double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw); 1455 vfpFlushToZero(fpscr, cOp1); 1456 VfpSavedState state = prepFpState(fpscr.rMode); 1457 __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); 1458 uint64_t mid = vfpFpDToFixed(cOp1, false, true, imm); 1459 __asm__ __volatile__("" :: "m" (mid)); 1460 finishVfp(fpscr, state, fpscr.fz); |
1429 Fpscr = fpscr; | 1461 FpCondCodes = fpscr & FpCondCodesMask; |
1430 FpDestP0.uw = mid; 1431 FpDestP1.uw = mid >> 32; 1432 ''' 1433 vcvtFpUHFixedDIop = InstObjParams("vcvt", "VcvtFpUHFixedD", 1434 "FpRegRegImmOp", 1435 { "code": vcvtFpUHFixedDCode, 1436 "predicate_test": predicateTest }, []) 1437 header_output += FpRegRegImmOpDeclare.subst(vcvtFpUHFixedDIop); 1438 decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpUHFixedDIop); 1439 exec_output += PredOpExecute.subst(vcvtFpUHFixedDIop); 1440 1441 vcvtSHFixedFpSCode = vfpEnabledCheckCode + ''' | 1462 FpDestP0.uw = mid; 1463 FpDestP1.uw = mid >> 32; 1464 ''' 1465 vcvtFpUHFixedDIop = InstObjParams("vcvt", "VcvtFpUHFixedD", 1466 "FpRegRegImmOp", 1467 { "code": vcvtFpUHFixedDCode, 1468 "predicate_test": predicateTest }, []) 1469 header_output += FpRegRegImmOpDeclare.subst(vcvtFpUHFixedDIop); 1470 decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpUHFixedDIop); 1471 exec_output += PredOpExecute.subst(vcvtFpUHFixedDIop); 1472 1473 vcvtSHFixedFpSCode = vfpEnabledCheckCode + ''' |
1442 FPSCR fpscr = Fpscr; | 1474 FPSCR fpscr = Fpscr | FpCondCodes; |
1443 VfpSavedState state = prepFpState(fpscr.rMode); 1444 __asm__ __volatile__("" : "=m" (FpOp1.sh) : "m" (FpOp1.sh)); 1445 FpDest = vfpSFixedToFpS(fpscr.fz, fpscr.dn, FpOp1.sh, true, imm); 1446 __asm__ __volatile__("" :: "m" (FpDest)); 1447 finishVfp(fpscr, state, fpscr.fz); | 1475 VfpSavedState state = prepFpState(fpscr.rMode); 1476 __asm__ __volatile__("" : "=m" (FpOp1.sh) : "m" (FpOp1.sh)); 1477 FpDest = vfpSFixedToFpS(fpscr.fz, fpscr.dn, FpOp1.sh, true, imm); 1478 __asm__ __volatile__("" :: "m" (FpDest)); 1479 finishVfp(fpscr, state, fpscr.fz); |
1448 Fpscr = fpscr; | 1480 FpCondCodes = fpscr & FpCondCodesMask; |
1449 ''' 1450 vcvtSHFixedFpSIop = InstObjParams("vcvt", "VcvtSHFixedFpS", 1451 "FpRegRegImmOp", 1452 { "code": vcvtSHFixedFpSCode, 1453 "predicate_test": predicateTest }, []) 1454 header_output += FpRegRegImmOpDeclare.subst(vcvtSHFixedFpSIop); 1455 decoder_output += FpRegRegImmOpConstructor.subst(vcvtSHFixedFpSIop); 1456 exec_output += PredOpExecute.subst(vcvtSHFixedFpSIop); 1457 1458 vcvtSHFixedFpDCode = vfpEnabledCheckCode + ''' | 1481 ''' 1482 vcvtSHFixedFpSIop = InstObjParams("vcvt", "VcvtSHFixedFpS", 1483 "FpRegRegImmOp", 1484 { "code": vcvtSHFixedFpSCode, 1485 "predicate_test": predicateTest }, []) 1486 header_output += FpRegRegImmOpDeclare.subst(vcvtSHFixedFpSIop); 1487 decoder_output += FpRegRegImmOpConstructor.subst(vcvtSHFixedFpSIop); 1488 exec_output += PredOpExecute.subst(vcvtSHFixedFpSIop); 1489 1490 vcvtSHFixedFpDCode = vfpEnabledCheckCode + ''' |
1459 FPSCR fpscr = Fpscr; | 1491 FPSCR fpscr = Fpscr | FpCondCodes; |
1460 uint64_t mid = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 1461 VfpSavedState state = prepFpState(fpscr.rMode); 1462 __asm__ __volatile__("" : "=m" (mid) : "m" (mid)); 1463 double cDest = vfpSFixedToFpD(fpscr.fz, fpscr.dn, mid, true, imm); 1464 __asm__ __volatile__("" :: "m" (cDest)); 1465 finishVfp(fpscr, state, fpscr.fz); | 1492 uint64_t mid = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 1493 VfpSavedState state = prepFpState(fpscr.rMode); 1494 __asm__ __volatile__("" : "=m" (mid) : "m" (mid)); 1495 double cDest = vfpSFixedToFpD(fpscr.fz, fpscr.dn, mid, true, imm); 1496 __asm__ __volatile__("" :: "m" (cDest)); 1497 finishVfp(fpscr, state, fpscr.fz); |
1466 Fpscr = fpscr; | 1498 FpCondCodes = fpscr & FpCondCodesMask; |
1467 FpDestP0.uw = dblLow(cDest); 1468 FpDestP1.uw = dblHi(cDest); 1469 ''' 1470 vcvtSHFixedFpDIop = InstObjParams("vcvt", "VcvtSHFixedFpD", 1471 "FpRegRegImmOp", 1472 { "code": vcvtSHFixedFpDCode, 1473 "predicate_test": predicateTest }, []) 1474 header_output += FpRegRegImmOpDeclare.subst(vcvtSHFixedFpDIop); 1475 decoder_output += FpRegRegImmOpConstructor.subst(vcvtSHFixedFpDIop); 1476 exec_output += PredOpExecute.subst(vcvtSHFixedFpDIop); 1477 1478 vcvtUHFixedFpSCode = vfpEnabledCheckCode + ''' | 1499 FpDestP0.uw = dblLow(cDest); 1500 FpDestP1.uw = dblHi(cDest); 1501 ''' 1502 vcvtSHFixedFpDIop = InstObjParams("vcvt", "VcvtSHFixedFpD", 1503 "FpRegRegImmOp", 1504 { "code": vcvtSHFixedFpDCode, 1505 "predicate_test": predicateTest }, []) 1506 header_output += FpRegRegImmOpDeclare.subst(vcvtSHFixedFpDIop); 1507 decoder_output += FpRegRegImmOpConstructor.subst(vcvtSHFixedFpDIop); 1508 exec_output += PredOpExecute.subst(vcvtSHFixedFpDIop); 1509 1510 vcvtUHFixedFpSCode = vfpEnabledCheckCode + ''' |
1479 FPSCR fpscr = Fpscr; | 1511 FPSCR fpscr = Fpscr | FpCondCodes; |
1480 VfpSavedState state = prepFpState(fpscr.rMode); 1481 __asm__ __volatile__("" : "=m" (FpOp1.uh) : "m" (FpOp1.uh)); 1482 FpDest = vfpUFixedToFpS(fpscr.fz, fpscr.dn, FpOp1.uh, true, imm); 1483 __asm__ __volatile__("" :: "m" (FpDest)); 1484 finishVfp(fpscr, state, fpscr.fz); | 1512 VfpSavedState state = prepFpState(fpscr.rMode); 1513 __asm__ __volatile__("" : "=m" (FpOp1.uh) : "m" (FpOp1.uh)); 1514 FpDest = vfpUFixedToFpS(fpscr.fz, fpscr.dn, FpOp1.uh, true, imm); 1515 __asm__ __volatile__("" :: "m" (FpDest)); 1516 finishVfp(fpscr, state, fpscr.fz); |
1485 Fpscr = fpscr; | 1517 FpCondCodes = fpscr & FpCondCodesMask; |
1486 ''' 1487 vcvtUHFixedFpSIop = InstObjParams("vcvt", "VcvtUHFixedFpS", 1488 "FpRegRegImmOp", 1489 { "code": vcvtUHFixedFpSCode, 1490 "predicate_test": predicateTest }, []) 1491 header_output += FpRegRegImmOpDeclare.subst(vcvtUHFixedFpSIop); 1492 decoder_output += FpRegRegImmOpConstructor.subst(vcvtUHFixedFpSIop); 1493 exec_output += PredOpExecute.subst(vcvtUHFixedFpSIop); 1494 1495 vcvtUHFixedFpDCode = vfpEnabledCheckCode + ''' | 1518 ''' 1519 vcvtUHFixedFpSIop = InstObjParams("vcvt", "VcvtUHFixedFpS", 1520 "FpRegRegImmOp", 1521 { "code": vcvtUHFixedFpSCode, 1522 "predicate_test": predicateTest }, []) 1523 header_output += FpRegRegImmOpDeclare.subst(vcvtUHFixedFpSIop); 1524 decoder_output += FpRegRegImmOpConstructor.subst(vcvtUHFixedFpSIop); 1525 exec_output += PredOpExecute.subst(vcvtUHFixedFpSIop); 1526 1527 vcvtUHFixedFpDCode = vfpEnabledCheckCode + ''' |
1496 FPSCR fpscr = Fpscr; | 1528 FPSCR fpscr = Fpscr | FpCondCodes; |
1497 uint64_t mid = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 1498 VfpSavedState state = prepFpState(fpscr.rMode); 1499 __asm__ __volatile__("" : "=m" (mid) : "m" (mid)); 1500 double cDest = vfpUFixedToFpD(fpscr.fz, fpscr.dn, mid, true, imm); 1501 __asm__ __volatile__("" :: "m" (cDest)); 1502 finishVfp(fpscr, state, fpscr.fz); | 1529 uint64_t mid = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 1530 VfpSavedState state = prepFpState(fpscr.rMode); 1531 __asm__ __volatile__("" : "=m" (mid) : "m" (mid)); 1532 double cDest = vfpUFixedToFpD(fpscr.fz, fpscr.dn, mid, true, imm); 1533 __asm__ __volatile__("" :: "m" (cDest)); 1534 finishVfp(fpscr, state, fpscr.fz); |
1503 Fpscr = fpscr; | 1535 FpCondCodes = fpscr & FpCondCodesMask; |
1504 FpDestP0.uw = dblLow(cDest); 1505 FpDestP1.uw = dblHi(cDest); 1506 ''' 1507 vcvtUHFixedFpDIop = InstObjParams("vcvt", "VcvtUHFixedFpD", 1508 "FpRegRegImmOp", 1509 { "code": vcvtUHFixedFpDCode, 1510 "predicate_test": predicateTest }, []) 1511 header_output += FpRegRegImmOpDeclare.subst(vcvtUHFixedFpDIop); 1512 decoder_output += FpRegRegImmOpConstructor.subst(vcvtUHFixedFpDIop); 1513 exec_output += PredOpExecute.subst(vcvtUHFixedFpDIop); 1514}}; | 1536 FpDestP0.uw = dblLow(cDest); 1537 FpDestP1.uw = dblHi(cDest); 1538 ''' 1539 vcvtUHFixedFpDIop = InstObjParams("vcvt", "VcvtUHFixedFpD", 1540 "FpRegRegImmOp", 1541 { "code": vcvtUHFixedFpDCode, 1542 "predicate_test": predicateTest }, []) 1543 header_output += FpRegRegImmOpDeclare.subst(vcvtUHFixedFpDIop); 1544 decoder_output += FpRegRegImmOpConstructor.subst(vcvtUHFixedFpDIop); 1545 exec_output += PredOpExecute.subst(vcvtUHFixedFpDIop); 1546}}; |