fp.isa (7639:8c09b7ff5b57) fp.isa (7640:5286a8a469c5)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 178 unchanged lines hidden (view full) ---

187
188let {{
189
190 header_output = ""
191 decoder_output = ""
192 exec_output = ""
193
194 vmsrIop = InstObjParams("vmsr", "Vmsr", "FpRegRegOp",
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 178 unchanged lines hidden (view full) ---

187
188let {{
189
190 header_output = ""
191 decoder_output = ""
192 exec_output = ""
193
194 vmsrIop = InstObjParams("vmsr", "Vmsr", "FpRegRegOp",
195 { "code": "MiscDest = Op1;",
195 { "code": vmsrrsEnabledCheckCode + \
196 "MiscDest = Op1;",
196 "predicate_test": predicateTest }, [])
197 header_output += FpRegRegOpDeclare.subst(vmsrIop);
198 decoder_output += FpRegRegOpConstructor.subst(vmsrIop);
199 exec_output += PredOpExecute.subst(vmsrIop);
200
201 vmrsIop = InstObjParams("vmrs", "Vmrs", "FpRegRegOp",
197 "predicate_test": predicateTest }, [])
198 header_output += FpRegRegOpDeclare.subst(vmsrIop);
199 decoder_output += FpRegRegOpConstructor.subst(vmsrIop);
200 exec_output += PredOpExecute.subst(vmsrIop);
201
202 vmrsIop = InstObjParams("vmrs", "Vmrs", "FpRegRegOp",
202 { "code": "Dest = MiscOp1;",
203 { "code": vmsrrsEnabledCheckCode + \
204 "Dest = MiscOp1;",
203 "predicate_test": predicateTest }, [])
204 header_output += FpRegRegOpDeclare.subst(vmrsIop);
205 decoder_output += FpRegRegOpConstructor.subst(vmrsIop);
206 exec_output += PredOpExecute.subst(vmrsIop);
207
208 vmrsApsrCode = "Dest = (MiscOp1 & imm) | (Dest & ~imm);"
209 vmrsApsrIop = InstObjParams("vmrs", "VmrsApsr", "FpRegRegImmOp",
210 { "code": vmrsApsrCode,
211 "predicate_test": predicateTest }, [])
212 header_output += FpRegRegImmOpDeclare.subst(vmrsApsrIop);
213 decoder_output += FpRegRegImmOpConstructor.subst(vmrsApsrIop);
214 exec_output += PredOpExecute.subst(vmrsApsrIop);
215
205 "predicate_test": predicateTest }, [])
206 header_output += FpRegRegOpDeclare.subst(vmrsIop);
207 decoder_output += FpRegRegOpConstructor.subst(vmrsIop);
208 exec_output += PredOpExecute.subst(vmrsIop);
209
210 vmrsApsrCode = "Dest = (MiscOp1 & imm) | (Dest & ~imm);"
211 vmrsApsrIop = InstObjParams("vmrs", "VmrsApsr", "FpRegRegImmOp",
212 { "code": vmrsApsrCode,
213 "predicate_test": predicateTest }, [])
214 header_output += FpRegRegImmOpDeclare.subst(vmrsApsrIop);
215 decoder_output += FpRegRegImmOpConstructor.subst(vmrsApsrIop);
216 exec_output += PredOpExecute.subst(vmrsApsrIop);
217
216 vmovImmSCode = '''
218 vmovImmSCode = vfpEnabledCheckCode + '''
217 FpDest.uw = bits(imm, 31, 0);
218 '''
219 vmovImmSIop = InstObjParams("vmov", "VmovImmS", "FpRegImmOp",
220 { "code": vmovImmSCode,
221 "predicate_test": predicateTest }, [])
222 header_output += FpRegImmOpDeclare.subst(vmovImmSIop);
223 decoder_output += FpRegImmOpConstructor.subst(vmovImmSIop);
224 exec_output += PredOpExecute.subst(vmovImmSIop);
225
219 FpDest.uw = bits(imm, 31, 0);
220 '''
221 vmovImmSIop = InstObjParams("vmov", "VmovImmS", "FpRegImmOp",
222 { "code": vmovImmSCode,
223 "predicate_test": predicateTest }, [])
224 header_output += FpRegImmOpDeclare.subst(vmovImmSIop);
225 decoder_output += FpRegImmOpConstructor.subst(vmovImmSIop);
226 exec_output += PredOpExecute.subst(vmovImmSIop);
227
226 vmovImmDCode = '''
228 vmovImmDCode = vfpEnabledCheckCode + '''
227 FpDestP0.uw = bits(imm, 31, 0);
228 FpDestP1.uw = bits(imm, 63, 32);
229 '''
230 vmovImmDIop = InstObjParams("vmov", "VmovImmD", "FpRegImmOp",
231 { "code": vmovImmDCode,
232 "predicate_test": predicateTest }, [])
233 header_output += FpRegImmOpDeclare.subst(vmovImmDIop);
234 decoder_output += FpRegImmOpConstructor.subst(vmovImmDIop);
235 exec_output += PredOpExecute.subst(vmovImmDIop);
236
229 FpDestP0.uw = bits(imm, 31, 0);
230 FpDestP1.uw = bits(imm, 63, 32);
231 '''
232 vmovImmDIop = InstObjParams("vmov", "VmovImmD", "FpRegImmOp",
233 { "code": vmovImmDCode,
234 "predicate_test": predicateTest }, [])
235 header_output += FpRegImmOpDeclare.subst(vmovImmDIop);
236 decoder_output += FpRegImmOpConstructor.subst(vmovImmDIop);
237 exec_output += PredOpExecute.subst(vmovImmDIop);
238
237 vmovImmQCode = '''
239 vmovImmQCode = vfpEnabledCheckCode + '''
238 FpDestP0.uw = bits(imm, 31, 0);
239 FpDestP1.uw = bits(imm, 63, 32);
240 FpDestP2.uw = bits(imm, 31, 0);
241 FpDestP3.uw = bits(imm, 63, 32);
242 '''
243 vmovImmQIop = InstObjParams("vmov", "VmovImmQ", "FpRegImmOp",
244 { "code": vmovImmQCode,
245 "predicate_test": predicateTest }, [])
246 header_output += FpRegImmOpDeclare.subst(vmovImmQIop);
247 decoder_output += FpRegImmOpConstructor.subst(vmovImmQIop);
248 exec_output += PredOpExecute.subst(vmovImmQIop);
249
240 FpDestP0.uw = bits(imm, 31, 0);
241 FpDestP1.uw = bits(imm, 63, 32);
242 FpDestP2.uw = bits(imm, 31, 0);
243 FpDestP3.uw = bits(imm, 63, 32);
244 '''
245 vmovImmQIop = InstObjParams("vmov", "VmovImmQ", "FpRegImmOp",
246 { "code": vmovImmQCode,
247 "predicate_test": predicateTest }, [])
248 header_output += FpRegImmOpDeclare.subst(vmovImmQIop);
249 decoder_output += FpRegImmOpConstructor.subst(vmovImmQIop);
250 exec_output += PredOpExecute.subst(vmovImmQIop);
251
250 vmovRegSCode = '''
252 vmovRegSCode = vfpEnabledCheckCode + '''
251 FpDest.uw = FpOp1.uw;
252 '''
253 vmovRegSIop = InstObjParams("vmov", "VmovRegS", "FpRegRegOp",
254 { "code": vmovRegSCode,
255 "predicate_test": predicateTest }, [])
256 header_output += FpRegRegOpDeclare.subst(vmovRegSIop);
257 decoder_output += FpRegRegOpConstructor.subst(vmovRegSIop);
258 exec_output += PredOpExecute.subst(vmovRegSIop);
259
253 FpDest.uw = FpOp1.uw;
254 '''
255 vmovRegSIop = InstObjParams("vmov", "VmovRegS", "FpRegRegOp",
256 { "code": vmovRegSCode,
257 "predicate_test": predicateTest }, [])
258 header_output += FpRegRegOpDeclare.subst(vmovRegSIop);
259 decoder_output += FpRegRegOpConstructor.subst(vmovRegSIop);
260 exec_output += PredOpExecute.subst(vmovRegSIop);
261
260 vmovRegDCode = '''
262 vmovRegDCode = vfpEnabledCheckCode + '''
261 FpDestP0.uw = FpOp1P0.uw;
262 FpDestP1.uw = FpOp1P1.uw;
263 '''
264 vmovRegDIop = InstObjParams("vmov", "VmovRegD", "FpRegRegOp",
265 { "code": vmovRegDCode,
266 "predicate_test": predicateTest }, [])
267 header_output += FpRegRegOpDeclare.subst(vmovRegDIop);
268 decoder_output += FpRegRegOpConstructor.subst(vmovRegDIop);
269 exec_output += PredOpExecute.subst(vmovRegDIop);
270
263 FpDestP0.uw = FpOp1P0.uw;
264 FpDestP1.uw = FpOp1P1.uw;
265 '''
266 vmovRegDIop = InstObjParams("vmov", "VmovRegD", "FpRegRegOp",
267 { "code": vmovRegDCode,
268 "predicate_test": predicateTest }, [])
269 header_output += FpRegRegOpDeclare.subst(vmovRegDIop);
270 decoder_output += FpRegRegOpConstructor.subst(vmovRegDIop);
271 exec_output += PredOpExecute.subst(vmovRegDIop);
272
271 vmovRegQCode = '''
273 vmovRegQCode = vfpEnabledCheckCode + '''
272 FpDestP0.uw = FpOp1P0.uw;
273 FpDestP1.uw = FpOp1P1.uw;
274 FpDestP2.uw = FpOp1P2.uw;
275 FpDestP3.uw = FpOp1P3.uw;
276 '''
277 vmovRegQIop = InstObjParams("vmov", "VmovRegQ", "FpRegRegOp",
278 { "code": vmovRegQCode,
279 "predicate_test": predicateTest }, [])
280 header_output += FpRegRegOpDeclare.subst(vmovRegQIop);
281 decoder_output += FpRegRegOpConstructor.subst(vmovRegQIop);
282 exec_output += PredOpExecute.subst(vmovRegQIop);
283
274 FpDestP0.uw = FpOp1P0.uw;
275 FpDestP1.uw = FpOp1P1.uw;
276 FpDestP2.uw = FpOp1P2.uw;
277 FpDestP3.uw = FpOp1P3.uw;
278 '''
279 vmovRegQIop = InstObjParams("vmov", "VmovRegQ", "FpRegRegOp",
280 { "code": vmovRegQCode,
281 "predicate_test": predicateTest }, [])
282 header_output += FpRegRegOpDeclare.subst(vmovRegQIop);
283 decoder_output += FpRegRegOpConstructor.subst(vmovRegQIop);
284 exec_output += PredOpExecute.subst(vmovRegQIop);
285
284 vmovCoreRegBCode = '''
286 vmovCoreRegBCode = vfpEnabledCheckCode + '''
285 FpDest.uw = insertBits(FpDest.uw, imm * 8 + 7, imm * 8, Op1.ub);
286 '''
287 vmovCoreRegBIop = InstObjParams("vmov", "VmovCoreRegB", "FpRegRegImmOp",
288 { "code": vmovCoreRegBCode,
289 "predicate_test": predicateTest }, [])
290 header_output += FpRegRegImmOpDeclare.subst(vmovCoreRegBIop);
291 decoder_output += FpRegRegImmOpConstructor.subst(vmovCoreRegBIop);
292 exec_output += PredOpExecute.subst(vmovCoreRegBIop);
293
287 FpDest.uw = insertBits(FpDest.uw, imm * 8 + 7, imm * 8, Op1.ub);
288 '''
289 vmovCoreRegBIop = InstObjParams("vmov", "VmovCoreRegB", "FpRegRegImmOp",
290 { "code": vmovCoreRegBCode,
291 "predicate_test": predicateTest }, [])
292 header_output += FpRegRegImmOpDeclare.subst(vmovCoreRegBIop);
293 decoder_output += FpRegRegImmOpConstructor.subst(vmovCoreRegBIop);
294 exec_output += PredOpExecute.subst(vmovCoreRegBIop);
295
294 vmovCoreRegHCode = '''
296 vmovCoreRegHCode = vfpEnabledCheckCode + '''
295 FpDest.uw = insertBits(FpDest.uw, imm * 16 + 15, imm * 16, Op1.uh);
296 '''
297 vmovCoreRegHIop = InstObjParams("vmov", "VmovCoreRegH", "FpRegRegImmOp",
298 { "code": vmovCoreRegHCode,
299 "predicate_test": predicateTest }, [])
300 header_output += FpRegRegImmOpDeclare.subst(vmovCoreRegHIop);
301 decoder_output += FpRegRegImmOpConstructor.subst(vmovCoreRegHIop);
302 exec_output += PredOpExecute.subst(vmovCoreRegHIop);
303
297 FpDest.uw = insertBits(FpDest.uw, imm * 16 + 15, imm * 16, Op1.uh);
298 '''
299 vmovCoreRegHIop = InstObjParams("vmov", "VmovCoreRegH", "FpRegRegImmOp",
300 { "code": vmovCoreRegHCode,
301 "predicate_test": predicateTest }, [])
302 header_output += FpRegRegImmOpDeclare.subst(vmovCoreRegHIop);
303 decoder_output += FpRegRegImmOpConstructor.subst(vmovCoreRegHIop);
304 exec_output += PredOpExecute.subst(vmovCoreRegHIop);
305
304 vmovCoreRegWCode = '''
306 vmovCoreRegWCode = vfpEnabledCheckCode + '''
305 FpDest.uw = Op1.uw;
306 '''
307 vmovCoreRegWIop = InstObjParams("vmov", "VmovCoreRegW", "FpRegRegOp",
308 { "code": vmovCoreRegWCode,
309 "predicate_test": predicateTest }, [])
310 header_output += FpRegRegOpDeclare.subst(vmovCoreRegWIop);
311 decoder_output += FpRegRegOpConstructor.subst(vmovCoreRegWIop);
312 exec_output += PredOpExecute.subst(vmovCoreRegWIop);
313
307 FpDest.uw = Op1.uw;
308 '''
309 vmovCoreRegWIop = InstObjParams("vmov", "VmovCoreRegW", "FpRegRegOp",
310 { "code": vmovCoreRegWCode,
311 "predicate_test": predicateTest }, [])
312 header_output += FpRegRegOpDeclare.subst(vmovCoreRegWIop);
313 decoder_output += FpRegRegOpConstructor.subst(vmovCoreRegWIop);
314 exec_output += PredOpExecute.subst(vmovCoreRegWIop);
315
314 vmovRegCoreUBCode = '''
316 vmovRegCoreUBCode = vfpEnabledCheckCode + '''
315 assert(imm < 4);
316 Dest = bits(FpOp1.uw, imm * 8 + 7, imm * 8);
317 '''
318 vmovRegCoreUBIop = InstObjParams("vmov", "VmovRegCoreUB", "FpRegRegImmOp",
319 { "code": vmovRegCoreUBCode,
320 "predicate_test": predicateTest }, [])
321 header_output += FpRegRegImmOpDeclare.subst(vmovRegCoreUBIop);
322 decoder_output += FpRegRegImmOpConstructor.subst(vmovRegCoreUBIop);
323 exec_output += PredOpExecute.subst(vmovRegCoreUBIop);
324
317 assert(imm < 4);
318 Dest = bits(FpOp1.uw, imm * 8 + 7, imm * 8);
319 '''
320 vmovRegCoreUBIop = InstObjParams("vmov", "VmovRegCoreUB", "FpRegRegImmOp",
321 { "code": vmovRegCoreUBCode,
322 "predicate_test": predicateTest }, [])
323 header_output += FpRegRegImmOpDeclare.subst(vmovRegCoreUBIop);
324 decoder_output += FpRegRegImmOpConstructor.subst(vmovRegCoreUBIop);
325 exec_output += PredOpExecute.subst(vmovRegCoreUBIop);
326
325 vmovRegCoreUHCode = '''
327 vmovRegCoreUHCode = vfpEnabledCheckCode + '''
326 assert(imm < 2);
327 Dest = bits(FpOp1.uw, imm * 16 + 15, imm * 16);
328 '''
329 vmovRegCoreUHIop = InstObjParams("vmov", "VmovRegCoreUH", "FpRegRegImmOp",
330 { "code": vmovRegCoreUHCode,
331 "predicate_test": predicateTest }, [])
332 header_output += FpRegRegImmOpDeclare.subst(vmovRegCoreUHIop);
333 decoder_output += FpRegRegImmOpConstructor.subst(vmovRegCoreUHIop);
334 exec_output += PredOpExecute.subst(vmovRegCoreUHIop);
335
328 assert(imm < 2);
329 Dest = bits(FpOp1.uw, imm * 16 + 15, imm * 16);
330 '''
331 vmovRegCoreUHIop = InstObjParams("vmov", "VmovRegCoreUH", "FpRegRegImmOp",
332 { "code": vmovRegCoreUHCode,
333 "predicate_test": predicateTest }, [])
334 header_output += FpRegRegImmOpDeclare.subst(vmovRegCoreUHIop);
335 decoder_output += FpRegRegImmOpConstructor.subst(vmovRegCoreUHIop);
336 exec_output += PredOpExecute.subst(vmovRegCoreUHIop);
337
336 vmovRegCoreSBCode = '''
338 vmovRegCoreSBCode = vfpEnabledCheckCode + '''
337 assert(imm < 4);
338 Dest = sext<8>(bits(FpOp1.uw, imm * 8 + 7, imm * 8));
339 '''
340 vmovRegCoreSBIop = InstObjParams("vmov", "VmovRegCoreSB", "FpRegRegImmOp",
341 { "code": vmovRegCoreSBCode,
342 "predicate_test": predicateTest }, [])
343 header_output += FpRegRegImmOpDeclare.subst(vmovRegCoreSBIop);
344 decoder_output += FpRegRegImmOpConstructor.subst(vmovRegCoreSBIop);
345 exec_output += PredOpExecute.subst(vmovRegCoreSBIop);
346
339 assert(imm < 4);
340 Dest = sext<8>(bits(FpOp1.uw, imm * 8 + 7, imm * 8));
341 '''
342 vmovRegCoreSBIop = InstObjParams("vmov", "VmovRegCoreSB", "FpRegRegImmOp",
343 { "code": vmovRegCoreSBCode,
344 "predicate_test": predicateTest }, [])
345 header_output += FpRegRegImmOpDeclare.subst(vmovRegCoreSBIop);
346 decoder_output += FpRegRegImmOpConstructor.subst(vmovRegCoreSBIop);
347 exec_output += PredOpExecute.subst(vmovRegCoreSBIop);
348
347 vmovRegCoreSHCode = '''
349 vmovRegCoreSHCode = vfpEnabledCheckCode + '''
348 assert(imm < 2);
349 Dest = sext<16>(bits(FpOp1.uw, imm * 16 + 15, imm * 16));
350 '''
351 vmovRegCoreSHIop = InstObjParams("vmov", "VmovRegCoreSH", "FpRegRegImmOp",
352 { "code": vmovRegCoreSHCode,
353 "predicate_test": predicateTest }, [])
354 header_output += FpRegRegImmOpDeclare.subst(vmovRegCoreSHIop);
355 decoder_output += FpRegRegImmOpConstructor.subst(vmovRegCoreSHIop);
356 exec_output += PredOpExecute.subst(vmovRegCoreSHIop);
357
350 assert(imm < 2);
351 Dest = sext<16>(bits(FpOp1.uw, imm * 16 + 15, imm * 16));
352 '''
353 vmovRegCoreSHIop = InstObjParams("vmov", "VmovRegCoreSH", "FpRegRegImmOp",
354 { "code": vmovRegCoreSHCode,
355 "predicate_test": predicateTest }, [])
356 header_output += FpRegRegImmOpDeclare.subst(vmovRegCoreSHIop);
357 decoder_output += FpRegRegImmOpConstructor.subst(vmovRegCoreSHIop);
358 exec_output += PredOpExecute.subst(vmovRegCoreSHIop);
359
358 vmovRegCoreWCode = '''
360 vmovRegCoreWCode = vfpEnabledCheckCode + '''
359 Dest = FpOp1.uw;
360 '''
361 vmovRegCoreWIop = InstObjParams("vmov", "VmovRegCoreW", "FpRegRegOp",
362 { "code": vmovRegCoreWCode,
363 "predicate_test": predicateTest }, [])
364 header_output += FpRegRegOpDeclare.subst(vmovRegCoreWIop);
365 decoder_output += FpRegRegOpConstructor.subst(vmovRegCoreWIop);
366 exec_output += PredOpExecute.subst(vmovRegCoreWIop);
367
361 Dest = FpOp1.uw;
362 '''
363 vmovRegCoreWIop = InstObjParams("vmov", "VmovRegCoreW", "FpRegRegOp",
364 { "code": vmovRegCoreWCode,
365 "predicate_test": predicateTest }, [])
366 header_output += FpRegRegOpDeclare.subst(vmovRegCoreWIop);
367 decoder_output += FpRegRegOpConstructor.subst(vmovRegCoreWIop);
368 exec_output += PredOpExecute.subst(vmovRegCoreWIop);
369
368 vmov2Reg2CoreCode = '''
370 vmov2Reg2CoreCode = vfpEnabledCheckCode + '''
369 FpDestP0.uw = Op1.uw;
370 FpDestP1.uw = Op2.uw;
371 '''
372 vmov2Reg2CoreIop = InstObjParams("vmov", "Vmov2Reg2Core", "FpRegRegRegOp",
373 { "code": vmov2Reg2CoreCode,
374 "predicate_test": predicateTest }, [])
375 header_output += FpRegRegRegOpDeclare.subst(vmov2Reg2CoreIop);
376 decoder_output += FpRegRegRegOpConstructor.subst(vmov2Reg2CoreIop);
377 exec_output += PredOpExecute.subst(vmov2Reg2CoreIop);
378
371 FpDestP0.uw = Op1.uw;
372 FpDestP1.uw = Op2.uw;
373 '''
374 vmov2Reg2CoreIop = InstObjParams("vmov", "Vmov2Reg2Core", "FpRegRegRegOp",
375 { "code": vmov2Reg2CoreCode,
376 "predicate_test": predicateTest }, [])
377 header_output += FpRegRegRegOpDeclare.subst(vmov2Reg2CoreIop);
378 decoder_output += FpRegRegRegOpConstructor.subst(vmov2Reg2CoreIop);
379 exec_output += PredOpExecute.subst(vmov2Reg2CoreIop);
380
379 vmov2Core2RegCode = '''
381 vmov2Core2RegCode = vfpEnabledCheckCode + '''
380 Dest.uw = FpOp2P0.uw;
381 Op1.uw = FpOp2P1.uw;
382 '''
383 vmov2Core2RegIop = InstObjParams("vmov", "Vmov2Core2Reg", "FpRegRegRegOp",
384 { "code": vmov2Core2RegCode,
385 "predicate_test": predicateTest }, [])
386 header_output += FpRegRegRegOpDeclare.subst(vmov2Core2RegIop);
387 decoder_output += FpRegRegRegOpConstructor.subst(vmov2Core2RegIop);
388 exec_output += PredOpExecute.subst(vmov2Core2RegIop);
389}};
390
391let {{
392
393 header_output = ""
394 decoder_output = ""
395 exec_output = ""
396
382 Dest.uw = FpOp2P0.uw;
383 Op1.uw = FpOp2P1.uw;
384 '''
385 vmov2Core2RegIop = InstObjParams("vmov", "Vmov2Core2Reg", "FpRegRegRegOp",
386 { "code": vmov2Core2RegCode,
387 "predicate_test": predicateTest }, [])
388 header_output += FpRegRegRegOpDeclare.subst(vmov2Core2RegIop);
389 decoder_output += FpRegRegRegOpConstructor.subst(vmov2Core2RegIop);
390 exec_output += PredOpExecute.subst(vmov2Core2RegIop);
391}};
392
393let {{
394
395 header_output = ""
396 decoder_output = ""
397 exec_output = ""
398
397 singleCode = '''
399 singleCode = vfpEnabledCheckCode + '''
398 FPSCR fpscr = Fpscr;
399 FpDest = %(op)s;
400 Fpscr = fpscr;
401 '''
402 singleBinOp = "binaryOp(fpscr, FpOp1, FpOp2," + \
403 "%(func)s, fpscr.fz, fpscr.dn, fpscr.rMode)"
404 singleUnaryOp = "unaryOp(fpscr, FpOp1, %(func)s, fpscr.fz, fpscr.rMode)"
400 FPSCR fpscr = Fpscr;
401 FpDest = %(op)s;
402 Fpscr = fpscr;
403 '''
404 singleBinOp = "binaryOp(fpscr, FpOp1, FpOp2," + \
405 "%(func)s, fpscr.fz, fpscr.dn, fpscr.rMode)"
406 singleUnaryOp = "unaryOp(fpscr, FpOp1, %(func)s, fpscr.fz, fpscr.rMode)"
405 doubleCode = '''
407 doubleCode = vfpEnabledCheckCode + '''
406 FPSCR fpscr = Fpscr;
407 double dest = %(op)s;
408 Fpscr = fpscr;
409 FpDestP0.uw = dblLow(dest);
410 FpDestP1.uw = dblHi(dest);
411 '''
412 doubleBinOp = '''
413 binaryOp(fpscr, dbl(FpOp1P0.uw, FpOp1P1.uw),

--- 81 unchanged lines hidden (view full) ---

495}};
496
497let {{
498
499 header_output = ""
500 decoder_output = ""
501 exec_output = ""
502
408 FPSCR fpscr = Fpscr;
409 double dest = %(op)s;
410 Fpscr = fpscr;
411 FpDestP0.uw = dblLow(dest);
412 FpDestP1.uw = dblHi(dest);
413 '''
414 doubleBinOp = '''
415 binaryOp(fpscr, dbl(FpOp1P0.uw, FpOp1P1.uw),

--- 81 unchanged lines hidden (view full) ---

497}};
498
499let {{
500
501 header_output = ""
502 decoder_output = ""
503 exec_output = ""
504
503 vmlaSCode = '''
505 vmlaSCode = vfpEnabledCheckCode + '''
504 FPSCR fpscr = Fpscr;
505 float mid = binaryOp(fpscr, FpOp1, FpOp2,
506 fpMulS, fpscr.fz, fpscr.dn, fpscr.rMode);
507 FpDest = binaryOp(fpscr, FpDest, mid, fpAddS,
508 fpscr.fz, fpscr.dn, fpscr.rMode);
509 Fpscr = fpscr;
510 '''
511 vmlaSIop = InstObjParams("vmlas", "VmlaS", "FpRegRegRegOp",
512 { "code": vmlaSCode,
513 "predicate_test": predicateTest }, [])
514 header_output += FpRegRegRegOpDeclare.subst(vmlaSIop);
515 decoder_output += FpRegRegRegOpConstructor.subst(vmlaSIop);
516 exec_output += PredOpExecute.subst(vmlaSIop);
517
506 FPSCR fpscr = Fpscr;
507 float mid = binaryOp(fpscr, FpOp1, FpOp2,
508 fpMulS, fpscr.fz, fpscr.dn, fpscr.rMode);
509 FpDest = binaryOp(fpscr, FpDest, mid, fpAddS,
510 fpscr.fz, fpscr.dn, fpscr.rMode);
511 Fpscr = fpscr;
512 '''
513 vmlaSIop = InstObjParams("vmlas", "VmlaS", "FpRegRegRegOp",
514 { "code": vmlaSCode,
515 "predicate_test": predicateTest }, [])
516 header_output += FpRegRegRegOpDeclare.subst(vmlaSIop);
517 decoder_output += FpRegRegRegOpConstructor.subst(vmlaSIop);
518 exec_output += PredOpExecute.subst(vmlaSIop);
519
518 vmlaDCode = '''
520 vmlaDCode = vfpEnabledCheckCode + '''
519 FPSCR fpscr = Fpscr;
520 double mid = binaryOp(fpscr, dbl(FpOp1P0.uw, FpOp1P1.uw),
521 dbl(FpOp2P0.uw, FpOp2P1.uw),
522 fpMulD, fpscr.fz, fpscr.dn, fpscr.rMode);
523 double dest = binaryOp(fpscr, dbl(FpDestP0.uw, FpDestP1.uw),
524 mid, fpAddD, fpscr.fz,
525 fpscr.dn, fpscr.rMode);
526 Fpscr = fpscr;
527 FpDestP0.uw = dblLow(dest);
528 FpDestP1.uw = dblHi(dest);
529 '''
530 vmlaDIop = InstObjParams("vmlad", "VmlaD", "FpRegRegRegOp",
531 { "code": vmlaDCode,
532 "predicate_test": predicateTest }, [])
533 header_output += FpRegRegRegOpDeclare.subst(vmlaDIop);
534 decoder_output += FpRegRegRegOpConstructor.subst(vmlaDIop);
535 exec_output += PredOpExecute.subst(vmlaDIop);
536
521 FPSCR fpscr = Fpscr;
522 double mid = binaryOp(fpscr, dbl(FpOp1P0.uw, FpOp1P1.uw),
523 dbl(FpOp2P0.uw, FpOp2P1.uw),
524 fpMulD, fpscr.fz, fpscr.dn, fpscr.rMode);
525 double dest = binaryOp(fpscr, dbl(FpDestP0.uw, FpDestP1.uw),
526 mid, fpAddD, fpscr.fz,
527 fpscr.dn, fpscr.rMode);
528 Fpscr = fpscr;
529 FpDestP0.uw = dblLow(dest);
530 FpDestP1.uw = dblHi(dest);
531 '''
532 vmlaDIop = InstObjParams("vmlad", "VmlaD", "FpRegRegRegOp",
533 { "code": vmlaDCode,
534 "predicate_test": predicateTest }, [])
535 header_output += FpRegRegRegOpDeclare.subst(vmlaDIop);
536 decoder_output += FpRegRegRegOpConstructor.subst(vmlaDIop);
537 exec_output += PredOpExecute.subst(vmlaDIop);
538
537 vmlsSCode = '''
539 vmlsSCode = vfpEnabledCheckCode + '''
538 FPSCR fpscr = Fpscr;
539 float mid = binaryOp(fpscr, FpOp1, FpOp2,
540 fpMulS, fpscr.fz, fpscr.dn, fpscr.rMode);
541 FpDest = binaryOp(fpscr, FpDest, -mid, fpAddS,
542 fpscr.fz, fpscr.dn, fpscr.rMode);
543 Fpscr = fpscr;
544 '''
545 vmlsSIop = InstObjParams("vmlss", "VmlsS", "FpRegRegRegOp",
546 { "code": vmlsSCode,
547 "predicate_test": predicateTest }, [])
548 header_output += FpRegRegRegOpDeclare.subst(vmlsSIop);
549 decoder_output += FpRegRegRegOpConstructor.subst(vmlsSIop);
550 exec_output += PredOpExecute.subst(vmlsSIop);
551
540 FPSCR fpscr = Fpscr;
541 float mid = binaryOp(fpscr, FpOp1, FpOp2,
542 fpMulS, fpscr.fz, fpscr.dn, fpscr.rMode);
543 FpDest = binaryOp(fpscr, FpDest, -mid, fpAddS,
544 fpscr.fz, fpscr.dn, fpscr.rMode);
545 Fpscr = fpscr;
546 '''
547 vmlsSIop = InstObjParams("vmlss", "VmlsS", "FpRegRegRegOp",
548 { "code": vmlsSCode,
549 "predicate_test": predicateTest }, [])
550 header_output += FpRegRegRegOpDeclare.subst(vmlsSIop);
551 decoder_output += FpRegRegRegOpConstructor.subst(vmlsSIop);
552 exec_output += PredOpExecute.subst(vmlsSIop);
553
552 vmlsDCode = '''
554 vmlsDCode = vfpEnabledCheckCode + '''
553 FPSCR fpscr = Fpscr;
554 double mid = binaryOp(fpscr, dbl(FpOp1P0.uw, FpOp1P1.uw),
555 dbl(FpOp2P0.uw, FpOp2P1.uw),
556 fpMulD, fpscr.fz, fpscr.dn, fpscr.rMode);
557 double dest = binaryOp(fpscr, dbl(FpDestP0.uw, FpDestP1.uw),
558 -mid, fpAddD, fpscr.fz,
559 fpscr.dn, fpscr.rMode);
560 Fpscr = fpscr;
561 FpDestP0.uw = dblLow(dest);
562 FpDestP1.uw = dblHi(dest);
563 '''
564 vmlsDIop = InstObjParams("vmlsd", "VmlsD", "FpRegRegRegOp",
565 { "code": vmlsDCode,
566 "predicate_test": predicateTest }, [])
567 header_output += FpRegRegRegOpDeclare.subst(vmlsDIop);
568 decoder_output += FpRegRegRegOpConstructor.subst(vmlsDIop);
569 exec_output += PredOpExecute.subst(vmlsDIop);
570
555 FPSCR fpscr = Fpscr;
556 double mid = binaryOp(fpscr, dbl(FpOp1P0.uw, FpOp1P1.uw),
557 dbl(FpOp2P0.uw, FpOp2P1.uw),
558 fpMulD, fpscr.fz, fpscr.dn, fpscr.rMode);
559 double dest = binaryOp(fpscr, dbl(FpDestP0.uw, FpDestP1.uw),
560 -mid, fpAddD, fpscr.fz,
561 fpscr.dn, fpscr.rMode);
562 Fpscr = fpscr;
563 FpDestP0.uw = dblLow(dest);
564 FpDestP1.uw = dblHi(dest);
565 '''
566 vmlsDIop = InstObjParams("vmlsd", "VmlsD", "FpRegRegRegOp",
567 { "code": vmlsDCode,
568 "predicate_test": predicateTest }, [])
569 header_output += FpRegRegRegOpDeclare.subst(vmlsDIop);
570 decoder_output += FpRegRegRegOpConstructor.subst(vmlsDIop);
571 exec_output += PredOpExecute.subst(vmlsDIop);
572
571 vnmlaSCode = '''
573 vnmlaSCode = vfpEnabledCheckCode + '''
572 FPSCR fpscr = Fpscr;
573 float mid = binaryOp(fpscr, FpOp1, FpOp2,
574 fpMulS, fpscr.fz, fpscr.dn, fpscr.rMode);
575 FpDest = binaryOp(fpscr, -FpDest, -mid, fpAddS,
576 fpscr.fz, fpscr.dn, fpscr.rMode);
577 Fpscr = fpscr;
578 '''
579 vnmlaSIop = InstObjParams("vnmlas", "VnmlaS", "FpRegRegRegOp",
580 { "code": vnmlaSCode,
581 "predicate_test": predicateTest }, [])
582 header_output += FpRegRegRegOpDeclare.subst(vnmlaSIop);
583 decoder_output += FpRegRegRegOpConstructor.subst(vnmlaSIop);
584 exec_output += PredOpExecute.subst(vnmlaSIop);
585
574 FPSCR fpscr = Fpscr;
575 float mid = binaryOp(fpscr, FpOp1, FpOp2,
576 fpMulS, fpscr.fz, fpscr.dn, fpscr.rMode);
577 FpDest = binaryOp(fpscr, -FpDest, -mid, fpAddS,
578 fpscr.fz, fpscr.dn, fpscr.rMode);
579 Fpscr = fpscr;
580 '''
581 vnmlaSIop = InstObjParams("vnmlas", "VnmlaS", "FpRegRegRegOp",
582 { "code": vnmlaSCode,
583 "predicate_test": predicateTest }, [])
584 header_output += FpRegRegRegOpDeclare.subst(vnmlaSIop);
585 decoder_output += FpRegRegRegOpConstructor.subst(vnmlaSIop);
586 exec_output += PredOpExecute.subst(vnmlaSIop);
587
586 vnmlaDCode = '''
588 vnmlaDCode = vfpEnabledCheckCode + '''
587 FPSCR fpscr = Fpscr;
588 double mid = binaryOp(fpscr, dbl(FpOp1P0.uw, FpOp1P1.uw),
589 dbl(FpOp2P0.uw, FpOp2P1.uw),
590 fpMulD, fpscr.fz, fpscr.dn, fpscr.rMode);
591 double dest = binaryOp(fpscr, -dbl(FpDestP0.uw, FpDestP1.uw),
592 -mid, fpAddD, fpscr.fz,
593 fpscr.dn, fpscr.rMode);
594 Fpscr = fpscr;
595 FpDestP0.uw = dblLow(dest);
596 FpDestP1.uw = dblHi(dest);
597 '''
598 vnmlaDIop = InstObjParams("vnmlad", "VnmlaD", "FpRegRegRegOp",
599 { "code": vnmlaDCode,
600 "predicate_test": predicateTest }, [])
601 header_output += FpRegRegRegOpDeclare.subst(vnmlaDIop);
602 decoder_output += FpRegRegRegOpConstructor.subst(vnmlaDIop);
603 exec_output += PredOpExecute.subst(vnmlaDIop);
604
589 FPSCR fpscr = Fpscr;
590 double mid = binaryOp(fpscr, dbl(FpOp1P0.uw, FpOp1P1.uw),
591 dbl(FpOp2P0.uw, FpOp2P1.uw),
592 fpMulD, fpscr.fz, fpscr.dn, fpscr.rMode);
593 double dest = binaryOp(fpscr, -dbl(FpDestP0.uw, FpDestP1.uw),
594 -mid, fpAddD, fpscr.fz,
595 fpscr.dn, fpscr.rMode);
596 Fpscr = fpscr;
597 FpDestP0.uw = dblLow(dest);
598 FpDestP1.uw = dblHi(dest);
599 '''
600 vnmlaDIop = InstObjParams("vnmlad", "VnmlaD", "FpRegRegRegOp",
601 { "code": vnmlaDCode,
602 "predicate_test": predicateTest }, [])
603 header_output += FpRegRegRegOpDeclare.subst(vnmlaDIop);
604 decoder_output += FpRegRegRegOpConstructor.subst(vnmlaDIop);
605 exec_output += PredOpExecute.subst(vnmlaDIop);
606
605 vnmlsSCode = '''
607 vnmlsSCode = vfpEnabledCheckCode + '''
606 FPSCR fpscr = Fpscr;
607 float mid = binaryOp(fpscr, FpOp1, FpOp2,
608 fpMulS, fpscr.fz, fpscr.dn, fpscr.rMode);
609 FpDest = binaryOp(fpscr, -FpDest, mid, fpAddS,
610 fpscr.fz, fpscr.dn, fpscr.rMode);
611 Fpscr = fpscr;
612 '''
613 vnmlsSIop = InstObjParams("vnmlss", "VnmlsS", "FpRegRegRegOp",
614 { "code": vnmlsSCode,
615 "predicate_test": predicateTest }, [])
616 header_output += FpRegRegRegOpDeclare.subst(vnmlsSIop);
617 decoder_output += FpRegRegRegOpConstructor.subst(vnmlsSIop);
618 exec_output += PredOpExecute.subst(vnmlsSIop);
619
608 FPSCR fpscr = Fpscr;
609 float mid = binaryOp(fpscr, FpOp1, FpOp2,
610 fpMulS, fpscr.fz, fpscr.dn, fpscr.rMode);
611 FpDest = binaryOp(fpscr, -FpDest, mid, fpAddS,
612 fpscr.fz, fpscr.dn, fpscr.rMode);
613 Fpscr = fpscr;
614 '''
615 vnmlsSIop = InstObjParams("vnmlss", "VnmlsS", "FpRegRegRegOp",
616 { "code": vnmlsSCode,
617 "predicate_test": predicateTest }, [])
618 header_output += FpRegRegRegOpDeclare.subst(vnmlsSIop);
619 decoder_output += FpRegRegRegOpConstructor.subst(vnmlsSIop);
620 exec_output += PredOpExecute.subst(vnmlsSIop);
621
620 vnmlsDCode = '''
622 vnmlsDCode = vfpEnabledCheckCode + '''
621 FPSCR fpscr = Fpscr;
622 double mid = binaryOp(fpscr, dbl(FpOp1P0.uw, FpOp1P1.uw),
623 dbl(FpOp2P0.uw, FpOp2P1.uw),
624 fpMulD, fpscr.fz, fpscr.dn, fpscr.rMode);
625 double dest = binaryOp(fpscr, -dbl(FpDestP0.uw, FpDestP1.uw),
626 mid, fpAddD, fpscr.fz,
627 fpscr.dn, fpscr.rMode);
628 Fpscr = fpscr;
629 FpDestP0.uw = dblLow(dest);
630 FpDestP1.uw = dblHi(dest);
631 '''
632 vnmlsDIop = InstObjParams("vnmlsd", "VnmlsD", "FpRegRegRegOp",
633 { "code": vnmlsDCode,
634 "predicate_test": predicateTest }, [])
635 header_output += FpRegRegRegOpDeclare.subst(vnmlsDIop);
636 decoder_output += FpRegRegRegOpConstructor.subst(vnmlsDIop);
637 exec_output += PredOpExecute.subst(vnmlsDIop);
638
623 FPSCR fpscr = Fpscr;
624 double mid = binaryOp(fpscr, dbl(FpOp1P0.uw, FpOp1P1.uw),
625 dbl(FpOp2P0.uw, FpOp2P1.uw),
626 fpMulD, fpscr.fz, fpscr.dn, fpscr.rMode);
627 double dest = binaryOp(fpscr, -dbl(FpDestP0.uw, FpDestP1.uw),
628 mid, fpAddD, fpscr.fz,
629 fpscr.dn, fpscr.rMode);
630 Fpscr = fpscr;
631 FpDestP0.uw = dblLow(dest);
632 FpDestP1.uw = dblHi(dest);
633 '''
634 vnmlsDIop = InstObjParams("vnmlsd", "VnmlsD", "FpRegRegRegOp",
635 { "code": vnmlsDCode,
636 "predicate_test": predicateTest }, [])
637 header_output += FpRegRegRegOpDeclare.subst(vnmlsDIop);
638 decoder_output += FpRegRegRegOpConstructor.subst(vnmlsDIop);
639 exec_output += PredOpExecute.subst(vnmlsDIop);
640
639 vnmulSCode = '''
641 vnmulSCode = vfpEnabledCheckCode + '''
640 FPSCR fpscr = Fpscr;
641 FpDest = -binaryOp(fpscr, FpOp1, FpOp2, fpMulS,
642 fpscr.fz, fpscr.dn, fpscr.rMode);
643 Fpscr = fpscr;
644 '''
645 vnmulSIop = InstObjParams("vnmuls", "VnmulS", "FpRegRegRegOp",
646 { "code": vnmulSCode,
647 "predicate_test": predicateTest }, [])
648 header_output += FpRegRegRegOpDeclare.subst(vnmulSIop);
649 decoder_output += FpRegRegRegOpConstructor.subst(vnmulSIop);
650 exec_output += PredOpExecute.subst(vnmulSIop);
651
642 FPSCR fpscr = Fpscr;
643 FpDest = -binaryOp(fpscr, FpOp1, FpOp2, fpMulS,
644 fpscr.fz, fpscr.dn, fpscr.rMode);
645 Fpscr = fpscr;
646 '''
647 vnmulSIop = InstObjParams("vnmuls", "VnmulS", "FpRegRegRegOp",
648 { "code": vnmulSCode,
649 "predicate_test": predicateTest }, [])
650 header_output += FpRegRegRegOpDeclare.subst(vnmulSIop);
651 decoder_output += FpRegRegRegOpConstructor.subst(vnmulSIop);
652 exec_output += PredOpExecute.subst(vnmulSIop);
653
652 vnmulDCode = '''
654 vnmulDCode = vfpEnabledCheckCode + '''
653 FPSCR fpscr = Fpscr;
654 double dest = -binaryOp(fpscr, dbl(FpOp1P0.uw, FpOp1P1.uw),
655 dbl(FpOp2P0.uw, FpOp2P1.uw),
656 fpMulD, fpscr.fz, fpscr.dn,
657 fpscr.rMode);
658 Fpscr = fpscr;
659 FpDestP0.uw = dblLow(dest);
660 FpDestP1.uw = dblHi(dest);

--- 7 unchanged lines hidden (view full) ---

668}};
669
670let {{
671
672 header_output = ""
673 decoder_output = ""
674 exec_output = ""
675
655 FPSCR fpscr = Fpscr;
656 double dest = -binaryOp(fpscr, dbl(FpOp1P0.uw, FpOp1P1.uw),
657 dbl(FpOp2P0.uw, FpOp2P1.uw),
658 fpMulD, fpscr.fz, fpscr.dn,
659 fpscr.rMode);
660 Fpscr = fpscr;
661 FpDestP0.uw = dblLow(dest);
662 FpDestP1.uw = dblHi(dest);

--- 7 unchanged lines hidden (view full) ---

670}};
671
672let {{
673
674 header_output = ""
675 decoder_output = ""
676 exec_output = ""
677
676 vcvtUIntFpSCode = '''
678 vcvtUIntFpSCode = vfpEnabledCheckCode + '''
677 FPSCR fpscr = Fpscr;
678 VfpSavedState state = prepFpState(fpscr.rMode);
679 __asm__ __volatile__("" : "=m" (FpOp1.uw) : "m" (FpOp1.uw));
680 FpDest = FpOp1.uw;
681 __asm__ __volatile__("" :: "m" (FpDest));
682 finishVfp(fpscr, state, fpscr.fz);
683 Fpscr = fpscr;
684 '''
685 vcvtUIntFpSIop = InstObjParams("vcvt", "VcvtUIntFpS", "FpRegRegOp",
686 { "code": vcvtUIntFpSCode,
687 "predicate_test": predicateTest }, [])
688 header_output += FpRegRegOpDeclare.subst(vcvtUIntFpSIop);
689 decoder_output += FpRegRegOpConstructor.subst(vcvtUIntFpSIop);
690 exec_output += PredOpExecute.subst(vcvtUIntFpSIop);
691
679 FPSCR fpscr = Fpscr;
680 VfpSavedState state = prepFpState(fpscr.rMode);
681 __asm__ __volatile__("" : "=m" (FpOp1.uw) : "m" (FpOp1.uw));
682 FpDest = FpOp1.uw;
683 __asm__ __volatile__("" :: "m" (FpDest));
684 finishVfp(fpscr, state, fpscr.fz);
685 Fpscr = fpscr;
686 '''
687 vcvtUIntFpSIop = InstObjParams("vcvt", "VcvtUIntFpS", "FpRegRegOp",
688 { "code": vcvtUIntFpSCode,
689 "predicate_test": predicateTest }, [])
690 header_output += FpRegRegOpDeclare.subst(vcvtUIntFpSIop);
691 decoder_output += FpRegRegOpConstructor.subst(vcvtUIntFpSIop);
692 exec_output += PredOpExecute.subst(vcvtUIntFpSIop);
693
692 vcvtUIntFpDCode = '''
694 vcvtUIntFpDCode = vfpEnabledCheckCode + '''
693 FPSCR fpscr = Fpscr;
694 VfpSavedState state = prepFpState(fpscr.rMode);
695 __asm__ __volatile__("" : "=m" (FpOp1P0.uw) : "m" (FpOp1P0.uw));
696 double cDest = (uint64_t)FpOp1P0.uw;
697 __asm__ __volatile__("" :: "m" (cDest));
698 finishVfp(fpscr, state, fpscr.fz);
699 Fpscr = fpscr;
700 FpDestP0.uw = dblLow(cDest);
701 FpDestP1.uw = dblHi(cDest);
702 '''
703 vcvtUIntFpDIop = InstObjParams("vcvt", "VcvtUIntFpD", "FpRegRegOp",
704 { "code": vcvtUIntFpDCode,
705 "predicate_test": predicateTest }, [])
706 header_output += FpRegRegOpDeclare.subst(vcvtUIntFpDIop);
707 decoder_output += FpRegRegOpConstructor.subst(vcvtUIntFpDIop);
708 exec_output += PredOpExecute.subst(vcvtUIntFpDIop);
709
695 FPSCR fpscr = Fpscr;
696 VfpSavedState state = prepFpState(fpscr.rMode);
697 __asm__ __volatile__("" : "=m" (FpOp1P0.uw) : "m" (FpOp1P0.uw));
698 double cDest = (uint64_t)FpOp1P0.uw;
699 __asm__ __volatile__("" :: "m" (cDest));
700 finishVfp(fpscr, state, fpscr.fz);
701 Fpscr = fpscr;
702 FpDestP0.uw = dblLow(cDest);
703 FpDestP1.uw = dblHi(cDest);
704 '''
705 vcvtUIntFpDIop = InstObjParams("vcvt", "VcvtUIntFpD", "FpRegRegOp",
706 { "code": vcvtUIntFpDCode,
707 "predicate_test": predicateTest }, [])
708 header_output += FpRegRegOpDeclare.subst(vcvtUIntFpDIop);
709 decoder_output += FpRegRegOpConstructor.subst(vcvtUIntFpDIop);
710 exec_output += PredOpExecute.subst(vcvtUIntFpDIop);
711
710 vcvtSIntFpSCode = '''
712 vcvtSIntFpSCode = vfpEnabledCheckCode + '''
711 FPSCR fpscr = Fpscr;
712 VfpSavedState state = prepFpState(fpscr.rMode);
713 __asm__ __volatile__("" : "=m" (FpOp1.sw) : "m" (FpOp1.sw));
714 FpDest = FpOp1.sw;
715 __asm__ __volatile__("" :: "m" (FpDest));
716 finishVfp(fpscr, state, fpscr.fz);
717 Fpscr = fpscr;
718 '''
719 vcvtSIntFpSIop = InstObjParams("vcvt", "VcvtSIntFpS", "FpRegRegOp",
720 { "code": vcvtSIntFpSCode,
721 "predicate_test": predicateTest }, [])
722 header_output += FpRegRegOpDeclare.subst(vcvtSIntFpSIop);
723 decoder_output += FpRegRegOpConstructor.subst(vcvtSIntFpSIop);
724 exec_output += PredOpExecute.subst(vcvtSIntFpSIop);
725
713 FPSCR fpscr = Fpscr;
714 VfpSavedState state = prepFpState(fpscr.rMode);
715 __asm__ __volatile__("" : "=m" (FpOp1.sw) : "m" (FpOp1.sw));
716 FpDest = FpOp1.sw;
717 __asm__ __volatile__("" :: "m" (FpDest));
718 finishVfp(fpscr, state, fpscr.fz);
719 Fpscr = fpscr;
720 '''
721 vcvtSIntFpSIop = InstObjParams("vcvt", "VcvtSIntFpS", "FpRegRegOp",
722 { "code": vcvtSIntFpSCode,
723 "predicate_test": predicateTest }, [])
724 header_output += FpRegRegOpDeclare.subst(vcvtSIntFpSIop);
725 decoder_output += FpRegRegOpConstructor.subst(vcvtSIntFpSIop);
726 exec_output += PredOpExecute.subst(vcvtSIntFpSIop);
727
726 vcvtSIntFpDCode = '''
728 vcvtSIntFpDCode = vfpEnabledCheckCode + '''
727 FPSCR fpscr = Fpscr;
728 VfpSavedState state = prepFpState(fpscr.rMode);
729 __asm__ __volatile__("" : "=m" (FpOp1P0.sw) : "m" (FpOp1P0.sw));
730 double cDest = FpOp1P0.sw;
731 __asm__ __volatile__("" :: "m" (cDest));
732 finishVfp(fpscr, state, fpscr.fz);
733 Fpscr = fpscr;
734 FpDestP0.uw = dblLow(cDest);
735 FpDestP1.uw = dblHi(cDest);
736 '''
737 vcvtSIntFpDIop = InstObjParams("vcvt", "VcvtSIntFpD", "FpRegRegOp",
738 { "code": vcvtSIntFpDCode,
739 "predicate_test": predicateTest }, [])
740 header_output += FpRegRegOpDeclare.subst(vcvtSIntFpDIop);
741 decoder_output += FpRegRegOpConstructor.subst(vcvtSIntFpDIop);
742 exec_output += PredOpExecute.subst(vcvtSIntFpDIop);
743
729 FPSCR fpscr = Fpscr;
730 VfpSavedState state = prepFpState(fpscr.rMode);
731 __asm__ __volatile__("" : "=m" (FpOp1P0.sw) : "m" (FpOp1P0.sw));
732 double cDest = FpOp1P0.sw;
733 __asm__ __volatile__("" :: "m" (cDest));
734 finishVfp(fpscr, state, fpscr.fz);
735 Fpscr = fpscr;
736 FpDestP0.uw = dblLow(cDest);
737 FpDestP1.uw = dblHi(cDest);
738 '''
739 vcvtSIntFpDIop = InstObjParams("vcvt", "VcvtSIntFpD", "FpRegRegOp",
740 { "code": vcvtSIntFpDCode,
741 "predicate_test": predicateTest }, [])
742 header_output += FpRegRegOpDeclare.subst(vcvtSIntFpDIop);
743 decoder_output += FpRegRegOpConstructor.subst(vcvtSIntFpDIop);
744 exec_output += PredOpExecute.subst(vcvtSIntFpDIop);
745
744 vcvtFpUIntSRCode = '''
746 vcvtFpUIntSRCode = vfpEnabledCheckCode + '''
745 FPSCR fpscr = Fpscr;
746 VfpSavedState state = prepFpState(fpscr.rMode);
747 vfpFlushToZero(fpscr, FpOp1);
748 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
749 FpDest.uw = vfpFpSToFixed(FpOp1, false, false, 0, false);
750 __asm__ __volatile__("" :: "m" (FpDest.uw));
751 finishVfp(fpscr, state, fpscr.fz);
752 Fpscr = fpscr;
753 '''
754 vcvtFpUIntSRIop = InstObjParams("vcvt", "VcvtFpUIntSR", "FpRegRegOp",
755 { "code": vcvtFpUIntSRCode,
756 "predicate_test": predicateTest }, [])
757 header_output += FpRegRegOpDeclare.subst(vcvtFpUIntSRIop);
758 decoder_output += FpRegRegOpConstructor.subst(vcvtFpUIntSRIop);
759 exec_output += PredOpExecute.subst(vcvtFpUIntSRIop);
760
747 FPSCR fpscr = Fpscr;
748 VfpSavedState state = prepFpState(fpscr.rMode);
749 vfpFlushToZero(fpscr, FpOp1);
750 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
751 FpDest.uw = vfpFpSToFixed(FpOp1, false, false, 0, false);
752 __asm__ __volatile__("" :: "m" (FpDest.uw));
753 finishVfp(fpscr, state, fpscr.fz);
754 Fpscr = fpscr;
755 '''
756 vcvtFpUIntSRIop = InstObjParams("vcvt", "VcvtFpUIntSR", "FpRegRegOp",
757 { "code": vcvtFpUIntSRCode,
758 "predicate_test": predicateTest }, [])
759 header_output += FpRegRegOpDeclare.subst(vcvtFpUIntSRIop);
760 decoder_output += FpRegRegOpConstructor.subst(vcvtFpUIntSRIop);
761 exec_output += PredOpExecute.subst(vcvtFpUIntSRIop);
762
761 vcvtFpUIntDRCode = '''
763 vcvtFpUIntDRCode = vfpEnabledCheckCode + '''
762 FPSCR fpscr = Fpscr;
763 double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw);
764 vfpFlushToZero(fpscr, cOp1);
765 VfpSavedState state = prepFpState(fpscr.rMode);
766 __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1));
767 uint64_t result = vfpFpDToFixed(cOp1, false, false, 0, false);
768 __asm__ __volatile__("" :: "m" (result));
769 finishVfp(fpscr, state, fpscr.fz);
770 Fpscr = fpscr;
771 FpDestP0.uw = result;
772 '''
773 vcvtFpUIntDRIop = InstObjParams("vcvtr", "VcvtFpUIntDR", "FpRegRegOp",
774 { "code": vcvtFpUIntDRCode,
775 "predicate_test": predicateTest }, [])
776 header_output += FpRegRegOpDeclare.subst(vcvtFpUIntDRIop);
777 decoder_output += FpRegRegOpConstructor.subst(vcvtFpUIntDRIop);
778 exec_output += PredOpExecute.subst(vcvtFpUIntDRIop);
779
764 FPSCR fpscr = Fpscr;
765 double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw);
766 vfpFlushToZero(fpscr, cOp1);
767 VfpSavedState state = prepFpState(fpscr.rMode);
768 __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1));
769 uint64_t result = vfpFpDToFixed(cOp1, false, false, 0, false);
770 __asm__ __volatile__("" :: "m" (result));
771 finishVfp(fpscr, state, fpscr.fz);
772 Fpscr = fpscr;
773 FpDestP0.uw = result;
774 '''
775 vcvtFpUIntDRIop = InstObjParams("vcvtr", "VcvtFpUIntDR", "FpRegRegOp",
776 { "code": vcvtFpUIntDRCode,
777 "predicate_test": predicateTest }, [])
778 header_output += FpRegRegOpDeclare.subst(vcvtFpUIntDRIop);
779 decoder_output += FpRegRegOpConstructor.subst(vcvtFpUIntDRIop);
780 exec_output += PredOpExecute.subst(vcvtFpUIntDRIop);
781
780 vcvtFpSIntSRCode = '''
782 vcvtFpSIntSRCode = vfpEnabledCheckCode + '''
781 FPSCR fpscr = Fpscr;
782 VfpSavedState state = prepFpState(fpscr.rMode);
783 vfpFlushToZero(fpscr, FpOp1);
784 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
785 FpDest.sw = vfpFpSToFixed(FpOp1, true, false, 0, false);
786 __asm__ __volatile__("" :: "m" (FpDest.sw));
787 finishVfp(fpscr, state, fpscr.fz);
788 Fpscr = fpscr;
789 '''
790 vcvtFpSIntSRIop = InstObjParams("vcvtr", "VcvtFpSIntSR", "FpRegRegOp",
791 { "code": vcvtFpSIntSRCode,
792 "predicate_test": predicateTest }, [])
793 header_output += FpRegRegOpDeclare.subst(vcvtFpSIntSRIop);
794 decoder_output += FpRegRegOpConstructor.subst(vcvtFpSIntSRIop);
795 exec_output += PredOpExecute.subst(vcvtFpSIntSRIop);
796
783 FPSCR fpscr = Fpscr;
784 VfpSavedState state = prepFpState(fpscr.rMode);
785 vfpFlushToZero(fpscr, FpOp1);
786 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
787 FpDest.sw = vfpFpSToFixed(FpOp1, true, false, 0, false);
788 __asm__ __volatile__("" :: "m" (FpDest.sw));
789 finishVfp(fpscr, state, fpscr.fz);
790 Fpscr = fpscr;
791 '''
792 vcvtFpSIntSRIop = InstObjParams("vcvtr", "VcvtFpSIntSR", "FpRegRegOp",
793 { "code": vcvtFpSIntSRCode,
794 "predicate_test": predicateTest }, [])
795 header_output += FpRegRegOpDeclare.subst(vcvtFpSIntSRIop);
796 decoder_output += FpRegRegOpConstructor.subst(vcvtFpSIntSRIop);
797 exec_output += PredOpExecute.subst(vcvtFpSIntSRIop);
798
797 vcvtFpSIntDRCode = '''
799 vcvtFpSIntDRCode = vfpEnabledCheckCode + '''
798 FPSCR fpscr = Fpscr;
799 double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw);
800 vfpFlushToZero(fpscr, cOp1);
801 VfpSavedState state = prepFpState(fpscr.rMode);
802 __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1));
803 int64_t result = vfpFpDToFixed(cOp1, true, false, 0, false);
804 __asm__ __volatile__("" :: "m" (result));
805 finishVfp(fpscr, state, fpscr.fz);
806 Fpscr = fpscr;
807 FpDestP0.uw = result;
808 '''
809 vcvtFpSIntDRIop = InstObjParams("vcvtr", "VcvtFpSIntDR", "FpRegRegOp",
810 { "code": vcvtFpSIntDRCode,
811 "predicate_test": predicateTest }, [])
812 header_output += FpRegRegOpDeclare.subst(vcvtFpSIntDRIop);
813 decoder_output += FpRegRegOpConstructor.subst(vcvtFpSIntDRIop);
814 exec_output += PredOpExecute.subst(vcvtFpSIntDRIop);
815
800 FPSCR fpscr = Fpscr;
801 double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw);
802 vfpFlushToZero(fpscr, cOp1);
803 VfpSavedState state = prepFpState(fpscr.rMode);
804 __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1));
805 int64_t result = vfpFpDToFixed(cOp1, true, false, 0, false);
806 __asm__ __volatile__("" :: "m" (result));
807 finishVfp(fpscr, state, fpscr.fz);
808 Fpscr = fpscr;
809 FpDestP0.uw = result;
810 '''
811 vcvtFpSIntDRIop = InstObjParams("vcvtr", "VcvtFpSIntDR", "FpRegRegOp",
812 { "code": vcvtFpSIntDRCode,
813 "predicate_test": predicateTest }, [])
814 header_output += FpRegRegOpDeclare.subst(vcvtFpSIntDRIop);
815 decoder_output += FpRegRegOpConstructor.subst(vcvtFpSIntDRIop);
816 exec_output += PredOpExecute.subst(vcvtFpSIntDRIop);
817
816 vcvtFpUIntSCode = '''
818 vcvtFpUIntSCode = vfpEnabledCheckCode + '''
817 FPSCR fpscr = Fpscr;
818 vfpFlushToZero(fpscr, FpOp1);
819 VfpSavedState state = prepFpState(fpscr.rMode);
820 fesetround(FeRoundZero);
821 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
822 FpDest.uw = vfpFpSToFixed(FpOp1, false, false, 0);
823 __asm__ __volatile__("" :: "m" (FpDest.uw));
824 finishVfp(fpscr, state, fpscr.fz);
825 Fpscr = fpscr;
826 '''
827 vcvtFpUIntSIop = InstObjParams("vcvt", "VcvtFpUIntS", "FpRegRegOp",
828 { "code": vcvtFpUIntSCode,
829 "predicate_test": predicateTest }, [])
830 header_output += FpRegRegOpDeclare.subst(vcvtFpUIntSIop);
831 decoder_output += FpRegRegOpConstructor.subst(vcvtFpUIntSIop);
832 exec_output += PredOpExecute.subst(vcvtFpUIntSIop);
833
819 FPSCR fpscr = Fpscr;
820 vfpFlushToZero(fpscr, FpOp1);
821 VfpSavedState state = prepFpState(fpscr.rMode);
822 fesetround(FeRoundZero);
823 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
824 FpDest.uw = vfpFpSToFixed(FpOp1, false, false, 0);
825 __asm__ __volatile__("" :: "m" (FpDest.uw));
826 finishVfp(fpscr, state, fpscr.fz);
827 Fpscr = fpscr;
828 '''
829 vcvtFpUIntSIop = InstObjParams("vcvt", "VcvtFpUIntS", "FpRegRegOp",
830 { "code": vcvtFpUIntSCode,
831 "predicate_test": predicateTest }, [])
832 header_output += FpRegRegOpDeclare.subst(vcvtFpUIntSIop);
833 decoder_output += FpRegRegOpConstructor.subst(vcvtFpUIntSIop);
834 exec_output += PredOpExecute.subst(vcvtFpUIntSIop);
835
834 vcvtFpUIntDCode = '''
836 vcvtFpUIntDCode = vfpEnabledCheckCode + '''
835 FPSCR fpscr = Fpscr;
836 double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw);
837 vfpFlushToZero(fpscr, cOp1);
838 VfpSavedState state = prepFpState(fpscr.rMode);
839 fesetround(FeRoundZero);
840 __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1));
841 uint64_t result = vfpFpDToFixed(cOp1, false, false, 0);
842 __asm__ __volatile__("" :: "m" (result));
843 finishVfp(fpscr, state, fpscr.fz);
844 Fpscr = fpscr;
845 FpDestP0.uw = result;
846 '''
847 vcvtFpUIntDIop = InstObjParams("vcvt", "VcvtFpUIntD", "FpRegRegOp",
848 { "code": vcvtFpUIntDCode,
849 "predicate_test": predicateTest }, [])
850 header_output += FpRegRegOpDeclare.subst(vcvtFpUIntDIop);
851 decoder_output += FpRegRegOpConstructor.subst(vcvtFpUIntDIop);
852 exec_output += PredOpExecute.subst(vcvtFpUIntDIop);
853
837 FPSCR fpscr = Fpscr;
838 double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw);
839 vfpFlushToZero(fpscr, cOp1);
840 VfpSavedState state = prepFpState(fpscr.rMode);
841 fesetround(FeRoundZero);
842 __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1));
843 uint64_t result = vfpFpDToFixed(cOp1, false, false, 0);
844 __asm__ __volatile__("" :: "m" (result));
845 finishVfp(fpscr, state, fpscr.fz);
846 Fpscr = fpscr;
847 FpDestP0.uw = result;
848 '''
849 vcvtFpUIntDIop = InstObjParams("vcvt", "VcvtFpUIntD", "FpRegRegOp",
850 { "code": vcvtFpUIntDCode,
851 "predicate_test": predicateTest }, [])
852 header_output += FpRegRegOpDeclare.subst(vcvtFpUIntDIop);
853 decoder_output += FpRegRegOpConstructor.subst(vcvtFpUIntDIop);
854 exec_output += PredOpExecute.subst(vcvtFpUIntDIop);
855
854 vcvtFpSIntSCode = '''
856 vcvtFpSIntSCode = vfpEnabledCheckCode + '''
855 FPSCR fpscr = Fpscr;
856 vfpFlushToZero(fpscr, FpOp1);
857 VfpSavedState state = prepFpState(fpscr.rMode);
858 fesetround(FeRoundZero);
859 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
860 FpDest.sw = vfpFpSToFixed(FpOp1, true, false, 0);
861 __asm__ __volatile__("" :: "m" (FpDest.sw));
862 finishVfp(fpscr, state, fpscr.fz);
863 Fpscr = fpscr;
864 '''
865 vcvtFpSIntSIop = InstObjParams("vcvt", "VcvtFpSIntS", "FpRegRegOp",
866 { "code": vcvtFpSIntSCode,
867 "predicate_test": predicateTest }, [])
868 header_output += FpRegRegOpDeclare.subst(vcvtFpSIntSIop);
869 decoder_output += FpRegRegOpConstructor.subst(vcvtFpSIntSIop);
870 exec_output += PredOpExecute.subst(vcvtFpSIntSIop);
871
857 FPSCR fpscr = Fpscr;
858 vfpFlushToZero(fpscr, FpOp1);
859 VfpSavedState state = prepFpState(fpscr.rMode);
860 fesetround(FeRoundZero);
861 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
862 FpDest.sw = vfpFpSToFixed(FpOp1, true, false, 0);
863 __asm__ __volatile__("" :: "m" (FpDest.sw));
864 finishVfp(fpscr, state, fpscr.fz);
865 Fpscr = fpscr;
866 '''
867 vcvtFpSIntSIop = InstObjParams("vcvt", "VcvtFpSIntS", "FpRegRegOp",
868 { "code": vcvtFpSIntSCode,
869 "predicate_test": predicateTest }, [])
870 header_output += FpRegRegOpDeclare.subst(vcvtFpSIntSIop);
871 decoder_output += FpRegRegOpConstructor.subst(vcvtFpSIntSIop);
872 exec_output += PredOpExecute.subst(vcvtFpSIntSIop);
873
872 vcvtFpSIntDCode = '''
874 vcvtFpSIntDCode = vfpEnabledCheckCode + '''
873 FPSCR fpscr = Fpscr;
874 double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw);
875 vfpFlushToZero(fpscr, cOp1);
876 VfpSavedState state = prepFpState(fpscr.rMode);
877 fesetround(FeRoundZero);
878 __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1));
879 int64_t result = vfpFpDToFixed(cOp1, true, false, 0);
880 __asm__ __volatile__("" :: "m" (result));
881 finishVfp(fpscr, state, fpscr.fz);
882 Fpscr = fpscr;
883 FpDestP0.uw = result;
884 '''
885 vcvtFpSIntDIop = InstObjParams("vcvt", "VcvtFpSIntD", "FpRegRegOp",
886 { "code": vcvtFpSIntDCode,
887 "predicate_test": predicateTest }, [])
888 header_output += FpRegRegOpDeclare.subst(vcvtFpSIntDIop);
889 decoder_output += FpRegRegOpConstructor.subst(vcvtFpSIntDIop);
890 exec_output += PredOpExecute.subst(vcvtFpSIntDIop);
891
875 FPSCR fpscr = Fpscr;
876 double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw);
877 vfpFlushToZero(fpscr, cOp1);
878 VfpSavedState state = prepFpState(fpscr.rMode);
879 fesetround(FeRoundZero);
880 __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1));
881 int64_t result = vfpFpDToFixed(cOp1, true, false, 0);
882 __asm__ __volatile__("" :: "m" (result));
883 finishVfp(fpscr, state, fpscr.fz);
884 Fpscr = fpscr;
885 FpDestP0.uw = result;
886 '''
887 vcvtFpSIntDIop = InstObjParams("vcvt", "VcvtFpSIntD", "FpRegRegOp",
888 { "code": vcvtFpSIntDCode,
889 "predicate_test": predicateTest }, [])
890 header_output += FpRegRegOpDeclare.subst(vcvtFpSIntDIop);
891 decoder_output += FpRegRegOpConstructor.subst(vcvtFpSIntDIop);
892 exec_output += PredOpExecute.subst(vcvtFpSIntDIop);
893
892 vcvtFpSFpDCode = '''
894 vcvtFpSFpDCode = vfpEnabledCheckCode + '''
893 FPSCR fpscr = Fpscr;
894 vfpFlushToZero(fpscr, FpOp1);
895 VfpSavedState state = prepFpState(fpscr.rMode);
896 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
897 double cDest = fixFpSFpDDest(Fpscr, FpOp1);
898 __asm__ __volatile__("" :: "m" (cDest));
899 finishVfp(fpscr, state, fpscr.fz);
900 Fpscr = fpscr;
901 FpDestP0.uw = dblLow(cDest);
902 FpDestP1.uw = dblHi(cDest);
903 '''
904 vcvtFpSFpDIop = InstObjParams("vcvt", "VcvtFpSFpD", "FpRegRegOp",
905 { "code": vcvtFpSFpDCode,
906 "predicate_test": predicateTest }, [])
907 header_output += FpRegRegOpDeclare.subst(vcvtFpSFpDIop);
908 decoder_output += FpRegRegOpConstructor.subst(vcvtFpSFpDIop);
909 exec_output += PredOpExecute.subst(vcvtFpSFpDIop);
910
895 FPSCR fpscr = Fpscr;
896 vfpFlushToZero(fpscr, FpOp1);
897 VfpSavedState state = prepFpState(fpscr.rMode);
898 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
899 double cDest = fixFpSFpDDest(Fpscr, FpOp1);
900 __asm__ __volatile__("" :: "m" (cDest));
901 finishVfp(fpscr, state, fpscr.fz);
902 Fpscr = fpscr;
903 FpDestP0.uw = dblLow(cDest);
904 FpDestP1.uw = dblHi(cDest);
905 '''
906 vcvtFpSFpDIop = InstObjParams("vcvt", "VcvtFpSFpD", "FpRegRegOp",
907 { "code": vcvtFpSFpDCode,
908 "predicate_test": predicateTest }, [])
909 header_output += FpRegRegOpDeclare.subst(vcvtFpSFpDIop);
910 decoder_output += FpRegRegOpConstructor.subst(vcvtFpSFpDIop);
911 exec_output += PredOpExecute.subst(vcvtFpSFpDIop);
912
911 vcvtFpDFpSCode = '''
913 vcvtFpDFpSCode = vfpEnabledCheckCode + '''
912 FPSCR fpscr = Fpscr;
913 double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw);
914 vfpFlushToZero(fpscr, cOp1);
915 VfpSavedState state = prepFpState(fpscr.rMode);
916 __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1));
917 FpDest = fixFpDFpSDest(Fpscr, cOp1);
918 __asm__ __volatile__("" :: "m" (FpDest));
919 finishVfp(fpscr, state, fpscr.fz);
920 Fpscr = fpscr;
921 '''
922 vcvtFpDFpSIop = InstObjParams("vcvt", "VcvtFpDFpS", "FpRegRegOp",
923 { "code": vcvtFpDFpSCode,
924 "predicate_test": predicateTest }, [])
925 header_output += FpRegRegOpDeclare.subst(vcvtFpDFpSIop);
926 decoder_output += FpRegRegOpConstructor.subst(vcvtFpDFpSIop);
927 exec_output += PredOpExecute.subst(vcvtFpDFpSIop);
928
914 FPSCR fpscr = Fpscr;
915 double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw);
916 vfpFlushToZero(fpscr, cOp1);
917 VfpSavedState state = prepFpState(fpscr.rMode);
918 __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1));
919 FpDest = fixFpDFpSDest(Fpscr, cOp1);
920 __asm__ __volatile__("" :: "m" (FpDest));
921 finishVfp(fpscr, state, fpscr.fz);
922 Fpscr = fpscr;
923 '''
924 vcvtFpDFpSIop = InstObjParams("vcvt", "VcvtFpDFpS", "FpRegRegOp",
925 { "code": vcvtFpDFpSCode,
926 "predicate_test": predicateTest }, [])
927 header_output += FpRegRegOpDeclare.subst(vcvtFpDFpSIop);
928 decoder_output += FpRegRegOpConstructor.subst(vcvtFpDFpSIop);
929 exec_output += PredOpExecute.subst(vcvtFpDFpSIop);
930
929 vcvtFpHTFpSCode = '''
931 vcvtFpHTFpSCode = vfpEnabledCheckCode + '''
930 FPSCR fpscr = Fpscr;
931 vfpFlushToZero(fpscr, FpOp1);
932 VfpSavedState state = prepFpState(fpscr.rMode);
933 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
934 FpDest = vcvtFpHFpS(fpscr, fpscr.dn, fpscr.ahp,
935 bits(fpToBits(FpOp1), 31, 16));
936 __asm__ __volatile__("" :: "m" (FpDest));
937 finishVfp(fpscr, state, fpscr.fz);
938 Fpscr = fpscr;
939 '''
940 vcvtFpHTFpSIop = InstObjParams("vcvtt", "VcvtFpHTFpS", "FpRegRegOp",
941 { "code": vcvtFpHTFpSCode,
942 "predicate_test": predicateTest }, [])
943 header_output += FpRegRegOpDeclare.subst(vcvtFpHTFpSIop);
944 decoder_output += FpRegRegOpConstructor.subst(vcvtFpHTFpSIop);
945 exec_output += PredOpExecute.subst(vcvtFpHTFpSIop);
946
932 FPSCR fpscr = Fpscr;
933 vfpFlushToZero(fpscr, FpOp1);
934 VfpSavedState state = prepFpState(fpscr.rMode);
935 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
936 FpDest = vcvtFpHFpS(fpscr, fpscr.dn, fpscr.ahp,
937 bits(fpToBits(FpOp1), 31, 16));
938 __asm__ __volatile__("" :: "m" (FpDest));
939 finishVfp(fpscr, state, fpscr.fz);
940 Fpscr = fpscr;
941 '''
942 vcvtFpHTFpSIop = InstObjParams("vcvtt", "VcvtFpHTFpS", "FpRegRegOp",
943 { "code": vcvtFpHTFpSCode,
944 "predicate_test": predicateTest }, [])
945 header_output += FpRegRegOpDeclare.subst(vcvtFpHTFpSIop);
946 decoder_output += FpRegRegOpConstructor.subst(vcvtFpHTFpSIop);
947 exec_output += PredOpExecute.subst(vcvtFpHTFpSIop);
948
947 vcvtFpHBFpSCode = '''
949 vcvtFpHBFpSCode = vfpEnabledCheckCode + '''
948 FPSCR fpscr = Fpscr;
949 VfpSavedState state = prepFpState(fpscr.rMode);
950 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
951 FpDest = vcvtFpHFpS(fpscr, fpscr.dn, fpscr.ahp,
952 bits(fpToBits(FpOp1), 15, 0));
953 __asm__ __volatile__("" :: "m" (FpDest));
954 finishVfp(fpscr, state, fpscr.fz);
955 Fpscr = fpscr;
956 '''
957 vcvtFpHBFpSIop = InstObjParams("vcvtb", "VcvtFpHBFpS", "FpRegRegOp",
958 { "code": vcvtFpHBFpSCode,
959 "predicate_test": predicateTest }, [])
960 header_output += FpRegRegOpDeclare.subst(vcvtFpHBFpSIop);
961 decoder_output += FpRegRegOpConstructor.subst(vcvtFpHBFpSIop);
962 exec_output += PredOpExecute.subst(vcvtFpHBFpSIop);
963
950 FPSCR fpscr = Fpscr;
951 VfpSavedState state = prepFpState(fpscr.rMode);
952 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
953 FpDest = vcvtFpHFpS(fpscr, fpscr.dn, fpscr.ahp,
954 bits(fpToBits(FpOp1), 15, 0));
955 __asm__ __volatile__("" :: "m" (FpDest));
956 finishVfp(fpscr, state, fpscr.fz);
957 Fpscr = fpscr;
958 '''
959 vcvtFpHBFpSIop = InstObjParams("vcvtb", "VcvtFpHBFpS", "FpRegRegOp",
960 { "code": vcvtFpHBFpSCode,
961 "predicate_test": predicateTest }, [])
962 header_output += FpRegRegOpDeclare.subst(vcvtFpHBFpSIop);
963 decoder_output += FpRegRegOpConstructor.subst(vcvtFpHBFpSIop);
964 exec_output += PredOpExecute.subst(vcvtFpHBFpSIop);
965
964 vcvtFpSFpHTCode = '''
966 vcvtFpSFpHTCode = vfpEnabledCheckCode + '''
965 FPSCR fpscr = Fpscr;
966 vfpFlushToZero(fpscr, FpOp1);
967 VfpSavedState state = prepFpState(fpscr.rMode);
968 __asm__ __volatile__("" : "=m" (FpOp1), "=m" (FpDest.uw)
969 : "m" (FpOp1), "m" (FpDest.uw));
970 FpDest.uw = insertBits(FpDest.uw, 31, 16,,
971 vcvtFpSFpH(fpscr, fpscr.fz, fpscr.dn,
972 fpscr.rMode, fpscr.ahp, FpOp1));
973 __asm__ __volatile__("" :: "m" (FpDest.uw));
974 finishVfp(fpscr, state, fpscr.fz);
975 Fpscr = fpscr;
976 '''
977 vcvtFpSFpHTIop = InstObjParams("vcvtt", "VcvtFpSFpHT", "FpRegRegOp",
978 { "code": vcvtFpHTFpSCode,
979 "predicate_test": predicateTest }, [])
980 header_output += FpRegRegOpDeclare.subst(vcvtFpSFpHTIop);
981 decoder_output += FpRegRegOpConstructor.subst(vcvtFpSFpHTIop);
982 exec_output += PredOpExecute.subst(vcvtFpSFpHTIop);
983
967 FPSCR fpscr = Fpscr;
968 vfpFlushToZero(fpscr, FpOp1);
969 VfpSavedState state = prepFpState(fpscr.rMode);
970 __asm__ __volatile__("" : "=m" (FpOp1), "=m" (FpDest.uw)
971 : "m" (FpOp1), "m" (FpDest.uw));
972 FpDest.uw = insertBits(FpDest.uw, 31, 16,,
973 vcvtFpSFpH(fpscr, fpscr.fz, fpscr.dn,
974 fpscr.rMode, fpscr.ahp, FpOp1));
975 __asm__ __volatile__("" :: "m" (FpDest.uw));
976 finishVfp(fpscr, state, fpscr.fz);
977 Fpscr = fpscr;
978 '''
979 vcvtFpSFpHTIop = InstObjParams("vcvtt", "VcvtFpSFpHT", "FpRegRegOp",
980 { "code": vcvtFpHTFpSCode,
981 "predicate_test": predicateTest }, [])
982 header_output += FpRegRegOpDeclare.subst(vcvtFpSFpHTIop);
983 decoder_output += FpRegRegOpConstructor.subst(vcvtFpSFpHTIop);
984 exec_output += PredOpExecute.subst(vcvtFpSFpHTIop);
985
984 vcvtFpSFpHBCode = '''
986 vcvtFpSFpHBCode = vfpEnabledCheckCode + '''
985 FPSCR fpscr = Fpscr;
986 vfpFlushToZero(fpscr, FpOp1);
987 VfpSavedState state = prepFpState(fpscr.rMode);
988 __asm__ __volatile__("" : "=m" (FpOp1), "=m" (FpDest.uw)
989 : "m" (FpOp1), "m" (FpDest.uw));
990 FpDest.uw = insertBits(FpDest.uw, 15, 0,
991 vcvtFpSFpH(fpscr, fpscr.fz, fpscr.dn,
992 fpscr.rMode, fpscr.ahp, FpOp1));
993 __asm__ __volatile__("" :: "m" (FpDest.uw));
994 finishVfp(fpscr, state, fpscr.fz);
995 Fpscr = fpscr;
996 '''
997 vcvtFpSFpHBIop = InstObjParams("vcvtb", "VcvtFpSFpHB", "FpRegRegOp",
998 { "code": vcvtFpSFpHBCode,
999 "predicate_test": predicateTest }, [])
1000 header_output += FpRegRegOpDeclare.subst(vcvtFpSFpHBIop);
1001 decoder_output += FpRegRegOpConstructor.subst(vcvtFpSFpHBIop);
1002 exec_output += PredOpExecute.subst(vcvtFpSFpHBIop);
1003
987 FPSCR fpscr = Fpscr;
988 vfpFlushToZero(fpscr, FpOp1);
989 VfpSavedState state = prepFpState(fpscr.rMode);
990 __asm__ __volatile__("" : "=m" (FpOp1), "=m" (FpDest.uw)
991 : "m" (FpOp1), "m" (FpDest.uw));
992 FpDest.uw = insertBits(FpDest.uw, 15, 0,
993 vcvtFpSFpH(fpscr, fpscr.fz, fpscr.dn,
994 fpscr.rMode, fpscr.ahp, FpOp1));
995 __asm__ __volatile__("" :: "m" (FpDest.uw));
996 finishVfp(fpscr, state, fpscr.fz);
997 Fpscr = fpscr;
998 '''
999 vcvtFpSFpHBIop = InstObjParams("vcvtb", "VcvtFpSFpHB", "FpRegRegOp",
1000 { "code": vcvtFpSFpHBCode,
1001 "predicate_test": predicateTest }, [])
1002 header_output += FpRegRegOpDeclare.subst(vcvtFpSFpHBIop);
1003 decoder_output += FpRegRegOpConstructor.subst(vcvtFpSFpHBIop);
1004 exec_output += PredOpExecute.subst(vcvtFpSFpHBIop);
1005
1004 vcmpSCode = '''
1006 vcmpSCode = vfpEnabledCheckCode + '''
1005 FPSCR fpscr = Fpscr;
1006 vfpFlushToZero(fpscr, FpDest, FpOp1);
1007 if (FpDest == FpOp1) {
1008 fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0;
1009 } else if (FpDest < FpOp1) {
1010 fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0;
1011 } else if (FpDest > FpOp1) {
1012 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0;

--- 11 unchanged lines hidden (view full) ---

1024 '''
1025 vcmpSIop = InstObjParams("vcmps", "VcmpS", "FpRegRegOp",
1026 { "code": vcmpSCode,
1027 "predicate_test": predicateTest }, [])
1028 header_output += FpRegRegOpDeclare.subst(vcmpSIop);
1029 decoder_output += FpRegRegOpConstructor.subst(vcmpSIop);
1030 exec_output += PredOpExecute.subst(vcmpSIop);
1031
1007 FPSCR fpscr = Fpscr;
1008 vfpFlushToZero(fpscr, FpDest, FpOp1);
1009 if (FpDest == FpOp1) {
1010 fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0;
1011 } else if (FpDest < FpOp1) {
1012 fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0;
1013 } else if (FpDest > FpOp1) {
1014 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0;

--- 11 unchanged lines hidden (view full) ---

1026 '''
1027 vcmpSIop = InstObjParams("vcmps", "VcmpS", "FpRegRegOp",
1028 { "code": vcmpSCode,
1029 "predicate_test": predicateTest }, [])
1030 header_output += FpRegRegOpDeclare.subst(vcmpSIop);
1031 decoder_output += FpRegRegOpConstructor.subst(vcmpSIop);
1032 exec_output += PredOpExecute.subst(vcmpSIop);
1033
1032 vcmpDCode = '''
1034 vcmpDCode = vfpEnabledCheckCode + '''
1033 double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw);
1034 double cDest = dbl(FpDestP0.uw, FpDestP1.uw);
1035 FPSCR fpscr = Fpscr;
1036 vfpFlushToZero(fpscr, cDest, cOp1);
1037 if (cDest == cOp1) {
1038 fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0;
1039 } else if (cDest < cOp1) {
1040 fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0;

--- 13 unchanged lines hidden (view full) ---

1054 '''
1055 vcmpDIop = InstObjParams("vcmpd", "VcmpD", "FpRegRegOp",
1056 { "code": vcmpDCode,
1057 "predicate_test": predicateTest }, [])
1058 header_output += FpRegRegOpDeclare.subst(vcmpDIop);
1059 decoder_output += FpRegRegOpConstructor.subst(vcmpDIop);
1060 exec_output += PredOpExecute.subst(vcmpDIop);
1061
1035 double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw);
1036 double cDest = dbl(FpDestP0.uw, FpDestP1.uw);
1037 FPSCR fpscr = Fpscr;
1038 vfpFlushToZero(fpscr, cDest, cOp1);
1039 if (cDest == cOp1) {
1040 fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0;
1041 } else if (cDest < cOp1) {
1042 fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0;

--- 13 unchanged lines hidden (view full) ---

1056 '''
1057 vcmpDIop = InstObjParams("vcmpd", "VcmpD", "FpRegRegOp",
1058 { "code": vcmpDCode,
1059 "predicate_test": predicateTest }, [])
1060 header_output += FpRegRegOpDeclare.subst(vcmpDIop);
1061 decoder_output += FpRegRegOpConstructor.subst(vcmpDIop);
1062 exec_output += PredOpExecute.subst(vcmpDIop);
1063
1062 vcmpZeroSCode = '''
1064 vcmpZeroSCode = vfpEnabledCheckCode + '''
1063 FPSCR fpscr = Fpscr;
1064 vfpFlushToZero(fpscr, FpDest);
1065 // This only handles imm == 0 for now.
1066 assert(imm == 0);
1067 if (FpDest == imm) {
1068 fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0;
1069 } else if (FpDest < imm) {
1070 fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0;

--- 11 unchanged lines hidden (view full) ---

1082 '''
1083 vcmpZeroSIop = InstObjParams("vcmpZeros", "VcmpZeroS", "FpRegImmOp",
1084 { "code": vcmpZeroSCode,
1085 "predicate_test": predicateTest }, [])
1086 header_output += FpRegImmOpDeclare.subst(vcmpZeroSIop);
1087 decoder_output += FpRegImmOpConstructor.subst(vcmpZeroSIop);
1088 exec_output += PredOpExecute.subst(vcmpZeroSIop);
1089
1065 FPSCR fpscr = Fpscr;
1066 vfpFlushToZero(fpscr, FpDest);
1067 // This only handles imm == 0 for now.
1068 assert(imm == 0);
1069 if (FpDest == imm) {
1070 fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0;
1071 } else if (FpDest < imm) {
1072 fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0;

--- 11 unchanged lines hidden (view full) ---

1084 '''
1085 vcmpZeroSIop = InstObjParams("vcmpZeros", "VcmpZeroS", "FpRegImmOp",
1086 { "code": vcmpZeroSCode,
1087 "predicate_test": predicateTest }, [])
1088 header_output += FpRegImmOpDeclare.subst(vcmpZeroSIop);
1089 decoder_output += FpRegImmOpConstructor.subst(vcmpZeroSIop);
1090 exec_output += PredOpExecute.subst(vcmpZeroSIop);
1091
1090 vcmpZeroDCode = '''
1092 vcmpZeroDCode = vfpEnabledCheckCode + '''
1091 // This only handles imm == 0 for now.
1092 assert(imm == 0);
1093 double cDest = dbl(FpDestP0.uw, FpDestP1.uw);
1094 FPSCR fpscr = Fpscr;
1095 vfpFlushToZero(fpscr, cDest);
1096 if (cDest == imm) {
1097 fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0;
1098 } else if (cDest < imm) {

--- 12 unchanged lines hidden (view full) ---

1111 '''
1112 vcmpZeroDIop = InstObjParams("vcmpZerod", "VcmpZeroD", "FpRegImmOp",
1113 { "code": vcmpZeroDCode,
1114 "predicate_test": predicateTest }, [])
1115 header_output += FpRegImmOpDeclare.subst(vcmpZeroDIop);
1116 decoder_output += FpRegImmOpConstructor.subst(vcmpZeroDIop);
1117 exec_output += PredOpExecute.subst(vcmpZeroDIop);
1118
1093 // This only handles imm == 0 for now.
1094 assert(imm == 0);
1095 double cDest = dbl(FpDestP0.uw, FpDestP1.uw);
1096 FPSCR fpscr = Fpscr;
1097 vfpFlushToZero(fpscr, cDest);
1098 if (cDest == imm) {
1099 fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0;
1100 } else if (cDest < imm) {

--- 12 unchanged lines hidden (view full) ---

1113 '''
1114 vcmpZeroDIop = InstObjParams("vcmpZerod", "VcmpZeroD", "FpRegImmOp",
1115 { "code": vcmpZeroDCode,
1116 "predicate_test": predicateTest }, [])
1117 header_output += FpRegImmOpDeclare.subst(vcmpZeroDIop);
1118 decoder_output += FpRegImmOpConstructor.subst(vcmpZeroDIop);
1119 exec_output += PredOpExecute.subst(vcmpZeroDIop);
1120
1119 vcmpeSCode = '''
1121 vcmpeSCode = vfpEnabledCheckCode + '''
1120 FPSCR fpscr = Fpscr;
1121 vfpFlushToZero(fpscr, FpDest, FpOp1);
1122 if (FpDest == FpOp1) {
1123 fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0;
1124 } else if (FpDest < FpOp1) {
1125 fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0;
1126 } else if (FpDest > FpOp1) {
1127 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0;

--- 5 unchanged lines hidden (view full) ---

1133 '''
1134 vcmpeSIop = InstObjParams("vcmpes", "VcmpeS", "FpRegRegOp",
1135 { "code": vcmpeSCode,
1136 "predicate_test": predicateTest }, [])
1137 header_output += FpRegRegOpDeclare.subst(vcmpeSIop);
1138 decoder_output += FpRegRegOpConstructor.subst(vcmpeSIop);
1139 exec_output += PredOpExecute.subst(vcmpeSIop);
1140
1122 FPSCR fpscr = Fpscr;
1123 vfpFlushToZero(fpscr, FpDest, FpOp1);
1124 if (FpDest == FpOp1) {
1125 fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0;
1126 } else if (FpDest < FpOp1) {
1127 fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0;
1128 } else if (FpDest > FpOp1) {
1129 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0;

--- 5 unchanged lines hidden (view full) ---

1135 '''
1136 vcmpeSIop = InstObjParams("vcmpes", "VcmpeS", "FpRegRegOp",
1137 { "code": vcmpeSCode,
1138 "predicate_test": predicateTest }, [])
1139 header_output += FpRegRegOpDeclare.subst(vcmpeSIop);
1140 decoder_output += FpRegRegOpConstructor.subst(vcmpeSIop);
1141 exec_output += PredOpExecute.subst(vcmpeSIop);
1142
1141 vcmpeDCode = '''
1143 vcmpeDCode = vfpEnabledCheckCode + '''
1142 double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw);
1143 double cDest = dbl(FpDestP0.uw, FpDestP1.uw);
1144 FPSCR fpscr = Fpscr;
1145 vfpFlushToZero(fpscr, cDest, cOp1);
1146 if (cDest == cOp1) {
1147 fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0;
1148 } else if (cDest < cOp1) {
1149 fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0;

--- 7 unchanged lines hidden (view full) ---

1157 '''
1158 vcmpeDIop = InstObjParams("vcmped", "VcmpeD", "FpRegRegOp",
1159 { "code": vcmpeDCode,
1160 "predicate_test": predicateTest }, [])
1161 header_output += FpRegRegOpDeclare.subst(vcmpeDIop);
1162 decoder_output += FpRegRegOpConstructor.subst(vcmpeDIop);
1163 exec_output += PredOpExecute.subst(vcmpeDIop);
1164
1144 double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw);
1145 double cDest = dbl(FpDestP0.uw, FpDestP1.uw);
1146 FPSCR fpscr = Fpscr;
1147 vfpFlushToZero(fpscr, cDest, cOp1);
1148 if (cDest == cOp1) {
1149 fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0;
1150 } else if (cDest < cOp1) {
1151 fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0;

--- 7 unchanged lines hidden (view full) ---

1159 '''
1160 vcmpeDIop = InstObjParams("vcmped", "VcmpeD", "FpRegRegOp",
1161 { "code": vcmpeDCode,
1162 "predicate_test": predicateTest }, [])
1163 header_output += FpRegRegOpDeclare.subst(vcmpeDIop);
1164 decoder_output += FpRegRegOpConstructor.subst(vcmpeDIop);
1165 exec_output += PredOpExecute.subst(vcmpeDIop);
1166
1165 vcmpeZeroSCode = '''
1167 vcmpeZeroSCode = vfpEnabledCheckCode + '''
1166 FPSCR fpscr = Fpscr;
1167 vfpFlushToZero(fpscr, FpDest);
1168 if (FpDest == imm) {
1169 fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0;
1170 } else if (FpDest < imm) {
1171 fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0;
1172 } else if (FpDest > imm) {
1173 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0;

--- 5 unchanged lines hidden (view full) ---

1179 '''
1180 vcmpeZeroSIop = InstObjParams("vcmpeZeros", "VcmpeZeroS", "FpRegImmOp",
1181 { "code": vcmpeZeroSCode,
1182 "predicate_test": predicateTest }, [])
1183 header_output += FpRegImmOpDeclare.subst(vcmpeZeroSIop);
1184 decoder_output += FpRegImmOpConstructor.subst(vcmpeZeroSIop);
1185 exec_output += PredOpExecute.subst(vcmpeZeroSIop);
1186
1168 FPSCR fpscr = Fpscr;
1169 vfpFlushToZero(fpscr, FpDest);
1170 if (FpDest == imm) {
1171 fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0;
1172 } else if (FpDest < imm) {
1173 fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0;
1174 } else if (FpDest > imm) {
1175 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0;

--- 5 unchanged lines hidden (view full) ---

1181 '''
1182 vcmpeZeroSIop = InstObjParams("vcmpeZeros", "VcmpeZeroS", "FpRegImmOp",
1183 { "code": vcmpeZeroSCode,
1184 "predicate_test": predicateTest }, [])
1185 header_output += FpRegImmOpDeclare.subst(vcmpeZeroSIop);
1186 decoder_output += FpRegImmOpConstructor.subst(vcmpeZeroSIop);
1187 exec_output += PredOpExecute.subst(vcmpeZeroSIop);
1188
1187 vcmpeZeroDCode = '''
1189 vcmpeZeroDCode = vfpEnabledCheckCode + '''
1188 double cDest = dbl(FpDestP0.uw, FpDestP1.uw);
1189 FPSCR fpscr = Fpscr;
1190 vfpFlushToZero(fpscr, cDest);
1191 if (cDest == imm) {
1192 fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0;
1193 } else if (cDest < imm) {
1194 fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0;
1195 } else if (cDest > imm) {

--- 13 unchanged lines hidden (view full) ---

1209}};
1210
1211let {{
1212
1213 header_output = ""
1214 decoder_output = ""
1215 exec_output = ""
1216
1190 double cDest = dbl(FpDestP0.uw, FpDestP1.uw);
1191 FPSCR fpscr = Fpscr;
1192 vfpFlushToZero(fpscr, cDest);
1193 if (cDest == imm) {
1194 fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0;
1195 } else if (cDest < imm) {
1196 fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0;
1197 } else if (cDest > imm) {

--- 13 unchanged lines hidden (view full) ---

1211}};
1212
1213let {{
1214
1215 header_output = ""
1216 decoder_output = ""
1217 exec_output = ""
1218
1217 vcvtFpSFixedSCode = '''
1219 vcvtFpSFixedSCode = vfpEnabledCheckCode + '''
1218 FPSCR fpscr = Fpscr;
1219 vfpFlushToZero(fpscr, FpOp1);
1220 VfpSavedState state = prepFpState(fpscr.rMode);
1221 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
1222 FpDest.sw = vfpFpSToFixed(FpOp1, true, false, imm);
1223 __asm__ __volatile__("" :: "m" (FpDest.sw));
1224 finishVfp(fpscr, state, fpscr.fz);
1225 Fpscr = fpscr;
1226 '''
1227 vcvtFpSFixedSIop = InstObjParams("vcvt", "VcvtFpSFixedS", "FpRegRegImmOp",
1228 { "code": vcvtFpSFixedSCode,
1229 "predicate_test": predicateTest }, [])
1230 header_output += FpRegRegImmOpDeclare.subst(vcvtFpSFixedSIop);
1231 decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpSFixedSIop);
1232 exec_output += PredOpExecute.subst(vcvtFpSFixedSIop);
1233
1220 FPSCR fpscr = Fpscr;
1221 vfpFlushToZero(fpscr, FpOp1);
1222 VfpSavedState state = prepFpState(fpscr.rMode);
1223 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
1224 FpDest.sw = vfpFpSToFixed(FpOp1, true, false, imm);
1225 __asm__ __volatile__("" :: "m" (FpDest.sw));
1226 finishVfp(fpscr, state, fpscr.fz);
1227 Fpscr = fpscr;
1228 '''
1229 vcvtFpSFixedSIop = InstObjParams("vcvt", "VcvtFpSFixedS", "FpRegRegImmOp",
1230 { "code": vcvtFpSFixedSCode,
1231 "predicate_test": predicateTest }, [])
1232 header_output += FpRegRegImmOpDeclare.subst(vcvtFpSFixedSIop);
1233 decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpSFixedSIop);
1234 exec_output += PredOpExecute.subst(vcvtFpSFixedSIop);
1235
1234 vcvtFpSFixedDCode = '''
1236 vcvtFpSFixedDCode = vfpEnabledCheckCode + '''
1235 FPSCR fpscr = Fpscr;
1236 double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw);
1237 vfpFlushToZero(fpscr, cOp1);
1238 VfpSavedState state = prepFpState(fpscr.rMode);
1239 __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1));
1240 uint64_t mid = vfpFpDToFixed(cOp1, true, false, imm);
1241 __asm__ __volatile__("" :: "m" (mid));
1242 finishVfp(fpscr, state, fpscr.fz);
1243 Fpscr = fpscr;
1244 FpDestP0.uw = mid;
1245 FpDestP1.uw = mid >> 32;
1246 '''
1247 vcvtFpSFixedDIop = InstObjParams("vcvt", "VcvtFpSFixedD", "FpRegRegImmOp",
1248 { "code": vcvtFpSFixedDCode,
1249 "predicate_test": predicateTest }, [])
1250 header_output += FpRegRegImmOpDeclare.subst(vcvtFpSFixedDIop);
1251 decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpSFixedDIop);
1252 exec_output += PredOpExecute.subst(vcvtFpSFixedDIop);
1253
1237 FPSCR fpscr = Fpscr;
1238 double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw);
1239 vfpFlushToZero(fpscr, cOp1);
1240 VfpSavedState state = prepFpState(fpscr.rMode);
1241 __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1));
1242 uint64_t mid = vfpFpDToFixed(cOp1, true, false, imm);
1243 __asm__ __volatile__("" :: "m" (mid));
1244 finishVfp(fpscr, state, fpscr.fz);
1245 Fpscr = fpscr;
1246 FpDestP0.uw = mid;
1247 FpDestP1.uw = mid >> 32;
1248 '''
1249 vcvtFpSFixedDIop = InstObjParams("vcvt", "VcvtFpSFixedD", "FpRegRegImmOp",
1250 { "code": vcvtFpSFixedDCode,
1251 "predicate_test": predicateTest }, [])
1252 header_output += FpRegRegImmOpDeclare.subst(vcvtFpSFixedDIop);
1253 decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpSFixedDIop);
1254 exec_output += PredOpExecute.subst(vcvtFpSFixedDIop);
1255
1254 vcvtFpUFixedSCode = '''
1256 vcvtFpUFixedSCode = vfpEnabledCheckCode + '''
1255 FPSCR fpscr = Fpscr;
1256 vfpFlushToZero(fpscr, FpOp1);
1257 VfpSavedState state = prepFpState(fpscr.rMode);
1258 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
1259 FpDest.uw = vfpFpSToFixed(FpOp1, false, false, imm);
1260 __asm__ __volatile__("" :: "m" (FpDest.uw));
1261 finishVfp(fpscr, state, fpscr.fz);
1262 Fpscr = fpscr;
1263 '''
1264 vcvtFpUFixedSIop = InstObjParams("vcvt", "VcvtFpUFixedS", "FpRegRegImmOp",
1265 { "code": vcvtFpUFixedSCode,
1266 "predicate_test": predicateTest }, [])
1267 header_output += FpRegRegImmOpDeclare.subst(vcvtFpUFixedSIop);
1268 decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpUFixedSIop);
1269 exec_output += PredOpExecute.subst(vcvtFpUFixedSIop);
1270
1257 FPSCR fpscr = Fpscr;
1258 vfpFlushToZero(fpscr, FpOp1);
1259 VfpSavedState state = prepFpState(fpscr.rMode);
1260 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
1261 FpDest.uw = vfpFpSToFixed(FpOp1, false, false, imm);
1262 __asm__ __volatile__("" :: "m" (FpDest.uw));
1263 finishVfp(fpscr, state, fpscr.fz);
1264 Fpscr = fpscr;
1265 '''
1266 vcvtFpUFixedSIop = InstObjParams("vcvt", "VcvtFpUFixedS", "FpRegRegImmOp",
1267 { "code": vcvtFpUFixedSCode,
1268 "predicate_test": predicateTest }, [])
1269 header_output += FpRegRegImmOpDeclare.subst(vcvtFpUFixedSIop);
1270 decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpUFixedSIop);
1271 exec_output += PredOpExecute.subst(vcvtFpUFixedSIop);
1272
1271 vcvtFpUFixedDCode = '''
1273 vcvtFpUFixedDCode = vfpEnabledCheckCode + '''
1272 FPSCR fpscr = Fpscr;
1273 double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw);
1274 vfpFlushToZero(fpscr, cOp1);
1275 VfpSavedState state = prepFpState(fpscr.rMode);
1276 __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1));
1277 uint64_t mid = vfpFpDToFixed(cOp1, false, false, imm);
1278 __asm__ __volatile__("" :: "m" (mid));
1279 finishVfp(fpscr, state, fpscr.fz);
1280 Fpscr = fpscr;
1281 FpDestP0.uw = mid;
1282 FpDestP1.uw = mid >> 32;
1283 '''
1284 vcvtFpUFixedDIop = InstObjParams("vcvt", "VcvtFpUFixedD", "FpRegRegImmOp",
1285 { "code": vcvtFpUFixedDCode,
1286 "predicate_test": predicateTest }, [])
1287 header_output += FpRegRegImmOpDeclare.subst(vcvtFpUFixedDIop);
1288 decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpUFixedDIop);
1289 exec_output += PredOpExecute.subst(vcvtFpUFixedDIop);
1290
1274 FPSCR fpscr = Fpscr;
1275 double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw);
1276 vfpFlushToZero(fpscr, cOp1);
1277 VfpSavedState state = prepFpState(fpscr.rMode);
1278 __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1));
1279 uint64_t mid = vfpFpDToFixed(cOp1, false, false, imm);
1280 __asm__ __volatile__("" :: "m" (mid));
1281 finishVfp(fpscr, state, fpscr.fz);
1282 Fpscr = fpscr;
1283 FpDestP0.uw = mid;
1284 FpDestP1.uw = mid >> 32;
1285 '''
1286 vcvtFpUFixedDIop = InstObjParams("vcvt", "VcvtFpUFixedD", "FpRegRegImmOp",
1287 { "code": vcvtFpUFixedDCode,
1288 "predicate_test": predicateTest }, [])
1289 header_output += FpRegRegImmOpDeclare.subst(vcvtFpUFixedDIop);
1290 decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpUFixedDIop);
1291 exec_output += PredOpExecute.subst(vcvtFpUFixedDIop);
1292
1291 vcvtSFixedFpSCode = '''
1293 vcvtSFixedFpSCode = vfpEnabledCheckCode + '''
1292 FPSCR fpscr = Fpscr;
1293 VfpSavedState state = prepFpState(fpscr.rMode);
1294 __asm__ __volatile__("" : "=m" (FpOp1.sw) : "m" (FpOp1.sw));
1295 FpDest = vfpSFixedToFpS(fpscr.fz, fpscr.dn, FpOp1.sw, false, imm);
1296 __asm__ __volatile__("" :: "m" (FpDest));
1297 finishVfp(fpscr, state, fpscr.fz);
1298 Fpscr = fpscr;
1299 '''
1300 vcvtSFixedFpSIop = InstObjParams("vcvt", "VcvtSFixedFpS", "FpRegRegImmOp",
1301 { "code": vcvtSFixedFpSCode,
1302 "predicate_test": predicateTest }, [])
1303 header_output += FpRegRegImmOpDeclare.subst(vcvtSFixedFpSIop);
1304 decoder_output += FpRegRegImmOpConstructor.subst(vcvtSFixedFpSIop);
1305 exec_output += PredOpExecute.subst(vcvtSFixedFpSIop);
1306
1294 FPSCR fpscr = Fpscr;
1295 VfpSavedState state = prepFpState(fpscr.rMode);
1296 __asm__ __volatile__("" : "=m" (FpOp1.sw) : "m" (FpOp1.sw));
1297 FpDest = vfpSFixedToFpS(fpscr.fz, fpscr.dn, FpOp1.sw, false, imm);
1298 __asm__ __volatile__("" :: "m" (FpDest));
1299 finishVfp(fpscr, state, fpscr.fz);
1300 Fpscr = fpscr;
1301 '''
1302 vcvtSFixedFpSIop = InstObjParams("vcvt", "VcvtSFixedFpS", "FpRegRegImmOp",
1303 { "code": vcvtSFixedFpSCode,
1304 "predicate_test": predicateTest }, [])
1305 header_output += FpRegRegImmOpDeclare.subst(vcvtSFixedFpSIop);
1306 decoder_output += FpRegRegImmOpConstructor.subst(vcvtSFixedFpSIop);
1307 exec_output += PredOpExecute.subst(vcvtSFixedFpSIop);
1308
1307 vcvtSFixedFpDCode = '''
1309 vcvtSFixedFpDCode = vfpEnabledCheckCode + '''
1308 FPSCR fpscr = Fpscr;
1309 uint64_t mid = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
1310 VfpSavedState state = prepFpState(fpscr.rMode);
1311 __asm__ __volatile__("" : "=m" (mid) : "m" (mid));
1312 double cDest = vfpSFixedToFpD(fpscr.fz, fpscr.dn, mid, false, imm);
1313 __asm__ __volatile__("" :: "m" (cDest));
1314 finishVfp(fpscr, state, fpscr.fz);
1315 Fpscr = fpscr;
1316 FpDestP0.uw = dblLow(cDest);
1317 FpDestP1.uw = dblHi(cDest);
1318 '''
1319 vcvtSFixedFpDIop = InstObjParams("vcvt", "VcvtSFixedFpD", "FpRegRegImmOp",
1320 { "code": vcvtSFixedFpDCode,
1321 "predicate_test": predicateTest }, [])
1322 header_output += FpRegRegImmOpDeclare.subst(vcvtSFixedFpDIop);
1323 decoder_output += FpRegRegImmOpConstructor.subst(vcvtSFixedFpDIop);
1324 exec_output += PredOpExecute.subst(vcvtSFixedFpDIop);
1325
1310 FPSCR fpscr = Fpscr;
1311 uint64_t mid = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
1312 VfpSavedState state = prepFpState(fpscr.rMode);
1313 __asm__ __volatile__("" : "=m" (mid) : "m" (mid));
1314 double cDest = vfpSFixedToFpD(fpscr.fz, fpscr.dn, mid, false, imm);
1315 __asm__ __volatile__("" :: "m" (cDest));
1316 finishVfp(fpscr, state, fpscr.fz);
1317 Fpscr = fpscr;
1318 FpDestP0.uw = dblLow(cDest);
1319 FpDestP1.uw = dblHi(cDest);
1320 '''
1321 vcvtSFixedFpDIop = InstObjParams("vcvt", "VcvtSFixedFpD", "FpRegRegImmOp",
1322 { "code": vcvtSFixedFpDCode,
1323 "predicate_test": predicateTest }, [])
1324 header_output += FpRegRegImmOpDeclare.subst(vcvtSFixedFpDIop);
1325 decoder_output += FpRegRegImmOpConstructor.subst(vcvtSFixedFpDIop);
1326 exec_output += PredOpExecute.subst(vcvtSFixedFpDIop);
1327
1326 vcvtUFixedFpSCode = '''
1328 vcvtUFixedFpSCode = vfpEnabledCheckCode + '''
1327 FPSCR fpscr = Fpscr;
1328 VfpSavedState state = prepFpState(fpscr.rMode);
1329 __asm__ __volatile__("" : "=m" (FpOp1.uw) : "m" (FpOp1.uw));
1330 FpDest = vfpUFixedToFpS(fpscr.fz, fpscr.dn, FpOp1.uw, false, imm);
1331 __asm__ __volatile__("" :: "m" (FpDest));
1332 finishVfp(fpscr, state, fpscr.fz);
1333 Fpscr = fpscr;
1334 '''
1335 vcvtUFixedFpSIop = InstObjParams("vcvt", "VcvtUFixedFpS", "FpRegRegImmOp",
1336 { "code": vcvtUFixedFpSCode,
1337 "predicate_test": predicateTest }, [])
1338 header_output += FpRegRegImmOpDeclare.subst(vcvtUFixedFpSIop);
1339 decoder_output += FpRegRegImmOpConstructor.subst(vcvtUFixedFpSIop);
1340 exec_output += PredOpExecute.subst(vcvtUFixedFpSIop);
1341
1329 FPSCR fpscr = Fpscr;
1330 VfpSavedState state = prepFpState(fpscr.rMode);
1331 __asm__ __volatile__("" : "=m" (FpOp1.uw) : "m" (FpOp1.uw));
1332 FpDest = vfpUFixedToFpS(fpscr.fz, fpscr.dn, FpOp1.uw, false, imm);
1333 __asm__ __volatile__("" :: "m" (FpDest));
1334 finishVfp(fpscr, state, fpscr.fz);
1335 Fpscr = fpscr;
1336 '''
1337 vcvtUFixedFpSIop = InstObjParams("vcvt", "VcvtUFixedFpS", "FpRegRegImmOp",
1338 { "code": vcvtUFixedFpSCode,
1339 "predicate_test": predicateTest }, [])
1340 header_output += FpRegRegImmOpDeclare.subst(vcvtUFixedFpSIop);
1341 decoder_output += FpRegRegImmOpConstructor.subst(vcvtUFixedFpSIop);
1342 exec_output += PredOpExecute.subst(vcvtUFixedFpSIop);
1343
1342 vcvtUFixedFpDCode = '''
1344 vcvtUFixedFpDCode = vfpEnabledCheckCode + '''
1343 FPSCR fpscr = Fpscr;
1344 uint64_t mid = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
1345 VfpSavedState state = prepFpState(fpscr.rMode);
1346 __asm__ __volatile__("" : "=m" (mid) : "m" (mid));
1347 double cDest = vfpUFixedToFpD(fpscr.fz, fpscr.dn, mid, false, imm);
1348 __asm__ __volatile__("" :: "m" (cDest));
1349 finishVfp(fpscr, state, fpscr.fz);
1350 Fpscr = fpscr;
1351 FpDestP0.uw = dblLow(cDest);
1352 FpDestP1.uw = dblHi(cDest);
1353 '''
1354 vcvtUFixedFpDIop = InstObjParams("vcvt", "VcvtUFixedFpD", "FpRegRegImmOp",
1355 { "code": vcvtUFixedFpDCode,
1356 "predicate_test": predicateTest }, [])
1357 header_output += FpRegRegImmOpDeclare.subst(vcvtUFixedFpDIop);
1358 decoder_output += FpRegRegImmOpConstructor.subst(vcvtUFixedFpDIop);
1359 exec_output += PredOpExecute.subst(vcvtUFixedFpDIop);
1360
1345 FPSCR fpscr = Fpscr;
1346 uint64_t mid = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
1347 VfpSavedState state = prepFpState(fpscr.rMode);
1348 __asm__ __volatile__("" : "=m" (mid) : "m" (mid));
1349 double cDest = vfpUFixedToFpD(fpscr.fz, fpscr.dn, mid, false, imm);
1350 __asm__ __volatile__("" :: "m" (cDest));
1351 finishVfp(fpscr, state, fpscr.fz);
1352 Fpscr = fpscr;
1353 FpDestP0.uw = dblLow(cDest);
1354 FpDestP1.uw = dblHi(cDest);
1355 '''
1356 vcvtUFixedFpDIop = InstObjParams("vcvt", "VcvtUFixedFpD", "FpRegRegImmOp",
1357 { "code": vcvtUFixedFpDCode,
1358 "predicate_test": predicateTest }, [])
1359 header_output += FpRegRegImmOpDeclare.subst(vcvtUFixedFpDIop);
1360 decoder_output += FpRegRegImmOpConstructor.subst(vcvtUFixedFpDIop);
1361 exec_output += PredOpExecute.subst(vcvtUFixedFpDIop);
1362
1361 vcvtFpSHFixedSCode = '''
1363 vcvtFpSHFixedSCode = vfpEnabledCheckCode + '''
1362 FPSCR fpscr = Fpscr;
1363 vfpFlushToZero(fpscr, FpOp1);
1364 VfpSavedState state = prepFpState(fpscr.rMode);
1365 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
1366 FpDest.sh = vfpFpSToFixed(FpOp1, true, true, imm);
1367 __asm__ __volatile__("" :: "m" (FpDest.sh));
1368 finishVfp(fpscr, state, fpscr.fz);
1369 Fpscr = fpscr;
1370 '''
1371 vcvtFpSHFixedSIop = InstObjParams("vcvt", "VcvtFpSHFixedS",
1372 "FpRegRegImmOp",
1373 { "code": vcvtFpSHFixedSCode,
1374 "predicate_test": predicateTest }, [])
1375 header_output += FpRegRegImmOpDeclare.subst(vcvtFpSHFixedSIop);
1376 decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpSHFixedSIop);
1377 exec_output += PredOpExecute.subst(vcvtFpSHFixedSIop);
1378
1364 FPSCR fpscr = Fpscr;
1365 vfpFlushToZero(fpscr, FpOp1);
1366 VfpSavedState state = prepFpState(fpscr.rMode);
1367 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
1368 FpDest.sh = vfpFpSToFixed(FpOp1, true, true, imm);
1369 __asm__ __volatile__("" :: "m" (FpDest.sh));
1370 finishVfp(fpscr, state, fpscr.fz);
1371 Fpscr = fpscr;
1372 '''
1373 vcvtFpSHFixedSIop = InstObjParams("vcvt", "VcvtFpSHFixedS",
1374 "FpRegRegImmOp",
1375 { "code": vcvtFpSHFixedSCode,
1376 "predicate_test": predicateTest }, [])
1377 header_output += FpRegRegImmOpDeclare.subst(vcvtFpSHFixedSIop);
1378 decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpSHFixedSIop);
1379 exec_output += PredOpExecute.subst(vcvtFpSHFixedSIop);
1380
1379 vcvtFpSHFixedDCode = '''
1381 vcvtFpSHFixedDCode = vfpEnabledCheckCode + '''
1380 FPSCR fpscr = Fpscr;
1381 double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw);
1382 vfpFlushToZero(fpscr, cOp1);
1383 VfpSavedState state = prepFpState(fpscr.rMode);
1384 __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1));
1385 uint64_t result = vfpFpDToFixed(cOp1, true, true, imm);
1386 __asm__ __volatile__("" :: "m" (result));
1387 finishVfp(fpscr, state, fpscr.fz);

--- 4 unchanged lines hidden (view full) ---

1392 vcvtFpSHFixedDIop = InstObjParams("vcvt", "VcvtFpSHFixedD",
1393 "FpRegRegImmOp",
1394 { "code": vcvtFpSHFixedDCode,
1395 "predicate_test": predicateTest }, [])
1396 header_output += FpRegRegImmOpDeclare.subst(vcvtFpSHFixedDIop);
1397 decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpSHFixedDIop);
1398 exec_output += PredOpExecute.subst(vcvtFpSHFixedDIop);
1399
1382 FPSCR fpscr = Fpscr;
1383 double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw);
1384 vfpFlushToZero(fpscr, cOp1);
1385 VfpSavedState state = prepFpState(fpscr.rMode);
1386 __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1));
1387 uint64_t result = vfpFpDToFixed(cOp1, true, true, imm);
1388 __asm__ __volatile__("" :: "m" (result));
1389 finishVfp(fpscr, state, fpscr.fz);

--- 4 unchanged lines hidden (view full) ---

1394 vcvtFpSHFixedDIop = InstObjParams("vcvt", "VcvtFpSHFixedD",
1395 "FpRegRegImmOp",
1396 { "code": vcvtFpSHFixedDCode,
1397 "predicate_test": predicateTest }, [])
1398 header_output += FpRegRegImmOpDeclare.subst(vcvtFpSHFixedDIop);
1399 decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpSHFixedDIop);
1400 exec_output += PredOpExecute.subst(vcvtFpSHFixedDIop);
1401
1400 vcvtFpUHFixedSCode = '''
1402 vcvtFpUHFixedSCode = vfpEnabledCheckCode + '''
1401 FPSCR fpscr = Fpscr;
1402 vfpFlushToZero(fpscr, FpOp1);
1403 VfpSavedState state = prepFpState(fpscr.rMode);
1404 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
1405 FpDest.uh = vfpFpSToFixed(FpOp1, false, true, imm);
1406 __asm__ __volatile__("" :: "m" (FpDest.uh));
1407 finishVfp(fpscr, state, fpscr.fz);
1408 Fpscr = fpscr;
1409 '''
1410 vcvtFpUHFixedSIop = InstObjParams("vcvt", "VcvtFpUHFixedS",
1411 "FpRegRegImmOp",
1412 { "code": vcvtFpUHFixedSCode,
1413 "predicate_test": predicateTest }, [])
1414 header_output += FpRegRegImmOpDeclare.subst(vcvtFpUHFixedSIop);
1415 decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpUHFixedSIop);
1416 exec_output += PredOpExecute.subst(vcvtFpUHFixedSIop);
1417
1403 FPSCR fpscr = Fpscr;
1404 vfpFlushToZero(fpscr, FpOp1);
1405 VfpSavedState state = prepFpState(fpscr.rMode);
1406 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
1407 FpDest.uh = vfpFpSToFixed(FpOp1, false, true, imm);
1408 __asm__ __volatile__("" :: "m" (FpDest.uh));
1409 finishVfp(fpscr, state, fpscr.fz);
1410 Fpscr = fpscr;
1411 '''
1412 vcvtFpUHFixedSIop = InstObjParams("vcvt", "VcvtFpUHFixedS",
1413 "FpRegRegImmOp",
1414 { "code": vcvtFpUHFixedSCode,
1415 "predicate_test": predicateTest }, [])
1416 header_output += FpRegRegImmOpDeclare.subst(vcvtFpUHFixedSIop);
1417 decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpUHFixedSIop);
1418 exec_output += PredOpExecute.subst(vcvtFpUHFixedSIop);
1419
1418 vcvtFpUHFixedDCode = '''
1420 vcvtFpUHFixedDCode = vfpEnabledCheckCode + '''
1419 FPSCR fpscr = Fpscr;
1420 double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw);
1421 vfpFlushToZero(fpscr, cOp1);
1422 VfpSavedState state = prepFpState(fpscr.rMode);
1423 __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1));
1424 uint64_t mid = vfpFpDToFixed(cOp1, false, true, imm);
1425 __asm__ __volatile__("" :: "m" (mid));
1426 finishVfp(fpscr, state, fpscr.fz);

--- 4 unchanged lines hidden (view full) ---

1431 vcvtFpUHFixedDIop = InstObjParams("vcvt", "VcvtFpUHFixedD",
1432 "FpRegRegImmOp",
1433 { "code": vcvtFpUHFixedDCode,
1434 "predicate_test": predicateTest }, [])
1435 header_output += FpRegRegImmOpDeclare.subst(vcvtFpUHFixedDIop);
1436 decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpUHFixedDIop);
1437 exec_output += PredOpExecute.subst(vcvtFpUHFixedDIop);
1438
1421 FPSCR fpscr = Fpscr;
1422 double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw);
1423 vfpFlushToZero(fpscr, cOp1);
1424 VfpSavedState state = prepFpState(fpscr.rMode);
1425 __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1));
1426 uint64_t mid = vfpFpDToFixed(cOp1, false, true, imm);
1427 __asm__ __volatile__("" :: "m" (mid));
1428 finishVfp(fpscr, state, fpscr.fz);

--- 4 unchanged lines hidden (view full) ---

1433 vcvtFpUHFixedDIop = InstObjParams("vcvt", "VcvtFpUHFixedD",
1434 "FpRegRegImmOp",
1435 { "code": vcvtFpUHFixedDCode,
1436 "predicate_test": predicateTest }, [])
1437 header_output += FpRegRegImmOpDeclare.subst(vcvtFpUHFixedDIop);
1438 decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpUHFixedDIop);
1439 exec_output += PredOpExecute.subst(vcvtFpUHFixedDIop);
1440
1439 vcvtSHFixedFpSCode = '''
1441 vcvtSHFixedFpSCode = vfpEnabledCheckCode + '''
1440 FPSCR fpscr = Fpscr;
1441 VfpSavedState state = prepFpState(fpscr.rMode);
1442 __asm__ __volatile__("" : "=m" (FpOp1.sh) : "m" (FpOp1.sh));
1443 FpDest = vfpSFixedToFpS(fpscr.fz, fpscr.dn, FpOp1.sh, true, imm);
1444 __asm__ __volatile__("" :: "m" (FpDest));
1445 finishVfp(fpscr, state, fpscr.fz);
1446 Fpscr = fpscr;
1447 '''
1448 vcvtSHFixedFpSIop = InstObjParams("vcvt", "VcvtSHFixedFpS",
1449 "FpRegRegImmOp",
1450 { "code": vcvtSHFixedFpSCode,
1451 "predicate_test": predicateTest }, [])
1452 header_output += FpRegRegImmOpDeclare.subst(vcvtSHFixedFpSIop);
1453 decoder_output += FpRegRegImmOpConstructor.subst(vcvtSHFixedFpSIop);
1454 exec_output += PredOpExecute.subst(vcvtSHFixedFpSIop);
1455
1442 FPSCR fpscr = Fpscr;
1443 VfpSavedState state = prepFpState(fpscr.rMode);
1444 __asm__ __volatile__("" : "=m" (FpOp1.sh) : "m" (FpOp1.sh));
1445 FpDest = vfpSFixedToFpS(fpscr.fz, fpscr.dn, FpOp1.sh, true, imm);
1446 __asm__ __volatile__("" :: "m" (FpDest));
1447 finishVfp(fpscr, state, fpscr.fz);
1448 Fpscr = fpscr;
1449 '''
1450 vcvtSHFixedFpSIop = InstObjParams("vcvt", "VcvtSHFixedFpS",
1451 "FpRegRegImmOp",
1452 { "code": vcvtSHFixedFpSCode,
1453 "predicate_test": predicateTest }, [])
1454 header_output += FpRegRegImmOpDeclare.subst(vcvtSHFixedFpSIop);
1455 decoder_output += FpRegRegImmOpConstructor.subst(vcvtSHFixedFpSIop);
1456 exec_output += PredOpExecute.subst(vcvtSHFixedFpSIop);
1457
1456 vcvtSHFixedFpDCode = '''
1458 vcvtSHFixedFpDCode = vfpEnabledCheckCode + '''
1457 FPSCR fpscr = Fpscr;
1458 uint64_t mid = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
1459 VfpSavedState state = prepFpState(fpscr.rMode);
1460 __asm__ __volatile__("" : "=m" (mid) : "m" (mid));
1461 double cDest = vfpSFixedToFpD(fpscr.fz, fpscr.dn, mid, true, imm);
1462 __asm__ __volatile__("" :: "m" (cDest));
1463 finishVfp(fpscr, state, fpscr.fz);
1464 Fpscr = fpscr;
1465 FpDestP0.uw = dblLow(cDest);
1466 FpDestP1.uw = dblHi(cDest);
1467 '''
1468 vcvtSHFixedFpDIop = InstObjParams("vcvt", "VcvtSHFixedFpD",
1469 "FpRegRegImmOp",
1470 { "code": vcvtSHFixedFpDCode,
1471 "predicate_test": predicateTest }, [])
1472 header_output += FpRegRegImmOpDeclare.subst(vcvtSHFixedFpDIop);
1473 decoder_output += FpRegRegImmOpConstructor.subst(vcvtSHFixedFpDIop);
1474 exec_output += PredOpExecute.subst(vcvtSHFixedFpDIop);
1475
1459 FPSCR fpscr = Fpscr;
1460 uint64_t mid = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
1461 VfpSavedState state = prepFpState(fpscr.rMode);
1462 __asm__ __volatile__("" : "=m" (mid) : "m" (mid));
1463 double cDest = vfpSFixedToFpD(fpscr.fz, fpscr.dn, mid, true, imm);
1464 __asm__ __volatile__("" :: "m" (cDest));
1465 finishVfp(fpscr, state, fpscr.fz);
1466 Fpscr = fpscr;
1467 FpDestP0.uw = dblLow(cDest);
1468 FpDestP1.uw = dblHi(cDest);
1469 '''
1470 vcvtSHFixedFpDIop = InstObjParams("vcvt", "VcvtSHFixedFpD",
1471 "FpRegRegImmOp",
1472 { "code": vcvtSHFixedFpDCode,
1473 "predicate_test": predicateTest }, [])
1474 header_output += FpRegRegImmOpDeclare.subst(vcvtSHFixedFpDIop);
1475 decoder_output += FpRegRegImmOpConstructor.subst(vcvtSHFixedFpDIop);
1476 exec_output += PredOpExecute.subst(vcvtSHFixedFpDIop);
1477
1476 vcvtUHFixedFpSCode = '''
1478 vcvtUHFixedFpSCode = vfpEnabledCheckCode + '''
1477 FPSCR fpscr = Fpscr;
1478 VfpSavedState state = prepFpState(fpscr.rMode);
1479 __asm__ __volatile__("" : "=m" (FpOp1.uh) : "m" (FpOp1.uh));
1480 FpDest = vfpUFixedToFpS(fpscr.fz, fpscr.dn, FpOp1.uh, true, imm);
1481 __asm__ __volatile__("" :: "m" (FpDest));
1482 finishVfp(fpscr, state, fpscr.fz);
1483 Fpscr = fpscr;
1484 '''
1485 vcvtUHFixedFpSIop = InstObjParams("vcvt", "VcvtUHFixedFpS",
1486 "FpRegRegImmOp",
1487 { "code": vcvtUHFixedFpSCode,
1488 "predicate_test": predicateTest }, [])
1489 header_output += FpRegRegImmOpDeclare.subst(vcvtUHFixedFpSIop);
1490 decoder_output += FpRegRegImmOpConstructor.subst(vcvtUHFixedFpSIop);
1491 exec_output += PredOpExecute.subst(vcvtUHFixedFpSIop);
1492
1479 FPSCR fpscr = Fpscr;
1480 VfpSavedState state = prepFpState(fpscr.rMode);
1481 __asm__ __volatile__("" : "=m" (FpOp1.uh) : "m" (FpOp1.uh));
1482 FpDest = vfpUFixedToFpS(fpscr.fz, fpscr.dn, FpOp1.uh, true, imm);
1483 __asm__ __volatile__("" :: "m" (FpDest));
1484 finishVfp(fpscr, state, fpscr.fz);
1485 Fpscr = fpscr;
1486 '''
1487 vcvtUHFixedFpSIop = InstObjParams("vcvt", "VcvtUHFixedFpS",
1488 "FpRegRegImmOp",
1489 { "code": vcvtUHFixedFpSCode,
1490 "predicate_test": predicateTest }, [])
1491 header_output += FpRegRegImmOpDeclare.subst(vcvtUHFixedFpSIop);
1492 decoder_output += FpRegRegImmOpConstructor.subst(vcvtUHFixedFpSIop);
1493 exec_output += PredOpExecute.subst(vcvtUHFixedFpSIop);
1494
1493 vcvtUHFixedFpDCode = '''
1495 vcvtUHFixedFpDCode = vfpEnabledCheckCode + '''
1494 FPSCR fpscr = Fpscr;
1495 uint64_t mid = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
1496 VfpSavedState state = prepFpState(fpscr.rMode);
1497 __asm__ __volatile__("" : "=m" (mid) : "m" (mid));
1498 double cDest = vfpUFixedToFpD(fpscr.fz, fpscr.dn, mid, true, imm);
1499 __asm__ __volatile__("" :: "m" (cDest));
1500 finishVfp(fpscr, state, fpscr.fz);
1501 Fpscr = fpscr;
1502 FpDestP0.uw = dblLow(cDest);
1503 FpDestP1.uw = dblHi(cDest);
1504 '''
1505 vcvtUHFixedFpDIop = InstObjParams("vcvt", "VcvtUHFixedFpD",
1506 "FpRegRegImmOp",
1507 { "code": vcvtUHFixedFpDCode,
1508 "predicate_test": predicateTest }, [])
1509 header_output += FpRegRegImmOpDeclare.subst(vcvtUHFixedFpDIop);
1510 decoder_output += FpRegRegImmOpConstructor.subst(vcvtUHFixedFpDIop);
1511 exec_output += PredOpExecute.subst(vcvtUHFixedFpDIop);
1512}};
1496 FPSCR fpscr = Fpscr;
1497 uint64_t mid = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
1498 VfpSavedState state = prepFpState(fpscr.rMode);
1499 __asm__ __volatile__("" : "=m" (mid) : "m" (mid));
1500 double cDest = vfpUFixedToFpD(fpscr.fz, fpscr.dn, mid, true, imm);
1501 __asm__ __volatile__("" :: "m" (cDest));
1502 finishVfp(fpscr, state, fpscr.fz);
1503 Fpscr = fpscr;
1504 FpDestP0.uw = dblLow(cDest);
1505 FpDestP1.uw = dblHi(cDest);
1506 '''
1507 vcvtUHFixedFpDIop = InstObjParams("vcvt", "VcvtUHFixedFpD",
1508 "FpRegRegImmOp",
1509 { "code": vcvtUHFixedFpDCode,
1510 "predicate_test": predicateTest }, [])
1511 header_output += FpRegRegImmOpDeclare.subst(vcvtUHFixedFpDIop);
1512 decoder_output += FpRegRegImmOpConstructor.subst(vcvtUHFixedFpDIop);
1513 exec_output += PredOpExecute.subst(vcvtUHFixedFpDIop);
1514}};