fp.isa (7396:53454ef35b46) | fp.isa (7397:cbd950459a29) |
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1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating --- 646 unchanged lines hidden (view full) --- 655 656let {{ 657 658 header_output = "" 659 decoder_output = "" 660 exec_output = "" 661 662 vcvtUIntFpSCode = ''' | 1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating --- 646 unchanged lines hidden (view full) --- 655 656let {{ 657 658 header_output = "" 659 decoder_output = "" 660 exec_output = "" 661 662 vcvtUIntFpSCode = ''' |
663 VfpSavedState state = prepVfpFpscr(Fpscr); | 663 FPSCR fpscr = Fpscr; 664 VfpSavedState state = prepFpState(fpscr.rMode); |
664 __asm__ __volatile__("" : "=m" (FpOp1.uw) : "m" (FpOp1.uw)); 665 FpDest = FpOp1.uw; 666 __asm__ __volatile__("" :: "m" (FpDest)); | 665 __asm__ __volatile__("" : "=m" (FpOp1.uw) : "m" (FpOp1.uw)); 666 FpDest = FpOp1.uw; 667 __asm__ __volatile__("" :: "m" (FpDest)); |
667 Fpscr = setVfpFpscr(Fpscr, state); | 668 finishVfp(fpscr, state); 669 Fpscr = fpscr; |
668 ''' 669 vcvtUIntFpSIop = InstObjParams("vcvt", "VcvtUIntFpS", "FpRegRegOp", 670 { "code": vcvtUIntFpSCode, 671 "predicate_test": predicateTest }, []) 672 header_output += FpRegRegOpDeclare.subst(vcvtUIntFpSIop); 673 decoder_output += FpRegRegOpConstructor.subst(vcvtUIntFpSIop); 674 exec_output += PredOpExecute.subst(vcvtUIntFpSIop); 675 676 vcvtUIntFpDCode = ''' | 670 ''' 671 vcvtUIntFpSIop = InstObjParams("vcvt", "VcvtUIntFpS", "FpRegRegOp", 672 { "code": vcvtUIntFpSCode, 673 "predicate_test": predicateTest }, []) 674 header_output += FpRegRegOpDeclare.subst(vcvtUIntFpSIop); 675 decoder_output += FpRegRegOpConstructor.subst(vcvtUIntFpSIop); 676 exec_output += PredOpExecute.subst(vcvtUIntFpSIop); 677 678 vcvtUIntFpDCode = ''' |
677 IntDoubleUnion cDest; 678 VfpSavedState state = prepVfpFpscr(Fpscr); | 679 FPSCR fpscr = Fpscr; 680 VfpSavedState state = prepFpState(fpscr.rMode); |
679 __asm__ __volatile__("" : "=m" (FpOp1P0.uw) : "m" (FpOp1P0.uw)); | 681 __asm__ __volatile__("" : "=m" (FpOp1P0.uw) : "m" (FpOp1P0.uw)); |
680 cDest.fp = (uint64_t)FpOp1P0.uw; 681 __asm__ __volatile__("" :: "m" (cDest.fp)); 682 Fpscr = setVfpFpscr(Fpscr, state); 683 FpDestP0.uw = cDest.bits; 684 FpDestP1.uw = cDest.bits >> 32; | 682 double cDest = (uint64_t)FpOp1P0.uw; 683 __asm__ __volatile__("" :: "m" (cDest)); 684 finishVfp(fpscr, state); 685 Fpscr = fpscr; 686 FpDestP0.uw = dblLow(cDest); 687 FpDestP1.uw = dblHi(cDest); |
685 ''' 686 vcvtUIntFpDIop = InstObjParams("vcvt", "VcvtUIntFpD", "FpRegRegOp", 687 { "code": vcvtUIntFpDCode, 688 "predicate_test": predicateTest }, []) 689 header_output += FpRegRegOpDeclare.subst(vcvtUIntFpDIop); 690 decoder_output += FpRegRegOpConstructor.subst(vcvtUIntFpDIop); 691 exec_output += PredOpExecute.subst(vcvtUIntFpDIop); 692 693 vcvtSIntFpSCode = ''' | 688 ''' 689 vcvtUIntFpDIop = InstObjParams("vcvt", "VcvtUIntFpD", "FpRegRegOp", 690 { "code": vcvtUIntFpDCode, 691 "predicate_test": predicateTest }, []) 692 header_output += FpRegRegOpDeclare.subst(vcvtUIntFpDIop); 693 decoder_output += FpRegRegOpConstructor.subst(vcvtUIntFpDIop); 694 exec_output += PredOpExecute.subst(vcvtUIntFpDIop); 695 696 vcvtSIntFpSCode = ''' |
694 VfpSavedState state = prepVfpFpscr(Fpscr); | 697 FPSCR fpscr = Fpscr; 698 VfpSavedState state = prepFpState(fpscr.rMode); |
695 __asm__ __volatile__("" : "=m" (FpOp1.sw) : "m" (FpOp1.sw)); 696 FpDest = FpOp1.sw; 697 __asm__ __volatile__("" :: "m" (FpDest)); | 699 __asm__ __volatile__("" : "=m" (FpOp1.sw) : "m" (FpOp1.sw)); 700 FpDest = FpOp1.sw; 701 __asm__ __volatile__("" :: "m" (FpDest)); |
698 Fpscr = setVfpFpscr(Fpscr, state); | 702 finishVfp(fpscr, state); 703 Fpscr = fpscr; |
699 ''' 700 vcvtSIntFpSIop = InstObjParams("vcvt", "VcvtSIntFpS", "FpRegRegOp", 701 { "code": vcvtSIntFpSCode, 702 "predicate_test": predicateTest }, []) 703 header_output += FpRegRegOpDeclare.subst(vcvtSIntFpSIop); 704 decoder_output += FpRegRegOpConstructor.subst(vcvtSIntFpSIop); 705 exec_output += PredOpExecute.subst(vcvtSIntFpSIop); 706 707 vcvtSIntFpDCode = ''' | 704 ''' 705 vcvtSIntFpSIop = InstObjParams("vcvt", "VcvtSIntFpS", "FpRegRegOp", 706 { "code": vcvtSIntFpSCode, 707 "predicate_test": predicateTest }, []) 708 header_output += FpRegRegOpDeclare.subst(vcvtSIntFpSIop); 709 decoder_output += FpRegRegOpConstructor.subst(vcvtSIntFpSIop); 710 exec_output += PredOpExecute.subst(vcvtSIntFpSIop); 711 712 vcvtSIntFpDCode = ''' |
708 IntDoubleUnion cDest; 709 VfpSavedState state = prepVfpFpscr(Fpscr); | 713 FPSCR fpscr = Fpscr; 714 VfpSavedState state = prepFpState(fpscr.rMode); |
710 __asm__ __volatile__("" : "=m" (FpOp1P0.sw) : "m" (FpOp1P0.sw)); | 715 __asm__ __volatile__("" : "=m" (FpOp1P0.sw) : "m" (FpOp1P0.sw)); |
711 cDest.fp = FpOp1P0.sw; 712 __asm__ __volatile__("" :: "m" (cDest.fp)); 713 Fpscr = setVfpFpscr(Fpscr, state); 714 FpDestP0.uw = cDest.bits; 715 FpDestP1.uw = cDest.bits >> 32; | 716 double cDest = FpOp1P0.sw; 717 __asm__ __volatile__("" :: "m" (cDest)); 718 finishVfp(fpscr, state); 719 Fpscr = fpscr; 720 FpDestP0.uw = dblLow(cDest); 721 FpDestP1.uw = dblHi(cDest); |
716 ''' 717 vcvtSIntFpDIop = InstObjParams("vcvt", "VcvtSIntFpD", "FpRegRegOp", 718 { "code": vcvtSIntFpDCode, 719 "predicate_test": predicateTest }, []) 720 header_output += FpRegRegOpDeclare.subst(vcvtSIntFpDIop); 721 decoder_output += FpRegRegOpConstructor.subst(vcvtSIntFpDIop); 722 exec_output += PredOpExecute.subst(vcvtSIntFpDIop); 723 724 vcvtFpUIntSRCode = ''' | 722 ''' 723 vcvtSIntFpDIop = InstObjParams("vcvt", "VcvtSIntFpD", "FpRegRegOp", 724 { "code": vcvtSIntFpDCode, 725 "predicate_test": predicateTest }, []) 726 header_output += FpRegRegOpDeclare.subst(vcvtSIntFpDIop); 727 decoder_output += FpRegRegOpConstructor.subst(vcvtSIntFpDIop); 728 exec_output += PredOpExecute.subst(vcvtSIntFpDIop); 729 730 vcvtFpUIntSRCode = ''' |
725 vfpFlushToZero(Fpscr, FpOp1); 726 VfpSavedState state = prepVfpFpscr(Fpscr); | 731 FPSCR fpscr = Fpscr; 732 VfpSavedState state = prepFpState(fpscr.rMode); 733 vfpFlushToZero(fpscr, FpOp1); |
727 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 728 FpDest.uw = vfpFpSToFixed(FpOp1, false, false, 0, false); 729 __asm__ __volatile__("" :: "m" (FpDest.uw)); | 734 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 735 FpDest.uw = vfpFpSToFixed(FpOp1, false, false, 0, false); 736 __asm__ __volatile__("" :: "m" (FpDest.uw)); |
730 Fpscr = setVfpFpscr(Fpscr, state); | 737 finishVfp(fpscr, state); 738 Fpscr = fpscr; |
731 ''' 732 vcvtFpUIntSRIop = InstObjParams("vcvt", "VcvtFpUIntSR", "FpRegRegOp", 733 { "code": vcvtFpUIntSRCode, 734 "predicate_test": predicateTest }, []) 735 header_output += FpRegRegOpDeclare.subst(vcvtFpUIntSRIop); 736 decoder_output += FpRegRegOpConstructor.subst(vcvtFpUIntSRIop); 737 exec_output += PredOpExecute.subst(vcvtFpUIntSRIop); 738 739 vcvtFpUIntDRCode = ''' | 739 ''' 740 vcvtFpUIntSRIop = InstObjParams("vcvt", "VcvtFpUIntSR", "FpRegRegOp", 741 { "code": vcvtFpUIntSRCode, 742 "predicate_test": predicateTest }, []) 743 header_output += FpRegRegOpDeclare.subst(vcvtFpUIntSRIop); 744 decoder_output += FpRegRegOpConstructor.subst(vcvtFpUIntSRIop); 745 exec_output += PredOpExecute.subst(vcvtFpUIntSRIop); 746 747 vcvtFpUIntDRCode = ''' |
740 IntDoubleUnion cOp1; 741 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 742 vfpFlushToZero(Fpscr, cOp1.fp); 743 VfpSavedState state = prepVfpFpscr(Fpscr); 744 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp)); 745 uint64_t result = vfpFpDToFixed(cOp1.fp, false, false, 0, false); | 748 FPSCR fpscr = Fpscr; 749 double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw); 750 vfpFlushToZero(fpscr, cOp1); 751 VfpSavedState state = prepFpState(fpscr.rMode); 752 __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); 753 uint64_t result = vfpFpDToFixed(cOp1, false, false, 0, false); |
746 __asm__ __volatile__("" :: "m" (result)); | 754 __asm__ __volatile__("" :: "m" (result)); |
747 Fpscr = setVfpFpscr(Fpscr, state); | 755 finishVfp(fpscr, state); 756 Fpscr = fpscr; |
748 FpDestP0.uw = result; 749 ''' 750 vcvtFpUIntDRIop = InstObjParams("vcvtr", "VcvtFpUIntDR", "FpRegRegOp", 751 { "code": vcvtFpUIntDRCode, 752 "predicate_test": predicateTest }, []) 753 header_output += FpRegRegOpDeclare.subst(vcvtFpUIntDRIop); 754 decoder_output += FpRegRegOpConstructor.subst(vcvtFpUIntDRIop); 755 exec_output += PredOpExecute.subst(vcvtFpUIntDRIop); 756 757 vcvtFpSIntSRCode = ''' | 757 FpDestP0.uw = result; 758 ''' 759 vcvtFpUIntDRIop = InstObjParams("vcvtr", "VcvtFpUIntDR", "FpRegRegOp", 760 { "code": vcvtFpUIntDRCode, 761 "predicate_test": predicateTest }, []) 762 header_output += FpRegRegOpDeclare.subst(vcvtFpUIntDRIop); 763 decoder_output += FpRegRegOpConstructor.subst(vcvtFpUIntDRIop); 764 exec_output += PredOpExecute.subst(vcvtFpUIntDRIop); 765 766 vcvtFpSIntSRCode = ''' |
758 vfpFlushToZero(Fpscr, FpOp1); 759 VfpSavedState state = prepVfpFpscr(Fpscr); | 767 FPSCR fpscr = Fpscr; 768 VfpSavedState state = prepFpState(fpscr.rMode); 769 vfpFlushToZero(fpscr, FpOp1); |
760 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 761 FpDest.sw = vfpFpSToFixed(FpOp1, true, false, 0, false); 762 __asm__ __volatile__("" :: "m" (FpDest.sw)); | 770 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 771 FpDest.sw = vfpFpSToFixed(FpOp1, true, false, 0, false); 772 __asm__ __volatile__("" :: "m" (FpDest.sw)); |
763 Fpscr = setVfpFpscr(Fpscr, state); | 773 finishVfp(fpscr, state); 774 Fpscr = fpscr; |
764 ''' 765 vcvtFpSIntSRIop = InstObjParams("vcvtr", "VcvtFpSIntSR", "FpRegRegOp", 766 { "code": vcvtFpSIntSRCode, 767 "predicate_test": predicateTest }, []) 768 header_output += FpRegRegOpDeclare.subst(vcvtFpSIntSRIop); 769 decoder_output += FpRegRegOpConstructor.subst(vcvtFpSIntSRIop); 770 exec_output += PredOpExecute.subst(vcvtFpSIntSRIop); 771 772 vcvtFpSIntDRCode = ''' | 775 ''' 776 vcvtFpSIntSRIop = InstObjParams("vcvtr", "VcvtFpSIntSR", "FpRegRegOp", 777 { "code": vcvtFpSIntSRCode, 778 "predicate_test": predicateTest }, []) 779 header_output += FpRegRegOpDeclare.subst(vcvtFpSIntSRIop); 780 decoder_output += FpRegRegOpConstructor.subst(vcvtFpSIntSRIop); 781 exec_output += PredOpExecute.subst(vcvtFpSIntSRIop); 782 783 vcvtFpSIntDRCode = ''' |
773 IntDoubleUnion cOp1; 774 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 775 vfpFlushToZero(Fpscr, cOp1.fp); 776 VfpSavedState state = prepVfpFpscr(Fpscr); 777 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp)); 778 int64_t result = vfpFpDToFixed(cOp1.fp, true, false, 0, false); | 784 FPSCR fpscr = Fpscr; 785 double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw); 786 vfpFlushToZero(fpscr, cOp1); 787 VfpSavedState state = prepFpState(fpscr.rMode); 788 __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); 789 int64_t result = vfpFpDToFixed(cOp1, true, false, 0, false); |
779 __asm__ __volatile__("" :: "m" (result)); | 790 __asm__ __volatile__("" :: "m" (result)); |
780 Fpscr = setVfpFpscr(Fpscr, state); | 791 finishVfp(fpscr, state); 792 Fpscr = fpscr; |
781 FpDestP0.uw = result; 782 ''' 783 vcvtFpSIntDRIop = InstObjParams("vcvtr", "VcvtFpSIntDR", "FpRegRegOp", 784 { "code": vcvtFpSIntDRCode, 785 "predicate_test": predicateTest }, []) 786 header_output += FpRegRegOpDeclare.subst(vcvtFpSIntDRIop); 787 decoder_output += FpRegRegOpConstructor.subst(vcvtFpSIntDRIop); 788 exec_output += PredOpExecute.subst(vcvtFpSIntDRIop); 789 790 vcvtFpUIntSCode = ''' | 793 FpDestP0.uw = result; 794 ''' 795 vcvtFpSIntDRIop = InstObjParams("vcvtr", "VcvtFpSIntDR", "FpRegRegOp", 796 { "code": vcvtFpSIntDRCode, 797 "predicate_test": predicateTest }, []) 798 header_output += FpRegRegOpDeclare.subst(vcvtFpSIntDRIop); 799 decoder_output += FpRegRegOpConstructor.subst(vcvtFpSIntDRIop); 800 exec_output += PredOpExecute.subst(vcvtFpSIntDRIop); 801 802 vcvtFpUIntSCode = ''' |
791 vfpFlushToZero(Fpscr, FpOp1); 792 VfpSavedState state = prepVfpFpscr(Fpscr); | 803 FPSCR fpscr = Fpscr; 804 vfpFlushToZero(fpscr, FpOp1); 805 VfpSavedState state = prepFpState(fpscr.rMode); |
793 fesetround(FeRoundZero); 794 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 795 FpDest.uw = vfpFpSToFixed(FpOp1, false, false, 0); 796 __asm__ __volatile__("" :: "m" (FpDest.uw)); | 806 fesetround(FeRoundZero); 807 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 808 FpDest.uw = vfpFpSToFixed(FpOp1, false, false, 0); 809 __asm__ __volatile__("" :: "m" (FpDest.uw)); |
797 Fpscr = setVfpFpscr(Fpscr, state); | 810 finishVfp(fpscr, state); 811 Fpscr = fpscr; |
798 ''' 799 vcvtFpUIntSIop = InstObjParams("vcvt", "VcvtFpUIntS", "FpRegRegOp", 800 { "code": vcvtFpUIntSCode, 801 "predicate_test": predicateTest }, []) 802 header_output += FpRegRegOpDeclare.subst(vcvtFpUIntSIop); 803 decoder_output += FpRegRegOpConstructor.subst(vcvtFpUIntSIop); 804 exec_output += PredOpExecute.subst(vcvtFpUIntSIop); 805 806 vcvtFpUIntDCode = ''' | 812 ''' 813 vcvtFpUIntSIop = InstObjParams("vcvt", "VcvtFpUIntS", "FpRegRegOp", 814 { "code": vcvtFpUIntSCode, 815 "predicate_test": predicateTest }, []) 816 header_output += FpRegRegOpDeclare.subst(vcvtFpUIntSIop); 817 decoder_output += FpRegRegOpConstructor.subst(vcvtFpUIntSIop); 818 exec_output += PredOpExecute.subst(vcvtFpUIntSIop); 819 820 vcvtFpUIntDCode = ''' |
807 IntDoubleUnion cOp1; 808 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 809 vfpFlushToZero(Fpscr, cOp1.fp); 810 VfpSavedState state = prepVfpFpscr(Fpscr); | 821 FPSCR fpscr = Fpscr; 822 double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw); 823 vfpFlushToZero(fpscr, cOp1); 824 VfpSavedState state = prepFpState(fpscr.rMode); |
811 fesetround(FeRoundZero); | 825 fesetround(FeRoundZero); |
812 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp)); 813 uint64_t result = vfpFpDToFixed(cOp1.fp, false, false, 0); | 826 __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); 827 uint64_t result = vfpFpDToFixed(cOp1, false, false, 0); |
814 __asm__ __volatile__("" :: "m" (result)); | 828 __asm__ __volatile__("" :: "m" (result)); |
815 Fpscr = setVfpFpscr(Fpscr, state); | 829 finishVfp(fpscr, state); 830 Fpscr = fpscr; |
816 FpDestP0.uw = result; 817 ''' 818 vcvtFpUIntDIop = InstObjParams("vcvt", "VcvtFpUIntD", "FpRegRegOp", 819 { "code": vcvtFpUIntDCode, 820 "predicate_test": predicateTest }, []) 821 header_output += FpRegRegOpDeclare.subst(vcvtFpUIntDIop); 822 decoder_output += FpRegRegOpConstructor.subst(vcvtFpUIntDIop); 823 exec_output += PredOpExecute.subst(vcvtFpUIntDIop); 824 825 vcvtFpSIntSCode = ''' | 831 FpDestP0.uw = result; 832 ''' 833 vcvtFpUIntDIop = InstObjParams("vcvt", "VcvtFpUIntD", "FpRegRegOp", 834 { "code": vcvtFpUIntDCode, 835 "predicate_test": predicateTest }, []) 836 header_output += FpRegRegOpDeclare.subst(vcvtFpUIntDIop); 837 decoder_output += FpRegRegOpConstructor.subst(vcvtFpUIntDIop); 838 exec_output += PredOpExecute.subst(vcvtFpUIntDIop); 839 840 vcvtFpSIntSCode = ''' |
826 vfpFlushToZero(Fpscr, FpOp1); 827 VfpSavedState state = prepVfpFpscr(Fpscr); | 841 FPSCR fpscr = Fpscr; 842 vfpFlushToZero(fpscr, FpOp1); 843 VfpSavedState state = prepFpState(fpscr.rMode); |
828 fesetround(FeRoundZero); 829 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 830 FpDest.sw = vfpFpSToFixed(FpOp1, true, false, 0); 831 __asm__ __volatile__("" :: "m" (FpDest.sw)); | 844 fesetround(FeRoundZero); 845 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 846 FpDest.sw = vfpFpSToFixed(FpOp1, true, false, 0); 847 __asm__ __volatile__("" :: "m" (FpDest.sw)); |
832 Fpscr = setVfpFpscr(Fpscr, state); | 848 finishVfp(fpscr, state); 849 Fpscr = fpscr; |
833 ''' 834 vcvtFpSIntSIop = InstObjParams("vcvt", "VcvtFpSIntS", "FpRegRegOp", 835 { "code": vcvtFpSIntSCode, 836 "predicate_test": predicateTest }, []) 837 header_output += FpRegRegOpDeclare.subst(vcvtFpSIntSIop); 838 decoder_output += FpRegRegOpConstructor.subst(vcvtFpSIntSIop); 839 exec_output += PredOpExecute.subst(vcvtFpSIntSIop); 840 841 vcvtFpSIntDCode = ''' | 850 ''' 851 vcvtFpSIntSIop = InstObjParams("vcvt", "VcvtFpSIntS", "FpRegRegOp", 852 { "code": vcvtFpSIntSCode, 853 "predicate_test": predicateTest }, []) 854 header_output += FpRegRegOpDeclare.subst(vcvtFpSIntSIop); 855 decoder_output += FpRegRegOpConstructor.subst(vcvtFpSIntSIop); 856 exec_output += PredOpExecute.subst(vcvtFpSIntSIop); 857 858 vcvtFpSIntDCode = ''' |
842 IntDoubleUnion cOp1; 843 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 844 vfpFlushToZero(Fpscr, cOp1.fp); 845 VfpSavedState state = prepVfpFpscr(Fpscr); | 859 FPSCR fpscr = Fpscr; 860 double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw); 861 vfpFlushToZero(fpscr, cOp1); 862 VfpSavedState state = prepFpState(fpscr.rMode); |
846 fesetround(FeRoundZero); | 863 fesetround(FeRoundZero); |
847 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp)); 848 int64_t result = vfpFpDToFixed(cOp1.fp, true, false, 0); | 864 __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); 865 int64_t result = vfpFpDToFixed(cOp1, true, false, 0); |
849 __asm__ __volatile__("" :: "m" (result)); | 866 __asm__ __volatile__("" :: "m" (result)); |
850 Fpscr = setVfpFpscr(Fpscr, state); | 867 finishVfp(fpscr, state); 868 Fpscr = fpscr; |
851 FpDestP0.uw = result; 852 ''' 853 vcvtFpSIntDIop = InstObjParams("vcvt", "VcvtFpSIntD", "FpRegRegOp", 854 { "code": vcvtFpSIntDCode, 855 "predicate_test": predicateTest }, []) 856 header_output += FpRegRegOpDeclare.subst(vcvtFpSIntDIop); 857 decoder_output += FpRegRegOpConstructor.subst(vcvtFpSIntDIop); 858 exec_output += PredOpExecute.subst(vcvtFpSIntDIop); 859 860 vcvtFpSFpDCode = ''' | 869 FpDestP0.uw = result; 870 ''' 871 vcvtFpSIntDIop = InstObjParams("vcvt", "VcvtFpSIntD", "FpRegRegOp", 872 { "code": vcvtFpSIntDCode, 873 "predicate_test": predicateTest }, []) 874 header_output += FpRegRegOpDeclare.subst(vcvtFpSIntDIop); 875 decoder_output += FpRegRegOpConstructor.subst(vcvtFpSIntDIop); 876 exec_output += PredOpExecute.subst(vcvtFpSIntDIop); 877 878 vcvtFpSFpDCode = ''' |
861 IntDoubleUnion cDest; 862 vfpFlushToZero(Fpscr, FpOp1); 863 VfpSavedState state = prepVfpFpscr(Fpscr); | 879 FPSCR fpscr = Fpscr; 880 vfpFlushToZero(fpscr, FpOp1); 881 VfpSavedState state = prepFpState(fpscr.rMode); |
864 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); | 882 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); |
865 cDest.fp = fixFpSFpDDest(Fpscr, FpOp1); 866 __asm__ __volatile__("" :: "m" (cDest.fp)); 867 Fpscr = setVfpFpscr(Fpscr, state); 868 FpDestP0.uw = cDest.bits; 869 FpDestP1.uw = cDest.bits >> 32; | 883 double cDest = fixFpSFpDDest(Fpscr, FpOp1); 884 __asm__ __volatile__("" :: "m" (cDest)); 885 finishVfp(fpscr, state); 886 Fpscr = fpscr; 887 FpDestP0.uw = dblLow(cDest); 888 FpDestP1.uw = dblHi(cDest); |
870 ''' 871 vcvtFpSFpDIop = InstObjParams("vcvt", "VcvtFpSFpD", "FpRegRegOp", 872 { "code": vcvtFpSFpDCode, 873 "predicate_test": predicateTest }, []) 874 header_output += FpRegRegOpDeclare.subst(vcvtFpSFpDIop); 875 decoder_output += FpRegRegOpConstructor.subst(vcvtFpSFpDIop); 876 exec_output += PredOpExecute.subst(vcvtFpSFpDIop); 877 878 vcvtFpDFpSCode = ''' | 889 ''' 890 vcvtFpSFpDIop = InstObjParams("vcvt", "VcvtFpSFpD", "FpRegRegOp", 891 { "code": vcvtFpSFpDCode, 892 "predicate_test": predicateTest }, []) 893 header_output += FpRegRegOpDeclare.subst(vcvtFpSFpDIop); 894 decoder_output += FpRegRegOpConstructor.subst(vcvtFpSFpDIop); 895 exec_output += PredOpExecute.subst(vcvtFpSFpDIop); 896 897 vcvtFpDFpSCode = ''' |
879 IntDoubleUnion cOp1; 880 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 881 vfpFlushToZero(Fpscr, cOp1.fp); 882 VfpSavedState state = prepVfpFpscr(Fpscr); 883 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp)); 884 FpDest = fixFpDFpSDest(Fpscr, cOp1.fp); | 898 FPSCR fpscr = Fpscr; 899 double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw); 900 vfpFlushToZero(fpscr, cOp1); 901 VfpSavedState state = prepFpState(fpscr.rMode); 902 __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); 903 FpDest = fixFpDFpSDest(Fpscr, cOp1); |
885 __asm__ __volatile__("" :: "m" (FpDest)); | 904 __asm__ __volatile__("" :: "m" (FpDest)); |
886 Fpscr = setVfpFpscr(Fpscr, state); | 905 finishVfp(fpscr, state); 906 Fpscr = fpscr; |
887 ''' 888 vcvtFpDFpSIop = InstObjParams("vcvt", "VcvtFpDFpS", "FpRegRegOp", 889 { "code": vcvtFpDFpSCode, 890 "predicate_test": predicateTest }, []) 891 header_output += FpRegRegOpDeclare.subst(vcvtFpDFpSIop); 892 decoder_output += FpRegRegOpConstructor.subst(vcvtFpDFpSIop); 893 exec_output += PredOpExecute.subst(vcvtFpDFpSIop); 894 895 vcmpSCode = ''' | 907 ''' 908 vcvtFpDFpSIop = InstObjParams("vcvt", "VcvtFpDFpS", "FpRegRegOp", 909 { "code": vcvtFpDFpSCode, 910 "predicate_test": predicateTest }, []) 911 header_output += FpRegRegOpDeclare.subst(vcvtFpDFpSIop); 912 decoder_output += FpRegRegOpConstructor.subst(vcvtFpDFpSIop); 913 exec_output += PredOpExecute.subst(vcvtFpDFpSIop); 914 915 vcmpSCode = ''' |
896 vfpFlushToZero(Fpscr, FpDest, FpOp1); | |
897 FPSCR fpscr = Fpscr; | 916 FPSCR fpscr = Fpscr; |
917 vfpFlushToZero(fpscr, FpDest, FpOp1); |
|
898 if (FpDest == FpOp1) { 899 fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 900 } else if (FpDest < FpOp1) { 901 fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 902 } else if (FpDest > FpOp1) { 903 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 904 } else { 905 const uint32_t qnan = 0x7fc00000; --- 10 unchanged lines hidden (view full) --- 916 vcmpSIop = InstObjParams("vcmps", "VcmpS", "FpRegRegOp", 917 { "code": vcmpSCode, 918 "predicate_test": predicateTest }, []) 919 header_output += FpRegRegOpDeclare.subst(vcmpSIop); 920 decoder_output += FpRegRegOpConstructor.subst(vcmpSIop); 921 exec_output += PredOpExecute.subst(vcmpSIop); 922 923 vcmpDCode = ''' | 918 if (FpDest == FpOp1) { 919 fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 920 } else if (FpDest < FpOp1) { 921 fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 922 } else if (FpDest > FpOp1) { 923 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 924 } else { 925 const uint32_t qnan = 0x7fc00000; --- 10 unchanged lines hidden (view full) --- 936 vcmpSIop = InstObjParams("vcmps", "VcmpS", "FpRegRegOp", 937 { "code": vcmpSCode, 938 "predicate_test": predicateTest }, []) 939 header_output += FpRegRegOpDeclare.subst(vcmpSIop); 940 decoder_output += FpRegRegOpConstructor.subst(vcmpSIop); 941 exec_output += PredOpExecute.subst(vcmpSIop); 942 943 vcmpDCode = ''' |
924 IntDoubleUnion cOp1, cDest; 925 cDest.bits = ((uint64_t)FpDestP0.uw | ((uint64_t)FpDestP1.uw << 32)); 926 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 927 vfpFlushToZero(Fpscr, cDest.fp, cOp1.fp); | 944 double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw); 945 double cDest = dbl(FpDestP0.uw, FpDestP1.uw); |
928 FPSCR fpscr = Fpscr; | 946 FPSCR fpscr = Fpscr; |
929 if (cDest.fp == cOp1.fp) { | 947 vfpFlushToZero(fpscr, cDest, cOp1); 948 if (cDest == cOp1) { |
930 fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; | 949 fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; |
931 } else if (cDest.fp < cOp1.fp) { | 950 } else if (cDest < cOp1) { |
932 fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; | 951 fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; |
933 } else if (cDest.fp > cOp1.fp) { | 952 } else if (cDest > cOp1) { |
934 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 935 } else { 936 const uint64_t qnan = ULL(0x7ff8000000000000); | 953 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 954 } else { 955 const uint64_t qnan = ULL(0x7ff8000000000000); |
937 const bool nan1 = std::isnan(cDest.fp); 938 const bool signal1 = nan1 && ((cDest.bits & qnan) != qnan); 939 const bool nan2 = std::isnan(cOp1.fp); 940 const bool signal2 = nan2 && ((cOp1.bits & qnan) != qnan); | 956 const bool nan1 = std::isnan(cDest); 957 const bool signal1 = nan1 && ((fpToBits(cDest) & qnan) != qnan); 958 const bool nan2 = std::isnan(cOp1); 959 const bool signal2 = nan2 && ((fpToBits(cOp1) & qnan) != qnan); |
941 if (signal1 || signal2) 942 fpscr.ioc = 1; 943 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 944 } 945 Fpscr = fpscr; 946 ''' 947 vcmpDIop = InstObjParams("vcmpd", "VcmpD", "FpRegRegOp", 948 { "code": vcmpDCode, 949 "predicate_test": predicateTest }, []) 950 header_output += FpRegRegOpDeclare.subst(vcmpDIop); 951 decoder_output += FpRegRegOpConstructor.subst(vcmpDIop); 952 exec_output += PredOpExecute.subst(vcmpDIop); 953 954 vcmpZeroSCode = ''' | 960 if (signal1 || signal2) 961 fpscr.ioc = 1; 962 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 963 } 964 Fpscr = fpscr; 965 ''' 966 vcmpDIop = InstObjParams("vcmpd", "VcmpD", "FpRegRegOp", 967 { "code": vcmpDCode, 968 "predicate_test": predicateTest }, []) 969 header_output += FpRegRegOpDeclare.subst(vcmpDIop); 970 decoder_output += FpRegRegOpConstructor.subst(vcmpDIop); 971 exec_output += PredOpExecute.subst(vcmpDIop); 972 973 vcmpZeroSCode = ''' |
955 vfpFlushToZero(Fpscr, FpDest); | |
956 FPSCR fpscr = Fpscr; | 974 FPSCR fpscr = Fpscr; |
975 vfpFlushToZero(fpscr, FpDest); |
|
957 // This only handles imm == 0 for now. 958 assert(imm == 0); 959 if (FpDest == imm) { 960 fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 961 } else if (FpDest < imm) { 962 fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 963 } else if (FpDest > imm) { 964 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; --- 10 unchanged lines hidden (view full) --- 975 vcmpZeroSIop = InstObjParams("vcmpZeros", "VcmpZeroS", "FpRegImmOp", 976 { "code": vcmpZeroSCode, 977 "predicate_test": predicateTest }, []) 978 header_output += FpRegImmOpDeclare.subst(vcmpZeroSIop); 979 decoder_output += FpRegImmOpConstructor.subst(vcmpZeroSIop); 980 exec_output += PredOpExecute.subst(vcmpZeroSIop); 981 982 vcmpZeroDCode = ''' | 976 // This only handles imm == 0 for now. 977 assert(imm == 0); 978 if (FpDest == imm) { 979 fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 980 } else if (FpDest < imm) { 981 fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 982 } else if (FpDest > imm) { 983 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; --- 10 unchanged lines hidden (view full) --- 994 vcmpZeroSIop = InstObjParams("vcmpZeros", "VcmpZeroS", "FpRegImmOp", 995 { "code": vcmpZeroSCode, 996 "predicate_test": predicateTest }, []) 997 header_output += FpRegImmOpDeclare.subst(vcmpZeroSIop); 998 decoder_output += FpRegImmOpConstructor.subst(vcmpZeroSIop); 999 exec_output += PredOpExecute.subst(vcmpZeroSIop); 1000 1001 vcmpZeroDCode = ''' |
983 IntDoubleUnion cDest; | |
984 // This only handles imm == 0 for now. 985 assert(imm == 0); | 1002 // This only handles imm == 0 for now. 1003 assert(imm == 0); |
986 cDest.bits = ((uint64_t)FpDestP0.uw | ((uint64_t)FpDestP1.uw << 32)); 987 vfpFlushToZero(Fpscr, cDest.fp); | 1004 double cDest = dbl(FpDestP0.uw, FpDestP1.uw); |
988 FPSCR fpscr = Fpscr; | 1005 FPSCR fpscr = Fpscr; |
989 if (cDest.fp == imm) { | 1006 vfpFlushToZero(fpscr, cDest); 1007 if (cDest == imm) { |
990 fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; | 1008 fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; |
991 } else if (cDest.fp < imm) { | 1009 } else if (cDest < imm) { |
992 fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; | 1010 fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; |
993 } else if (cDest.fp > imm) { | 1011 } else if (cDest > imm) { |
994 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 995 } else { 996 const uint64_t qnan = ULL(0x7ff8000000000000); | 1012 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 1013 } else { 1014 const uint64_t qnan = ULL(0x7ff8000000000000); |
997 const bool nan = std::isnan(cDest.fp); 998 const bool signal = nan && ((cDest.bits & qnan) != qnan); | 1015 const bool nan = std::isnan(cDest); 1016 const bool signal = nan && ((fpToBits(cDest) & qnan) != qnan); |
999 if (signal) 1000 fpscr.ioc = 1; 1001 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 1002 } 1003 Fpscr = fpscr; 1004 ''' 1005 vcmpZeroDIop = InstObjParams("vcmpZerod", "VcmpZeroD", "FpRegImmOp", 1006 { "code": vcmpZeroDCode, 1007 "predicate_test": predicateTest }, []) 1008 header_output += FpRegImmOpDeclare.subst(vcmpZeroDIop); 1009 decoder_output += FpRegImmOpConstructor.subst(vcmpZeroDIop); 1010 exec_output += PredOpExecute.subst(vcmpZeroDIop); 1011 1012 vcmpeSCode = ''' | 1017 if (signal) 1018 fpscr.ioc = 1; 1019 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 1020 } 1021 Fpscr = fpscr; 1022 ''' 1023 vcmpZeroDIop = InstObjParams("vcmpZerod", "VcmpZeroD", "FpRegImmOp", 1024 { "code": vcmpZeroDCode, 1025 "predicate_test": predicateTest }, []) 1026 header_output += FpRegImmOpDeclare.subst(vcmpZeroDIop); 1027 decoder_output += FpRegImmOpConstructor.subst(vcmpZeroDIop); 1028 exec_output += PredOpExecute.subst(vcmpZeroDIop); 1029 1030 vcmpeSCode = ''' |
1013 vfpFlushToZero(Fpscr, FpDest, FpOp1); | |
1014 FPSCR fpscr = Fpscr; | 1031 FPSCR fpscr = Fpscr; |
1032 vfpFlushToZero(fpscr, FpDest, FpOp1); |
|
1015 if (FpDest == FpOp1) { 1016 fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 1017 } else if (FpDest < FpOp1) { 1018 fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 1019 } else if (FpDest > FpOp1) { 1020 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 1021 } else { 1022 fpscr.ioc = 1; --- 4 unchanged lines hidden (view full) --- 1027 vcmpeSIop = InstObjParams("vcmpes", "VcmpeS", "FpRegRegOp", 1028 { "code": vcmpeSCode, 1029 "predicate_test": predicateTest }, []) 1030 header_output += FpRegRegOpDeclare.subst(vcmpeSIop); 1031 decoder_output += FpRegRegOpConstructor.subst(vcmpeSIop); 1032 exec_output += PredOpExecute.subst(vcmpeSIop); 1033 1034 vcmpeDCode = ''' | 1033 if (FpDest == FpOp1) { 1034 fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 1035 } else if (FpDest < FpOp1) { 1036 fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 1037 } else if (FpDest > FpOp1) { 1038 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 1039 } else { 1040 fpscr.ioc = 1; --- 4 unchanged lines hidden (view full) --- 1045 vcmpeSIop = InstObjParams("vcmpes", "VcmpeS", "FpRegRegOp", 1046 { "code": vcmpeSCode, 1047 "predicate_test": predicateTest }, []) 1048 header_output += FpRegRegOpDeclare.subst(vcmpeSIop); 1049 decoder_output += FpRegRegOpConstructor.subst(vcmpeSIop); 1050 exec_output += PredOpExecute.subst(vcmpeSIop); 1051 1052 vcmpeDCode = ''' |
1035 IntDoubleUnion cOp1, cDest; 1036 cDest.bits = ((uint64_t)FpDestP0.uw | ((uint64_t)FpDestP1.uw << 32)); 1037 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 1038 vfpFlushToZero(Fpscr, cDest.fp, cOp1.fp); | 1053 double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw); 1054 double cDest = dbl(FpDestP0.uw, FpDestP1.uw); |
1039 FPSCR fpscr = Fpscr; | 1055 FPSCR fpscr = Fpscr; |
1040 if (cDest.fp == cOp1.fp) { | 1056 vfpFlushToZero(fpscr, cDest, cOp1); 1057 if (cDest == cOp1) { |
1041 fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; | 1058 fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; |
1042 } else if (cDest.fp < cOp1.fp) { | 1059 } else if (cDest < cOp1) { |
1043 fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; | 1060 fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; |
1044 } else if (cDest.fp > cOp1.fp) { | 1061 } else if (cDest > cOp1) { |
1045 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 1046 } else { 1047 fpscr.ioc = 1; 1048 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 1049 } 1050 Fpscr = fpscr; 1051 ''' 1052 vcmpeDIop = InstObjParams("vcmped", "VcmpeD", "FpRegRegOp", 1053 { "code": vcmpeDCode, 1054 "predicate_test": predicateTest }, []) 1055 header_output += FpRegRegOpDeclare.subst(vcmpeDIop); 1056 decoder_output += FpRegRegOpConstructor.subst(vcmpeDIop); 1057 exec_output += PredOpExecute.subst(vcmpeDIop); 1058 1059 vcmpeZeroSCode = ''' | 1062 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 1063 } else { 1064 fpscr.ioc = 1; 1065 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 1066 } 1067 Fpscr = fpscr; 1068 ''' 1069 vcmpeDIop = InstObjParams("vcmped", "VcmpeD", "FpRegRegOp", 1070 { "code": vcmpeDCode, 1071 "predicate_test": predicateTest }, []) 1072 header_output += FpRegRegOpDeclare.subst(vcmpeDIop); 1073 decoder_output += FpRegRegOpConstructor.subst(vcmpeDIop); 1074 exec_output += PredOpExecute.subst(vcmpeDIop); 1075 1076 vcmpeZeroSCode = ''' |
1060 vfpFlushToZero(Fpscr, FpDest); | |
1061 FPSCR fpscr = Fpscr; | 1077 FPSCR fpscr = Fpscr; |
1078 vfpFlushToZero(fpscr, FpDest); |
|
1062 if (FpDest == imm) { 1063 fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 1064 } else if (FpDest < imm) { 1065 fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 1066 } else if (FpDest > imm) { 1067 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 1068 } else { 1069 fpscr.ioc = 1; --- 4 unchanged lines hidden (view full) --- 1074 vcmpeZeroSIop = InstObjParams("vcmpeZeros", "VcmpeZeroS", "FpRegImmOp", 1075 { "code": vcmpeZeroSCode, 1076 "predicate_test": predicateTest }, []) 1077 header_output += FpRegImmOpDeclare.subst(vcmpeZeroSIop); 1078 decoder_output += FpRegImmOpConstructor.subst(vcmpeZeroSIop); 1079 exec_output += PredOpExecute.subst(vcmpeZeroSIop); 1080 1081 vcmpeZeroDCode = ''' | 1079 if (FpDest == imm) { 1080 fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 1081 } else if (FpDest < imm) { 1082 fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 1083 } else if (FpDest > imm) { 1084 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 1085 } else { 1086 fpscr.ioc = 1; --- 4 unchanged lines hidden (view full) --- 1091 vcmpeZeroSIop = InstObjParams("vcmpeZeros", "VcmpeZeroS", "FpRegImmOp", 1092 { "code": vcmpeZeroSCode, 1093 "predicate_test": predicateTest }, []) 1094 header_output += FpRegImmOpDeclare.subst(vcmpeZeroSIop); 1095 decoder_output += FpRegImmOpConstructor.subst(vcmpeZeroSIop); 1096 exec_output += PredOpExecute.subst(vcmpeZeroSIop); 1097 1098 vcmpeZeroDCode = ''' |
1082 IntDoubleUnion cDest; 1083 cDest.bits = ((uint64_t)FpDestP0.uw | ((uint64_t)FpDestP1.uw << 32)); 1084 vfpFlushToZero(Fpscr, cDest.fp); | 1099 double cDest = dbl(FpDestP0.uw, FpDestP1.uw); |
1085 FPSCR fpscr = Fpscr; | 1100 FPSCR fpscr = Fpscr; |
1086 if (cDest.fp == imm) { | 1101 vfpFlushToZero(fpscr, cDest); 1102 if (cDest == imm) { |
1087 fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; | 1103 fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; |
1088 } else if (cDest.fp < imm) { | 1104 } else if (cDest < imm) { |
1089 fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; | 1105 fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; |
1090 } else if (cDest.fp > imm) { | 1106 } else if (cDest > imm) { |
1091 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 1092 } else { 1093 fpscr.ioc = 1; 1094 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 1095 } 1096 Fpscr = fpscr; 1097 ''' 1098 vcmpeZeroDIop = InstObjParams("vcmpeZerod", "VcmpeZeroD", "FpRegImmOp", --- 6 unchanged lines hidden (view full) --- 1105 1106let {{ 1107 1108 header_output = "" 1109 decoder_output = "" 1110 exec_output = "" 1111 1112 vcvtFpSFixedSCode = ''' | 1107 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 1108 } else { 1109 fpscr.ioc = 1; 1110 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 1111 } 1112 Fpscr = fpscr; 1113 ''' 1114 vcmpeZeroDIop = InstObjParams("vcmpeZerod", "VcmpeZeroD", "FpRegImmOp", --- 6 unchanged lines hidden (view full) --- 1121 1122let {{ 1123 1124 header_output = "" 1125 decoder_output = "" 1126 exec_output = "" 1127 1128 vcvtFpSFixedSCode = ''' |
1113 vfpFlushToZero(Fpscr, FpOp1); 1114 VfpSavedState state = prepVfpFpscr(Fpscr); | 1129 FPSCR fpscr = Fpscr; 1130 vfpFlushToZero(fpscr, FpOp1); 1131 VfpSavedState state = prepFpState(fpscr.rMode); |
1115 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 1116 FpDest.sw = vfpFpSToFixed(FpOp1, true, false, imm); 1117 __asm__ __volatile__("" :: "m" (FpDest.sw)); | 1132 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 1133 FpDest.sw = vfpFpSToFixed(FpOp1, true, false, imm); 1134 __asm__ __volatile__("" :: "m" (FpDest.sw)); |
1118 Fpscr = setVfpFpscr(Fpscr, state); | 1135 finishVfp(fpscr, state); 1136 Fpscr = fpscr; |
1119 ''' 1120 vcvtFpSFixedSIop = InstObjParams("vcvt", "VcvtFpSFixedS", "FpRegRegImmOp", 1121 { "code": vcvtFpSFixedSCode, 1122 "predicate_test": predicateTest }, []) 1123 header_output += FpRegRegImmOpDeclare.subst(vcvtFpSFixedSIop); 1124 decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpSFixedSIop); 1125 exec_output += PredOpExecute.subst(vcvtFpSFixedSIop); 1126 1127 vcvtFpSFixedDCode = ''' | 1137 ''' 1138 vcvtFpSFixedSIop = InstObjParams("vcvt", "VcvtFpSFixedS", "FpRegRegImmOp", 1139 { "code": vcvtFpSFixedSCode, 1140 "predicate_test": predicateTest }, []) 1141 header_output += FpRegRegImmOpDeclare.subst(vcvtFpSFixedSIop); 1142 decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpSFixedSIop); 1143 exec_output += PredOpExecute.subst(vcvtFpSFixedSIop); 1144 1145 vcvtFpSFixedDCode = ''' |
1128 IntDoubleUnion cOp1; 1129 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 1130 vfpFlushToZero(Fpscr, cOp1.fp); 1131 VfpSavedState state = prepVfpFpscr(Fpscr); 1132 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp)); 1133 uint64_t mid = vfpFpDToFixed(cOp1.fp, true, false, imm); | 1146 FPSCR fpscr = Fpscr; 1147 double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw); 1148 vfpFlushToZero(fpscr, cOp1); 1149 VfpSavedState state = prepFpState(fpscr.rMode); 1150 __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); 1151 uint64_t mid = vfpFpDToFixed(cOp1, true, false, imm); |
1134 __asm__ __volatile__("" :: "m" (mid)); | 1152 __asm__ __volatile__("" :: "m" (mid)); |
1135 Fpscr = setVfpFpscr(Fpscr, state); | 1153 finishVfp(fpscr, state); 1154 Fpscr = fpscr; |
1136 FpDestP0.uw = mid; 1137 FpDestP1.uw = mid >> 32; 1138 ''' 1139 vcvtFpSFixedDIop = InstObjParams("vcvt", "VcvtFpSFixedD", "FpRegRegImmOp", 1140 { "code": vcvtFpSFixedDCode, 1141 "predicate_test": predicateTest }, []) 1142 header_output += FpRegRegImmOpDeclare.subst(vcvtFpSFixedDIop); 1143 decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpSFixedDIop); 1144 exec_output += PredOpExecute.subst(vcvtFpSFixedDIop); 1145 1146 vcvtFpUFixedSCode = ''' | 1155 FpDestP0.uw = mid; 1156 FpDestP1.uw = mid >> 32; 1157 ''' 1158 vcvtFpSFixedDIop = InstObjParams("vcvt", "VcvtFpSFixedD", "FpRegRegImmOp", 1159 { "code": vcvtFpSFixedDCode, 1160 "predicate_test": predicateTest }, []) 1161 header_output += FpRegRegImmOpDeclare.subst(vcvtFpSFixedDIop); 1162 decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpSFixedDIop); 1163 exec_output += PredOpExecute.subst(vcvtFpSFixedDIop); 1164 1165 vcvtFpUFixedSCode = ''' |
1147 vfpFlushToZero(Fpscr, FpOp1); 1148 VfpSavedState state = prepVfpFpscr(Fpscr); | 1166 FPSCR fpscr = Fpscr; 1167 vfpFlushToZero(fpscr, FpOp1); 1168 VfpSavedState state = prepFpState(fpscr.rMode); |
1149 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 1150 FpDest.uw = vfpFpSToFixed(FpOp1, false, false, imm); 1151 __asm__ __volatile__("" :: "m" (FpDest.uw)); | 1169 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 1170 FpDest.uw = vfpFpSToFixed(FpOp1, false, false, imm); 1171 __asm__ __volatile__("" :: "m" (FpDest.uw)); |
1152 Fpscr = setVfpFpscr(Fpscr, state); | 1172 finishVfp(fpscr, state); 1173 Fpscr = fpscr; |
1153 ''' 1154 vcvtFpUFixedSIop = InstObjParams("vcvt", "VcvtFpUFixedS", "FpRegRegImmOp", 1155 { "code": vcvtFpUFixedSCode, 1156 "predicate_test": predicateTest }, []) 1157 header_output += FpRegRegImmOpDeclare.subst(vcvtFpUFixedSIop); 1158 decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpUFixedSIop); 1159 exec_output += PredOpExecute.subst(vcvtFpUFixedSIop); 1160 1161 vcvtFpUFixedDCode = ''' | 1174 ''' 1175 vcvtFpUFixedSIop = InstObjParams("vcvt", "VcvtFpUFixedS", "FpRegRegImmOp", 1176 { "code": vcvtFpUFixedSCode, 1177 "predicate_test": predicateTest }, []) 1178 header_output += FpRegRegImmOpDeclare.subst(vcvtFpUFixedSIop); 1179 decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpUFixedSIop); 1180 exec_output += PredOpExecute.subst(vcvtFpUFixedSIop); 1181 1182 vcvtFpUFixedDCode = ''' |
1162 IntDoubleUnion cOp1; 1163 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 1164 vfpFlushToZero(Fpscr, cOp1.fp); 1165 VfpSavedState state = prepVfpFpscr(Fpscr); 1166 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp)); 1167 uint64_t mid = vfpFpDToFixed(cOp1.fp, false, false, imm); | 1183 FPSCR fpscr = Fpscr; 1184 double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw); 1185 vfpFlushToZero(fpscr, cOp1); 1186 VfpSavedState state = prepFpState(fpscr.rMode); 1187 __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); 1188 uint64_t mid = vfpFpDToFixed(cOp1, false, false, imm); |
1168 __asm__ __volatile__("" :: "m" (mid)); | 1189 __asm__ __volatile__("" :: "m" (mid)); |
1169 Fpscr = setVfpFpscr(Fpscr, state); | 1190 finishVfp(fpscr, state); 1191 Fpscr = fpscr; |
1170 FpDestP0.uw = mid; 1171 FpDestP1.uw = mid >> 32; 1172 ''' 1173 vcvtFpUFixedDIop = InstObjParams("vcvt", "VcvtFpUFixedD", "FpRegRegImmOp", 1174 { "code": vcvtFpUFixedDCode, 1175 "predicate_test": predicateTest }, []) 1176 header_output += FpRegRegImmOpDeclare.subst(vcvtFpUFixedDIop); 1177 decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpUFixedDIop); 1178 exec_output += PredOpExecute.subst(vcvtFpUFixedDIop); 1179 1180 vcvtSFixedFpSCode = ''' | 1192 FpDestP0.uw = mid; 1193 FpDestP1.uw = mid >> 32; 1194 ''' 1195 vcvtFpUFixedDIop = InstObjParams("vcvt", "VcvtFpUFixedD", "FpRegRegImmOp", 1196 { "code": vcvtFpUFixedDCode, 1197 "predicate_test": predicateTest }, []) 1198 header_output += FpRegRegImmOpDeclare.subst(vcvtFpUFixedDIop); 1199 decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpUFixedDIop); 1200 exec_output += PredOpExecute.subst(vcvtFpUFixedDIop); 1201 1202 vcvtSFixedFpSCode = ''' |
1181 VfpSavedState state = prepVfpFpscr(Fpscr); | 1203 FPSCR fpscr = Fpscr; 1204 VfpSavedState state = prepFpState(fpscr.rMode); |
1182 __asm__ __volatile__("" : "=m" (FpOp1.sw) : "m" (FpOp1.sw)); 1183 FpDest = vfpSFixedToFpS(Fpscr, FpOp1.sw, false, imm); 1184 __asm__ __volatile__("" :: "m" (FpDest)); | 1205 __asm__ __volatile__("" : "=m" (FpOp1.sw) : "m" (FpOp1.sw)); 1206 FpDest = vfpSFixedToFpS(Fpscr, FpOp1.sw, false, imm); 1207 __asm__ __volatile__("" :: "m" (FpDest)); |
1185 Fpscr = setVfpFpscr(Fpscr, state); | 1208 finishVfp(fpscr, state); 1209 Fpscr = fpscr; |
1186 ''' 1187 vcvtSFixedFpSIop = InstObjParams("vcvt", "VcvtSFixedFpS", "FpRegRegImmOp", 1188 { "code": vcvtSFixedFpSCode, 1189 "predicate_test": predicateTest }, []) 1190 header_output += FpRegRegImmOpDeclare.subst(vcvtSFixedFpSIop); 1191 decoder_output += FpRegRegImmOpConstructor.subst(vcvtSFixedFpSIop); 1192 exec_output += PredOpExecute.subst(vcvtSFixedFpSIop); 1193 1194 vcvtSFixedFpDCode = ''' | 1210 ''' 1211 vcvtSFixedFpSIop = InstObjParams("vcvt", "VcvtSFixedFpS", "FpRegRegImmOp", 1212 { "code": vcvtSFixedFpSCode, 1213 "predicate_test": predicateTest }, []) 1214 header_output += FpRegRegImmOpDeclare.subst(vcvtSFixedFpSIop); 1215 decoder_output += FpRegRegImmOpConstructor.subst(vcvtSFixedFpSIop); 1216 exec_output += PredOpExecute.subst(vcvtSFixedFpSIop); 1217 1218 vcvtSFixedFpDCode = ''' |
1195 IntDoubleUnion cDest; | 1219 FPSCR fpscr = Fpscr; |
1196 uint64_t mid = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); | 1220 uint64_t mid = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); |
1197 VfpSavedState state = prepVfpFpscr(Fpscr); | 1221 VfpSavedState state = prepFpState(fpscr.rMode); |
1198 __asm__ __volatile__("" : "=m" (mid) : "m" (mid)); | 1222 __asm__ __volatile__("" : "=m" (mid) : "m" (mid)); |
1199 cDest.fp = vfpSFixedToFpD(Fpscr, mid, false, imm); 1200 __asm__ __volatile__("" :: "m" (cDest.fp)); 1201 Fpscr = setVfpFpscr(Fpscr, state); 1202 FpDestP0.uw = cDest.bits; 1203 FpDestP1.uw = cDest.bits >> 32; | 1223 double cDest = vfpSFixedToFpD(Fpscr, mid, false, imm); 1224 __asm__ __volatile__("" :: "m" (cDest)); 1225 finishVfp(fpscr, state); 1226 Fpscr = fpscr; 1227 FpDestP0.uw = dblLow(cDest); 1228 FpDestP1.uw = dblHi(cDest); |
1204 ''' 1205 vcvtSFixedFpDIop = InstObjParams("vcvt", "VcvtSFixedFpD", "FpRegRegImmOp", 1206 { "code": vcvtSFixedFpDCode, 1207 "predicate_test": predicateTest }, []) 1208 header_output += FpRegRegImmOpDeclare.subst(vcvtSFixedFpDIop); 1209 decoder_output += FpRegRegImmOpConstructor.subst(vcvtSFixedFpDIop); 1210 exec_output += PredOpExecute.subst(vcvtSFixedFpDIop); 1211 1212 vcvtUFixedFpSCode = ''' | 1229 ''' 1230 vcvtSFixedFpDIop = InstObjParams("vcvt", "VcvtSFixedFpD", "FpRegRegImmOp", 1231 { "code": vcvtSFixedFpDCode, 1232 "predicate_test": predicateTest }, []) 1233 header_output += FpRegRegImmOpDeclare.subst(vcvtSFixedFpDIop); 1234 decoder_output += FpRegRegImmOpConstructor.subst(vcvtSFixedFpDIop); 1235 exec_output += PredOpExecute.subst(vcvtSFixedFpDIop); 1236 1237 vcvtUFixedFpSCode = ''' |
1213 VfpSavedState state = prepVfpFpscr(Fpscr); | 1238 FPSCR fpscr = Fpscr; 1239 VfpSavedState state = prepFpState(fpscr.rMode); |
1214 __asm__ __volatile__("" : "=m" (FpOp1.uw) : "m" (FpOp1.uw)); 1215 FpDest = vfpUFixedToFpS(Fpscr, FpOp1.uw, false, imm); 1216 __asm__ __volatile__("" :: "m" (FpDest)); | 1240 __asm__ __volatile__("" : "=m" (FpOp1.uw) : "m" (FpOp1.uw)); 1241 FpDest = vfpUFixedToFpS(Fpscr, FpOp1.uw, false, imm); 1242 __asm__ __volatile__("" :: "m" (FpDest)); |
1217 Fpscr = setVfpFpscr(Fpscr, state); | 1243 finishVfp(fpscr, state); 1244 Fpscr = fpscr; |
1218 ''' 1219 vcvtUFixedFpSIop = InstObjParams("vcvt", "VcvtUFixedFpS", "FpRegRegImmOp", 1220 { "code": vcvtUFixedFpSCode, 1221 "predicate_test": predicateTest }, []) 1222 header_output += FpRegRegImmOpDeclare.subst(vcvtUFixedFpSIop); 1223 decoder_output += FpRegRegImmOpConstructor.subst(vcvtUFixedFpSIop); 1224 exec_output += PredOpExecute.subst(vcvtUFixedFpSIop); 1225 1226 vcvtUFixedFpDCode = ''' | 1245 ''' 1246 vcvtUFixedFpSIop = InstObjParams("vcvt", "VcvtUFixedFpS", "FpRegRegImmOp", 1247 { "code": vcvtUFixedFpSCode, 1248 "predicate_test": predicateTest }, []) 1249 header_output += FpRegRegImmOpDeclare.subst(vcvtUFixedFpSIop); 1250 decoder_output += FpRegRegImmOpConstructor.subst(vcvtUFixedFpSIop); 1251 exec_output += PredOpExecute.subst(vcvtUFixedFpSIop); 1252 1253 vcvtUFixedFpDCode = ''' |
1227 IntDoubleUnion cDest; | 1254 FPSCR fpscr = Fpscr; |
1228 uint64_t mid = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); | 1255 uint64_t mid = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); |
1229 VfpSavedState state = prepVfpFpscr(Fpscr); | 1256 VfpSavedState state = prepFpState(fpscr.rMode); |
1230 __asm__ __volatile__("" : "=m" (mid) : "m" (mid)); | 1257 __asm__ __volatile__("" : "=m" (mid) : "m" (mid)); |
1231 cDest.fp = vfpUFixedToFpD(Fpscr, mid, false, imm); 1232 __asm__ __volatile__("" :: "m" (cDest.fp)); 1233 Fpscr = setVfpFpscr(Fpscr, state); 1234 FpDestP0.uw = cDest.bits; 1235 FpDestP1.uw = cDest.bits >> 32; | 1258 double cDest = vfpUFixedToFpD(Fpscr, mid, false, imm); 1259 __asm__ __volatile__("" :: "m" (cDest)); 1260 finishVfp(fpscr, state); 1261 Fpscr = fpscr; 1262 FpDestP0.uw = dblLow(cDest); 1263 FpDestP1.uw = dblHi(cDest); |
1236 ''' 1237 vcvtUFixedFpDIop = InstObjParams("vcvt", "VcvtUFixedFpD", "FpRegRegImmOp", 1238 { "code": vcvtUFixedFpDCode, 1239 "predicate_test": predicateTest }, []) 1240 header_output += FpRegRegImmOpDeclare.subst(vcvtUFixedFpDIop); 1241 decoder_output += FpRegRegImmOpConstructor.subst(vcvtUFixedFpDIop); 1242 exec_output += PredOpExecute.subst(vcvtUFixedFpDIop); 1243 1244 vcvtFpSHFixedSCode = ''' | 1264 ''' 1265 vcvtUFixedFpDIop = InstObjParams("vcvt", "VcvtUFixedFpD", "FpRegRegImmOp", 1266 { "code": vcvtUFixedFpDCode, 1267 "predicate_test": predicateTest }, []) 1268 header_output += FpRegRegImmOpDeclare.subst(vcvtUFixedFpDIop); 1269 decoder_output += FpRegRegImmOpConstructor.subst(vcvtUFixedFpDIop); 1270 exec_output += PredOpExecute.subst(vcvtUFixedFpDIop); 1271 1272 vcvtFpSHFixedSCode = ''' |
1245 vfpFlushToZero(Fpscr, FpOp1); 1246 VfpSavedState state = prepVfpFpscr(Fpscr); | 1273 FPSCR fpscr = Fpscr; 1274 vfpFlushToZero(fpscr, FpOp1); 1275 VfpSavedState state = prepFpState(fpscr.rMode); |
1247 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 1248 FpDest.sh = vfpFpSToFixed(FpOp1, true, true, imm); 1249 __asm__ __volatile__("" :: "m" (FpDest.sh)); | 1276 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 1277 FpDest.sh = vfpFpSToFixed(FpOp1, true, true, imm); 1278 __asm__ __volatile__("" :: "m" (FpDest.sh)); |
1250 Fpscr = setVfpFpscr(Fpscr, state); | 1279 finishVfp(fpscr, state); 1280 Fpscr = fpscr; |
1251 ''' 1252 vcvtFpSHFixedSIop = InstObjParams("vcvt", "VcvtFpSHFixedS", 1253 "FpRegRegImmOp", 1254 { "code": vcvtFpSHFixedSCode, 1255 "predicate_test": predicateTest }, []) 1256 header_output += FpRegRegImmOpDeclare.subst(vcvtFpSHFixedSIop); 1257 decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpSHFixedSIop); 1258 exec_output += PredOpExecute.subst(vcvtFpSHFixedSIop); 1259 1260 vcvtFpSHFixedDCode = ''' | 1281 ''' 1282 vcvtFpSHFixedSIop = InstObjParams("vcvt", "VcvtFpSHFixedS", 1283 "FpRegRegImmOp", 1284 { "code": vcvtFpSHFixedSCode, 1285 "predicate_test": predicateTest }, []) 1286 header_output += FpRegRegImmOpDeclare.subst(vcvtFpSHFixedSIop); 1287 decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpSHFixedSIop); 1288 exec_output += PredOpExecute.subst(vcvtFpSHFixedSIop); 1289 1290 vcvtFpSHFixedDCode = ''' |
1261 IntDoubleUnion cOp1; 1262 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 1263 vfpFlushToZero(Fpscr, cOp1.fp); 1264 VfpSavedState state = prepVfpFpscr(Fpscr); 1265 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp)); 1266 uint64_t result = vfpFpDToFixed(cOp1.fp, true, true, imm); | 1291 FPSCR fpscr = Fpscr; 1292 double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw); 1293 vfpFlushToZero(fpscr, cOp1); 1294 VfpSavedState state = prepFpState(fpscr.rMode); 1295 __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); 1296 uint64_t result = vfpFpDToFixed(cOp1, true, true, imm); |
1267 __asm__ __volatile__("" :: "m" (result)); | 1297 __asm__ __volatile__("" :: "m" (result)); |
1268 Fpscr = setVfpFpscr(Fpscr, state); | 1298 finishVfp(fpscr, state); 1299 Fpscr = fpscr; |
1269 FpDestP0.uw = result; 1270 FpDestP1.uw = result >> 32; 1271 ''' 1272 vcvtFpSHFixedDIop = InstObjParams("vcvt", "VcvtFpSHFixedD", 1273 "FpRegRegImmOp", 1274 { "code": vcvtFpSHFixedDCode, 1275 "predicate_test": predicateTest }, []) 1276 header_output += FpRegRegImmOpDeclare.subst(vcvtFpSHFixedDIop); 1277 decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpSHFixedDIop); 1278 exec_output += PredOpExecute.subst(vcvtFpSHFixedDIop); 1279 1280 vcvtFpUHFixedSCode = ''' | 1300 FpDestP0.uw = result; 1301 FpDestP1.uw = result >> 32; 1302 ''' 1303 vcvtFpSHFixedDIop = InstObjParams("vcvt", "VcvtFpSHFixedD", 1304 "FpRegRegImmOp", 1305 { "code": vcvtFpSHFixedDCode, 1306 "predicate_test": predicateTest }, []) 1307 header_output += FpRegRegImmOpDeclare.subst(vcvtFpSHFixedDIop); 1308 decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpSHFixedDIop); 1309 exec_output += PredOpExecute.subst(vcvtFpSHFixedDIop); 1310 1311 vcvtFpUHFixedSCode = ''' |
1281 vfpFlushToZero(Fpscr, FpOp1); 1282 VfpSavedState state = prepVfpFpscr(Fpscr); | 1312 FPSCR fpscr = Fpscr; 1313 vfpFlushToZero(fpscr, FpOp1); 1314 VfpSavedState state = prepFpState(fpscr.rMode); |
1283 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 1284 FpDest.uh = vfpFpSToFixed(FpOp1, false, true, imm); 1285 __asm__ __volatile__("" :: "m" (FpDest.uh)); | 1315 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 1316 FpDest.uh = vfpFpSToFixed(FpOp1, false, true, imm); 1317 __asm__ __volatile__("" :: "m" (FpDest.uh)); |
1286 Fpscr = setVfpFpscr(Fpscr, state); | 1318 finishVfp(fpscr, state); 1319 Fpscr = fpscr; |
1287 ''' 1288 vcvtFpUHFixedSIop = InstObjParams("vcvt", "VcvtFpUHFixedS", 1289 "FpRegRegImmOp", 1290 { "code": vcvtFpUHFixedSCode, 1291 "predicate_test": predicateTest }, []) 1292 header_output += FpRegRegImmOpDeclare.subst(vcvtFpUHFixedSIop); 1293 decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpUHFixedSIop); 1294 exec_output += PredOpExecute.subst(vcvtFpUHFixedSIop); 1295 1296 vcvtFpUHFixedDCode = ''' | 1320 ''' 1321 vcvtFpUHFixedSIop = InstObjParams("vcvt", "VcvtFpUHFixedS", 1322 "FpRegRegImmOp", 1323 { "code": vcvtFpUHFixedSCode, 1324 "predicate_test": predicateTest }, []) 1325 header_output += FpRegRegImmOpDeclare.subst(vcvtFpUHFixedSIop); 1326 decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpUHFixedSIop); 1327 exec_output += PredOpExecute.subst(vcvtFpUHFixedSIop); 1328 1329 vcvtFpUHFixedDCode = ''' |
1297 IntDoubleUnion cOp1; 1298 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 1299 vfpFlushToZero(Fpscr, cOp1.fp); 1300 VfpSavedState state = prepVfpFpscr(Fpscr); 1301 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp)); 1302 uint64_t mid = vfpFpDToFixed(cOp1.fp, false, true, imm); | 1330 FPSCR fpscr = Fpscr; 1331 double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw); 1332 vfpFlushToZero(fpscr, cOp1); 1333 VfpSavedState state = prepFpState(fpscr.rMode); 1334 __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); 1335 uint64_t mid = vfpFpDToFixed(cOp1, false, true, imm); |
1303 __asm__ __volatile__("" :: "m" (mid)); | 1336 __asm__ __volatile__("" :: "m" (mid)); |
1304 Fpscr = setVfpFpscr(Fpscr, state); | 1337 finishVfp(fpscr, state); 1338 Fpscr = fpscr; |
1305 FpDestP0.uw = mid; 1306 FpDestP1.uw = mid >> 32; 1307 ''' 1308 vcvtFpUHFixedDIop = InstObjParams("vcvt", "VcvtFpUHFixedD", 1309 "FpRegRegImmOp", 1310 { "code": vcvtFpUHFixedDCode, 1311 "predicate_test": predicateTest }, []) 1312 header_output += FpRegRegImmOpDeclare.subst(vcvtFpUHFixedDIop); 1313 decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpUHFixedDIop); 1314 exec_output += PredOpExecute.subst(vcvtFpUHFixedDIop); 1315 1316 vcvtSHFixedFpSCode = ''' | 1339 FpDestP0.uw = mid; 1340 FpDestP1.uw = mid >> 32; 1341 ''' 1342 vcvtFpUHFixedDIop = InstObjParams("vcvt", "VcvtFpUHFixedD", 1343 "FpRegRegImmOp", 1344 { "code": vcvtFpUHFixedDCode, 1345 "predicate_test": predicateTest }, []) 1346 header_output += FpRegRegImmOpDeclare.subst(vcvtFpUHFixedDIop); 1347 decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpUHFixedDIop); 1348 exec_output += PredOpExecute.subst(vcvtFpUHFixedDIop); 1349 1350 vcvtSHFixedFpSCode = ''' |
1317 VfpSavedState state = prepVfpFpscr(Fpscr); | 1351 FPSCR fpscr = Fpscr; 1352 VfpSavedState state = prepFpState(fpscr.rMode); |
1318 __asm__ __volatile__("" : "=m" (FpOp1.sh) : "m" (FpOp1.sh)); 1319 FpDest = vfpSFixedToFpS(Fpscr, FpOp1.sh, true, imm); 1320 __asm__ __volatile__("" :: "m" (FpDest)); | 1353 __asm__ __volatile__("" : "=m" (FpOp1.sh) : "m" (FpOp1.sh)); 1354 FpDest = vfpSFixedToFpS(Fpscr, FpOp1.sh, true, imm); 1355 __asm__ __volatile__("" :: "m" (FpDest)); |
1321 Fpscr = setVfpFpscr(Fpscr, state); | 1356 finishVfp(fpscr, state); 1357 Fpscr = fpscr; |
1322 ''' 1323 vcvtSHFixedFpSIop = InstObjParams("vcvt", "VcvtSHFixedFpS", 1324 "FpRegRegImmOp", 1325 { "code": vcvtSHFixedFpSCode, 1326 "predicate_test": predicateTest }, []) 1327 header_output += FpRegRegImmOpDeclare.subst(vcvtSHFixedFpSIop); 1328 decoder_output += FpRegRegImmOpConstructor.subst(vcvtSHFixedFpSIop); 1329 exec_output += PredOpExecute.subst(vcvtSHFixedFpSIop); 1330 1331 vcvtSHFixedFpDCode = ''' | 1358 ''' 1359 vcvtSHFixedFpSIop = InstObjParams("vcvt", "VcvtSHFixedFpS", 1360 "FpRegRegImmOp", 1361 { "code": vcvtSHFixedFpSCode, 1362 "predicate_test": predicateTest }, []) 1363 header_output += FpRegRegImmOpDeclare.subst(vcvtSHFixedFpSIop); 1364 decoder_output += FpRegRegImmOpConstructor.subst(vcvtSHFixedFpSIop); 1365 exec_output += PredOpExecute.subst(vcvtSHFixedFpSIop); 1366 1367 vcvtSHFixedFpDCode = ''' |
1332 IntDoubleUnion cDest; | 1368 FPSCR fpscr = Fpscr; |
1333 uint64_t mid = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); | 1369 uint64_t mid = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); |
1334 VfpSavedState state = prepVfpFpscr(Fpscr); | 1370 VfpSavedState state = prepFpState(fpscr.rMode); |
1335 __asm__ __volatile__("" : "=m" (mid) : "m" (mid)); | 1371 __asm__ __volatile__("" : "=m" (mid) : "m" (mid)); |
1336 cDest.fp = vfpSFixedToFpD(Fpscr, mid, true, imm); 1337 __asm__ __volatile__("" :: "m" (cDest.fp)); 1338 Fpscr = setVfpFpscr(Fpscr, state); 1339 FpDestP0.uw = cDest.bits; 1340 FpDestP1.uw = cDest.bits >> 32; | 1372 double cDest = vfpSFixedToFpD(Fpscr, mid, true, imm); 1373 __asm__ __volatile__("" :: "m" (cDest)); 1374 finishVfp(fpscr, state); 1375 Fpscr = fpscr; 1376 FpDestP0.uw = dblLow(cDest); 1377 FpDestP1.uw = dblHi(cDest); |
1341 ''' 1342 vcvtSHFixedFpDIop = InstObjParams("vcvt", "VcvtSHFixedFpD", 1343 "FpRegRegImmOp", 1344 { "code": vcvtSHFixedFpDCode, 1345 "predicate_test": predicateTest }, []) 1346 header_output += FpRegRegImmOpDeclare.subst(vcvtSHFixedFpDIop); 1347 decoder_output += FpRegRegImmOpConstructor.subst(vcvtSHFixedFpDIop); 1348 exec_output += PredOpExecute.subst(vcvtSHFixedFpDIop); 1349 1350 vcvtUHFixedFpSCode = ''' | 1378 ''' 1379 vcvtSHFixedFpDIop = InstObjParams("vcvt", "VcvtSHFixedFpD", 1380 "FpRegRegImmOp", 1381 { "code": vcvtSHFixedFpDCode, 1382 "predicate_test": predicateTest }, []) 1383 header_output += FpRegRegImmOpDeclare.subst(vcvtSHFixedFpDIop); 1384 decoder_output += FpRegRegImmOpConstructor.subst(vcvtSHFixedFpDIop); 1385 exec_output += PredOpExecute.subst(vcvtSHFixedFpDIop); 1386 1387 vcvtUHFixedFpSCode = ''' |
1351 VfpSavedState state = prepVfpFpscr(Fpscr); | 1388 FPSCR fpscr = Fpscr; 1389 VfpSavedState state = prepFpState(fpscr.rMode); |
1352 __asm__ __volatile__("" : "=m" (FpOp1.uh) : "m" (FpOp1.uh)); 1353 FpDest = vfpUFixedToFpS(Fpscr, FpOp1.uh, true, imm); 1354 __asm__ __volatile__("" :: "m" (FpDest)); | 1390 __asm__ __volatile__("" : "=m" (FpOp1.uh) : "m" (FpOp1.uh)); 1391 FpDest = vfpUFixedToFpS(Fpscr, FpOp1.uh, true, imm); 1392 __asm__ __volatile__("" :: "m" (FpDest)); |
1355 Fpscr = setVfpFpscr(Fpscr, state); | 1393 finishVfp(fpscr, state); 1394 Fpscr = fpscr; |
1356 ''' 1357 vcvtUHFixedFpSIop = InstObjParams("vcvt", "VcvtUHFixedFpS", 1358 "FpRegRegImmOp", 1359 { "code": vcvtUHFixedFpSCode, 1360 "predicate_test": predicateTest }, []) 1361 header_output += FpRegRegImmOpDeclare.subst(vcvtUHFixedFpSIop); 1362 decoder_output += FpRegRegImmOpConstructor.subst(vcvtUHFixedFpSIop); 1363 exec_output += PredOpExecute.subst(vcvtUHFixedFpSIop); 1364 1365 vcvtUHFixedFpDCode = ''' | 1395 ''' 1396 vcvtUHFixedFpSIop = InstObjParams("vcvt", "VcvtUHFixedFpS", 1397 "FpRegRegImmOp", 1398 { "code": vcvtUHFixedFpSCode, 1399 "predicate_test": predicateTest }, []) 1400 header_output += FpRegRegImmOpDeclare.subst(vcvtUHFixedFpSIop); 1401 decoder_output += FpRegRegImmOpConstructor.subst(vcvtUHFixedFpSIop); 1402 exec_output += PredOpExecute.subst(vcvtUHFixedFpSIop); 1403 1404 vcvtUHFixedFpDCode = ''' |
1366 IntDoubleUnion cDest; | 1405 FPSCR fpscr = Fpscr; |
1367 uint64_t mid = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); | 1406 uint64_t mid = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); |
1368 VfpSavedState state = prepVfpFpscr(Fpscr); | 1407 VfpSavedState state = prepFpState(fpscr.rMode); |
1369 __asm__ __volatile__("" : "=m" (mid) : "m" (mid)); | 1408 __asm__ __volatile__("" : "=m" (mid) : "m" (mid)); |
1370 cDest.fp = vfpUFixedToFpD(Fpscr, mid, true, imm); 1371 __asm__ __volatile__("" :: "m" (cDest.fp)); 1372 Fpscr = setVfpFpscr(Fpscr, state); 1373 FpDestP0.uw = cDest.bits; 1374 FpDestP1.uw = cDest.bits >> 32; | 1409 double cDest = vfpUFixedToFpD(Fpscr, mid, true, imm); 1410 __asm__ __volatile__("" :: "m" (cDest)); 1411 finishVfp(fpscr, state); 1412 Fpscr = fpscr; 1413 FpDestP0.uw = dblLow(cDest); 1414 FpDestP1.uw = dblHi(cDest); |
1375 ''' 1376 vcvtUHFixedFpDIop = InstObjParams("vcvt", "VcvtUHFixedFpD", 1377 "FpRegRegImmOp", 1378 { "code": vcvtUHFixedFpDCode, 1379 "predicate_test": predicateTest }, []) 1380 header_output += FpRegRegImmOpDeclare.subst(vcvtUHFixedFpDIop); 1381 decoder_output += FpRegRegImmOpConstructor.subst(vcvtUHFixedFpDIop); 1382 exec_output += PredOpExecute.subst(vcvtUHFixedFpDIop); 1383}}; | 1415 ''' 1416 vcvtUHFixedFpDIop = InstObjParams("vcvt", "VcvtUHFixedFpD", 1417 "FpRegRegImmOp", 1418 { "code": vcvtUHFixedFpDCode, 1419 "predicate_test": predicateTest }, []) 1420 header_output += FpRegRegImmOpDeclare.subst(vcvtUHFixedFpDIop); 1421 decoder_output += FpRegRegImmOpConstructor.subst(vcvtUHFixedFpDIop); 1422 exec_output += PredOpExecute.subst(vcvtUHFixedFpDIop); 1423}}; |