Cross Reference: /gem5/src/arch/arm/isa/insts/fp.isa

1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 177 unchanged lines hidden (view full) ---

186}};
187
188let {{
189
190 header_output = ""
191 decoder_output = ""
192 exec_output = ""
193

194 vmsrIop = InstObjParams("vmsr", "Vmsr", "VfpRegRegOp",

194 vmsrIop = InstObjParams("vmsr", "Vmsr", "FpRegRegOp",

195 { "code": "MiscDest = Op1;",
196 "predicate_test": predicateTest }, [])

197 header_output += VfpRegRegOpDeclare.subst(vmsrIop);
198 decoder_output += VfpRegRegOpConstructor.subst(vmsrIop);

197 header_output += FpRegRegOpDeclare.subst(vmsrIop);
198 decoder_output += FpRegRegOpConstructor.subst(vmsrIop);

199 exec_output += PredOpExecute.subst(vmsrIop);
200

201 vmrsIop = InstObjParams("vmrs", "Vmrs", "VfpRegRegOp",

201 vmrsIop = InstObjParams("vmrs", "Vmrs", "FpRegRegOp",

202 { "code": "Dest = MiscOp1;",
203 "predicate_test": predicateTest }, [])

204 header_output += VfpRegRegOpDeclare.subst(vmrsIop);
205 decoder_output += VfpRegRegOpConstructor.subst(vmrsIop);

204 header_output += FpRegRegOpDeclare.subst(vmrsIop);
205 decoder_output += FpRegRegOpConstructor.subst(vmrsIop);

206 exec_output += PredOpExecute.subst(vmrsIop);
207
208 vmrsApsrCode = "Dest = (MiscOp1 & imm) | (Dest & ~imm);"

209 vmrsApsrIop = InstObjParams("vmrs", "VmrsApsr", "VfpRegRegImmOp",

209 vmrsApsrIop = InstObjParams("vmrs", "VmrsApsr", "FpRegRegImmOp",

210 { "code": vmrsApsrCode,
211 "predicate_test": predicateTest }, [])

212 header_output += VfpRegRegImmOpDeclare.subst(vmrsApsrIop);
213 decoder_output += VfpRegRegImmOpConstructor.subst(vmrsApsrIop);

212 header_output += FpRegRegImmOpDeclare.subst(vmrsApsrIop);
213 decoder_output += FpRegRegImmOpConstructor.subst(vmrsApsrIop);

214 exec_output += PredOpExecute.subst(vmrsApsrIop);
215
216 vmovImmSCode = '''
217 FpDest.uw = bits(imm, 31, 0);
218 '''

219 vmovImmSIop = InstObjParams("vmov", "VmovImmS", "VfpRegImmOp",

219 vmovImmSIop = InstObjParams("vmov", "VmovImmS", "FpRegImmOp",

220 { "code": vmovImmSCode,
221 "predicate_test": predicateTest }, [])

222 header_output += VfpRegImmOpDeclare.subst(vmovImmSIop);
223 decoder_output += VfpRegImmOpConstructor.subst(vmovImmSIop);

222 header_output += FpRegImmOpDeclare.subst(vmovImmSIop);
223 decoder_output += FpRegImmOpConstructor.subst(vmovImmSIop);

224 exec_output += PredOpExecute.subst(vmovImmSIop);
225
226 vmovImmDCode = '''
227 FpDestP0.uw = bits(imm, 31, 0);
228 FpDestP1.uw = bits(imm, 63, 32);
229 '''

230 vmovImmDIop = InstObjParams("vmov", "VmovImmD", "VfpRegImmOp",

230 vmovImmDIop = InstObjParams("vmov", "VmovImmD", "FpRegImmOp",

231 { "code": vmovImmDCode,
232 "predicate_test": predicateTest }, [])

233 header_output += VfpRegImmOpDeclare.subst(vmovImmDIop);
234 decoder_output += VfpRegImmOpConstructor.subst(vmovImmDIop);

233 header_output += FpRegImmOpDeclare.subst(vmovImmDIop);
234 decoder_output += FpRegImmOpConstructor.subst(vmovImmDIop);

235 exec_output += PredOpExecute.subst(vmovImmDIop);
236
237 vmovImmQCode = '''
238 FpDestP0.uw = bits(imm, 31, 0);
239 FpDestP1.uw = bits(imm, 63, 32);
240 FpDestP2.uw = bits(imm, 31, 0);
241 FpDestP3.uw = bits(imm, 63, 32);
242 '''

243 vmovImmQIop = InstObjParams("vmov", "VmovImmQ", "VfpRegImmOp",

243 vmovImmQIop = InstObjParams("vmov", "VmovImmQ", "FpRegImmOp",

244 { "code": vmovImmQCode,
245 "predicate_test": predicateTest }, [])

246 header_output += VfpRegImmOpDeclare.subst(vmovImmQIop);
247 decoder_output += VfpRegImmOpConstructor.subst(vmovImmQIop);

246 header_output += FpRegImmOpDeclare.subst(vmovImmQIop);
247 decoder_output += FpRegImmOpConstructor.subst(vmovImmQIop);

248 exec_output += PredOpExecute.subst(vmovImmQIop);
249
250 vmovRegSCode = '''
251 FpDest.uw = FpOp1.uw;
252 '''

253 vmovRegSIop = InstObjParams("vmov", "VmovRegS", "VfpRegRegOp",

253 vmovRegSIop = InstObjParams("vmov", "VmovRegS", "FpRegRegOp",

254 { "code": vmovRegSCode,
255 "predicate_test": predicateTest }, [])

256 header_output += VfpRegRegOpDeclare.subst(vmovRegSIop);
257 decoder_output += VfpRegRegOpConstructor.subst(vmovRegSIop);

256 header_output += FpRegRegOpDeclare.subst(vmovRegSIop);
257 decoder_output += FpRegRegOpConstructor.subst(vmovRegSIop);

258 exec_output += PredOpExecute.subst(vmovRegSIop);
259
260 vmovRegDCode = '''
261 FpDestP0.uw = FpOp1P0.uw;
262 FpDestP1.uw = FpOp1P1.uw;
263 '''

264 vmovRegDIop = InstObjParams("vmov", "VmovRegD", "VfpRegRegOp",

264 vmovRegDIop = InstObjParams("vmov", "VmovRegD", "FpRegRegOp",

265 { "code": vmovRegDCode,
266 "predicate_test": predicateTest }, [])

267 header_output += VfpRegRegOpDeclare.subst(vmovRegDIop);
268 decoder_output += VfpRegRegOpConstructor.subst(vmovRegDIop);

267 header_output += FpRegRegOpDeclare.subst(vmovRegDIop);
268 decoder_output += FpRegRegOpConstructor.subst(vmovRegDIop);

269 exec_output += PredOpExecute.subst(vmovRegDIop);
270
271 vmovRegQCode = '''
272 FpDestP0.uw = FpOp1P0.uw;
273 FpDestP1.uw = FpOp1P1.uw;
274 FpDestP2.uw = FpOp1P2.uw;
275 FpDestP3.uw = FpOp1P3.uw;
276 '''

277 vmovRegQIop = InstObjParams("vmov", "VmovRegQ", "VfpRegRegOp",

277 vmovRegQIop = InstObjParams("vmov", "VmovRegQ", "FpRegRegOp",

278 { "code": vmovRegQCode,
279 "predicate_test": predicateTest }, [])

280 header_output += VfpRegRegOpDeclare.subst(vmovRegQIop);
281 decoder_output += VfpRegRegOpConstructor.subst(vmovRegQIop);

280 header_output += FpRegRegOpDeclare.subst(vmovRegQIop);
281 decoder_output += FpRegRegOpConstructor.subst(vmovRegQIop);

282 exec_output += PredOpExecute.subst(vmovRegQIop);
283
284 vmovCoreRegBCode = '''
285 FpDest.uw = insertBits(FpDest.uw, imm * 8, imm * 8 + 7, Op1.ub);
286 '''

287 vmovCoreRegBIop = InstObjParams("vmov", "VmovCoreRegB", "VfpRegRegImmOp",

287 vmovCoreRegBIop = InstObjParams("vmov", "VmovCoreRegB", "FpRegRegImmOp",

288 { "code": vmovCoreRegBCode,
289 "predicate_test": predicateTest }, [])

290 header_output += VfpRegRegImmOpDeclare.subst(vmovCoreRegBIop);
291 decoder_output += VfpRegRegImmOpConstructor.subst(vmovCoreRegBIop);

290 header_output += FpRegRegImmOpDeclare.subst(vmovCoreRegBIop);
291 decoder_output += FpRegRegImmOpConstructor.subst(vmovCoreRegBIop);

292 exec_output += PredOpExecute.subst(vmovCoreRegBIop);
293
294 vmovCoreRegHCode = '''
295 FpDest.uw = insertBits(FpDest.uw, imm * 16, imm * 16 + 15, Op1.uh);
296 '''

297 vmovCoreRegHIop = InstObjParams("vmov", "VmovCoreRegH", "VfpRegRegImmOp",

297 vmovCoreRegHIop = InstObjParams("vmov", "VmovCoreRegH", "FpRegRegImmOp",

298 { "code": vmovCoreRegHCode,
299 "predicate_test": predicateTest }, [])

300 header_output += VfpRegRegImmOpDeclare.subst(vmovCoreRegHIop);
301 decoder_output += VfpRegRegImmOpConstructor.subst(vmovCoreRegHIop);

300 header_output += FpRegRegImmOpDeclare.subst(vmovCoreRegHIop);
301 decoder_output += FpRegRegImmOpConstructor.subst(vmovCoreRegHIop);

302 exec_output += PredOpExecute.subst(vmovCoreRegHIop);
303
304 vmovCoreRegWCode = '''
305 FpDest.uw = Op1.uw;
306 '''

307 vmovCoreRegWIop = InstObjParams("vmov", "VmovCoreRegW", "VfpRegRegOp",

307 vmovCoreRegWIop = InstObjParams("vmov", "VmovCoreRegW", "FpRegRegOp",

308 { "code": vmovCoreRegWCode,
309 "predicate_test": predicateTest }, [])

310 header_output += VfpRegRegOpDeclare.subst(vmovCoreRegWIop);
311 decoder_output += VfpRegRegOpConstructor.subst(vmovCoreRegWIop);

310 header_output += FpRegRegOpDeclare.subst(vmovCoreRegWIop);
311 decoder_output += FpRegRegOpConstructor.subst(vmovCoreRegWIop);

312 exec_output += PredOpExecute.subst(vmovCoreRegWIop);
313
314 vmovRegCoreUBCode = '''
315 Dest = bits(FpOp1.uw, imm * 8, imm * 8 + 7);
316 '''

317 vmovRegCoreUBIop = InstObjParams("vmov", "VmovRegCoreUB", "VfpRegRegImmOp",

317 vmovRegCoreUBIop = InstObjParams("vmov", "VmovRegCoreUB", "FpRegRegImmOp",

318 { "code": vmovRegCoreUBCode,
319 "predicate_test": predicateTest }, [])

320 header_output += VfpRegRegImmOpDeclare.subst(vmovRegCoreUBIop);
321 decoder_output += VfpRegRegImmOpConstructor.subst(vmovRegCoreUBIop);

320 header_output += FpRegRegImmOpDeclare.subst(vmovRegCoreUBIop);
321 decoder_output += FpRegRegImmOpConstructor.subst(vmovRegCoreUBIop);

322 exec_output += PredOpExecute.subst(vmovRegCoreUBIop);
323
324 vmovRegCoreUHCode = '''
325 Dest = bits(FpOp1.uw, imm * 16, imm * 16 + 15);
326 '''

327 vmovRegCoreUHIop = InstObjParams("vmov", "VmovRegCoreUH", "VfpRegRegImmOp",

327 vmovRegCoreUHIop = InstObjParams("vmov", "VmovRegCoreUH", "FpRegRegImmOp",

328 { "code": vmovRegCoreUHCode,
329 "predicate_test": predicateTest }, [])

330 header_output += VfpRegRegImmOpDeclare.subst(vmovRegCoreUHIop);
331 decoder_output += VfpRegRegImmOpConstructor.subst(vmovRegCoreUHIop);

330 header_output += FpRegRegImmOpDeclare.subst(vmovRegCoreUHIop);
331 decoder_output += FpRegRegImmOpConstructor.subst(vmovRegCoreUHIop);

332 exec_output += PredOpExecute.subst(vmovRegCoreUHIop);
333
334 vmovRegCoreSBCode = '''
335 Dest = sext<8>(bits(FpOp1.uw, imm * 8, imm * 8 + 7));
336 '''

337 vmovRegCoreSBIop = InstObjParams("vmov", "VmovRegCoreSB", "VfpRegRegImmOp",

337 vmovRegCoreSBIop = InstObjParams("vmov", "VmovRegCoreSB", "FpRegRegImmOp",

338 { "code": vmovRegCoreSBCode,
339 "predicate_test": predicateTest }, [])

340 header_output += VfpRegRegImmOpDeclare.subst(vmovRegCoreSBIop);
341 decoder_output += VfpRegRegImmOpConstructor.subst(vmovRegCoreSBIop);

340 header_output += FpRegRegImmOpDeclare.subst(vmovRegCoreSBIop);
341 decoder_output += FpRegRegImmOpConstructor.subst(vmovRegCoreSBIop);

342 exec_output += PredOpExecute.subst(vmovRegCoreSBIop);
343
344 vmovRegCoreSHCode = '''
345 Dest = sext<16>(bits(FpOp1.uw, imm * 16, imm * 16 + 15));
346 '''

347 vmovRegCoreSHIop = InstObjParams("vmov", "VmovRegCoreSH", "VfpRegRegImmOp",

347 vmovRegCoreSHIop = InstObjParams("vmov", "VmovRegCoreSH", "FpRegRegImmOp",

348 { "code": vmovRegCoreSHCode,
349 "predicate_test": predicateTest }, [])

350 header_output += VfpRegRegImmOpDeclare.subst(vmovRegCoreSHIop);
351 decoder_output += VfpRegRegImmOpConstructor.subst(vmovRegCoreSHIop);

350 header_output += FpRegRegImmOpDeclare.subst(vmovRegCoreSHIop);
351 decoder_output += FpRegRegImmOpConstructor.subst(vmovRegCoreSHIop);

352 exec_output += PredOpExecute.subst(vmovRegCoreSHIop);
353
354 vmovRegCoreWCode = '''
355 Dest = FpOp1.uw;
356 '''

357 vmovRegCoreWIop = InstObjParams("vmov", "VmovRegCoreW", "VfpRegRegOp",

357 vmovRegCoreWIop = InstObjParams("vmov", "VmovRegCoreW", "FpRegRegOp",

358 { "code": vmovRegCoreWCode,
359 "predicate_test": predicateTest }, [])

360 header_output += VfpRegRegOpDeclare.subst(vmovRegCoreWIop);
361 decoder_output += VfpRegRegOpConstructor.subst(vmovRegCoreWIop);

360 header_output += FpRegRegOpDeclare.subst(vmovRegCoreWIop);
361 decoder_output += FpRegRegOpConstructor.subst(vmovRegCoreWIop);

362 exec_output += PredOpExecute.subst(vmovRegCoreWIop);
363
364 vmov2Reg2CoreCode = '''
365 FpDestP0.uw = Op1.uw;
366 FpDestP1.uw = Op2.uw;
367 '''

368 vmov2Reg2CoreIop = InstObjParams("vmov", "Vmov2Reg2Core", "VfpRegRegRegOp",

368 vmov2Reg2CoreIop = InstObjParams("vmov", "Vmov2Reg2Core", "FpRegRegRegOp",

369 { "code": vmov2Reg2CoreCode,
370 "predicate_test": predicateTest }, [])

371 header_output += VfpRegRegRegOpDeclare.subst(vmov2Reg2CoreIop);
372 decoder_output += VfpRegRegRegOpConstructor.subst(vmov2Reg2CoreIop);

371 header_output += FpRegRegRegOpDeclare.subst(vmov2Reg2CoreIop);
372 decoder_output += FpRegRegRegOpConstructor.subst(vmov2Reg2CoreIop);

373 exec_output += PredOpExecute.subst(vmov2Reg2CoreIop);
374
375 vmov2Core2RegCode = '''
376 Dest.uw = FpOp2P0.uw;
377 Op1.uw = FpOp2P1.uw;
378 '''

379 vmov2Core2RegIop = InstObjParams("vmov", "Vmov2Core2Reg", "VfpRegRegRegOp",

379 vmov2Core2RegIop = InstObjParams("vmov", "Vmov2Core2Reg", "FpRegRegRegOp",

380 { "code": vmov2Core2RegCode,
381 "predicate_test": predicateTest }, [])

382 header_output += VfpRegRegRegOpDeclare.subst(vmov2Core2RegIop);
383 decoder_output += VfpRegRegRegOpConstructor.subst(vmov2Core2RegIop);

382 header_output += FpRegRegRegOpDeclare.subst(vmov2Core2RegIop);
383 decoder_output += FpRegRegRegOpConstructor.subst(vmov2Core2RegIop);

384 exec_output += PredOpExecute.subst(vmov2Core2RegIop);
385}};
386
387let {{
388
389 header_output = ""
390 decoder_output = ""
391 exec_output = ""
392

393 vmulSCode = '''
394 vfpFlushToZero(Fpscr, FpOp1, FpOp2);
395 VfpSavedState state = prepVfpFpscr(Fpscr);
396 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
397 FpDest = fixMultDest(Fpscr, FpOp1 * FpOp2, FpOp1, FpOp2);
398 __asm__ __volatile__("" :: "m" (FpDest));
399 Fpscr = setVfpFpscr(Fpscr, state);
400 if ((isinf(FpOp1) && FpOp2 == 0) || (isinf(FpOp2) && FpOp1 == 0)) {
401 FpDest = NAN;
402 }

393 singleCode = '''
394 FPSCR fpscr = Fpscr;
395 FpDest = %(op)s;
396 Fpscr = fpscr;

403 '''

397 '''

404 vmulSIop = InstObjParams("vmuls", "VmulS", "VfpRegRegRegOp",
405 { "code": vmulSCode,
406 "predicate_test": predicateTest }, [])
407 header_output += VfpRegRegRegOpDeclare.subst(vmulSIop);
408 decoder_output += VfpRegRegRegOpConstructor.subst(vmulSIop);
409 exec_output += PredOpExecute.subst(vmulSIop);
410
411 vmulDCode = '''
412 IntDoubleUnion cOp1, cOp2, cDest;
413 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
414 cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32));
415 vfpFlushToZero(Fpscr, cOp1.fp, cOp2.fp);
416 VfpSavedState state = prepVfpFpscr(Fpscr);
417 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp));
418 cDest.fp = fixMultDest(Fpscr, cOp1.fp * cOp2.fp, cOp1.fp, cOp2.fp);
419 __asm__ __volatile__("" :: "m" (cDest.fp));
420 Fpscr = setVfpFpscr(Fpscr, state);
421 if ((isinf(cOp1.fp) && cOp2.fp == 0) ||
422 (isinf(cOp2.fp) && cOp1.fp == 0)) {
423 cDest.fp = NAN;
424 }
425 FpDestP0.uw = cDest.bits;
426 FpDestP1.uw = cDest.bits >> 32;

398 singleBinOp = "binaryOp(fpscr, FpOp1, FpOp2," + \
399 "%(func)s, fpscr.fz, fpscr.rMode)"
400 singleUnaryOp = "unaryOp(fpscr, FpOp1, %(func)s, fpscr.fz, fpscr.rMode)"
401 doubleCode = '''
402 FPSCR fpscr = Fpscr;
403 double dest = %(op)s;
404 Fpscr = fpscr;
405 FpDestP0.uw = dblLow(dest);
406 FpDestP1.uw = dblHi(dest);

427 '''

407 '''

428 vmulDIop = InstObjParams("vmuld", "VmulD", "VfpRegRegRegOp",
429 { "code": vmulDCode,
430 "predicate_test": predicateTest }, [])
431 header_output += VfpRegRegRegOpDeclare.subst(vmulDIop);
432 decoder_output += VfpRegRegRegOpConstructor.subst(vmulDIop);
433 exec_output += PredOpExecute.subst(vmulDIop);
434
435 vnegSCode = '''
436 FpDest = -FpOp1;

408 doubleBinOp = '''
409 binaryOp(fpscr, dbl(FpOp1P0.uw, FpOp1P1.uw),
410 dbl(FpOp2P0.uw, FpOp2P1.uw),
411 %(func)s, fpscr.fz, fpscr.rMode);

437 '''

412 '''

438 vnegSIop = InstObjParams("vnegs", "VnegS", "VfpRegRegOp",
439 { "code": vnegSCode,
440 "predicate_test": predicateTest }, [])
441 header_output += VfpRegRegOpDeclare.subst(vnegSIop);
442 decoder_output += VfpRegRegOpConstructor.subst(vnegSIop);
443 exec_output += PredOpExecute.subst(vnegSIop);
444
445 vnegDCode = '''
446 IntDoubleUnion cOp1, cDest;
447 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
448 cDest.fp = -cOp1.fp;
449 FpDestP0.uw = cDest.bits;
450 FpDestP1.uw = cDest.bits >> 32;

413 doubleUnaryOp = '''
414 unaryOp(fpscr, dbl(FpOp1P0.uw, FpOp1P1.uw), %(func)s,
415 fpscr.fz, fpscr.rMode)

451 '''

416 '''

452 vnegDIop = InstObjParams("vnegd", "VnegD", "VfpRegRegOp",
453 { "code": vnegDCode,
454 "predicate_test": predicateTest }, [])
455 header_output += VfpRegRegOpDeclare.subst(vnegDIop);
456 decoder_output += VfpRegRegOpConstructor.subst(vnegDIop);
457 exec_output += PredOpExecute.subst(vnegDIop);

458

417

459 vabsSCode = '''
460 FpDest = fabsf(FpOp1);
461 '''
462 vabsSIop = InstObjParams("vabss", "VabsS", "VfpRegRegOp",
463 { "code": vabsSCode,
464 "predicate_test": predicateTest }, [])
465 header_output += VfpRegRegOpDeclare.subst(vabsSIop);
466 decoder_output += VfpRegRegOpConstructor.subst(vabsSIop);
467 exec_output += PredOpExecute.subst(vabsSIop);

418 def buildBinFpOp(name, Name, base, singleOp, doubleOp):
419 global header_output, decoder_output, exec_output

468

420

469 vabsDCode = '''
470 IntDoubleUnion cOp1, cDest;
471 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
472 cDest.fp = fabs(cOp1.fp);
473 FpDestP0.uw = cDest.bits;
474 FpDestP1.uw = cDest.bits >> 32;
475 '''
476 vabsDIop = InstObjParams("vabsd", "VabsD", "VfpRegRegOp",
477 { "code": vabsDCode,
478 "predicate_test": predicateTest }, [])
479 header_output += VfpRegRegOpDeclare.subst(vabsDIop);
480 decoder_output += VfpRegRegOpConstructor.subst(vabsDIop);
481 exec_output += PredOpExecute.subst(vabsDIop);

421 code = singleCode % { "op": singleBinOp }
422 code = code % { "func": singleOp }
423 sIop = InstObjParams(name + "s", Name + "S", base,
424 { "code": code, "predicate_test": predicateTest }, [])
425 code = doubleCode % { "op": doubleBinOp }
426 code = code % { "func": doubleOp }
427 dIop = InstObjParams(name + "d", Name + "D", base,
428 { "code": code, "predicate_test": predicateTest }, [])

482

429

483 vaddSCode = '''
484 vfpFlushToZero(Fpscr, FpOp1, FpOp2);
485 VfpSavedState state = prepVfpFpscr(Fpscr);
486 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
487 FpDest = fixDest(Fpscr, FpOp1 + FpOp2, FpOp1, FpOp2);
488 __asm__ __volatile__("" :: "m" (FpDest));
489 Fpscr = setVfpFpscr(Fpscr, state);
490 '''
491 vaddSIop = InstObjParams("vadds", "VaddS", "VfpRegRegRegOp",
492 { "code": vaddSCode,
493 "predicate_test": predicateTest }, [])
494 header_output += VfpRegRegRegOpDeclare.subst(vaddSIop);
495 decoder_output += VfpRegRegRegOpConstructor.subst(vaddSIop);
496 exec_output += PredOpExecute.subst(vaddSIop);

430 declareTempl = eval(base + "Declare");
431 constructorTempl = eval(base + "Constructor");

497

432

498 vaddDCode = '''
499 IntDoubleUnion cOp1, cOp2, cDest;
500 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
501 cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32));
502 DPRINTFN("cOp1.bits = %#x, cOp1.fp = %f.\\n", cOp1.bits, cOp1.fp);
503 DPRINTFN("cOp2.bits = %#x, cOp2.fp = %f.\\n", cOp2.bits, cOp2.fp);
504 vfpFlushToZero(Fpscr, cOp1.fp, cOp2.fp);
505 VfpSavedState state = prepVfpFpscr(Fpscr);
506 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp));
507 cDest.fp = fixDest(Fpscr, cOp1.fp + cOp2.fp, cOp1.fp, cOp2.fp);
508 DPRINTFN("cDest.bits = %#x, cDest.fp = %f.\\n", cDest.bits, cDest.fp);
509 __asm__ __volatile__("" :: "m" (cDest.fp));
510 Fpscr = setVfpFpscr(Fpscr, state);
511 FpDestP0.uw = cDest.bits;
512 FpDestP1.uw = cDest.bits >> 32;
513 '''
514 vaddDIop = InstObjParams("vaddd", "VaddD", "VfpRegRegRegOp",
515 { "code": vaddDCode,
516 "predicate_test": predicateTest }, [])
517 header_output += VfpRegRegRegOpDeclare.subst(vaddDIop);
518 decoder_output += VfpRegRegRegOpConstructor.subst(vaddDIop);
519 exec_output += PredOpExecute.subst(vaddDIop);

433 for iop in sIop, dIop:
434 header_output += declareTempl.subst(iop)
435 decoder_output += constructorTempl.subst(iop)
436 exec_output += PredOpExecute.subst(iop)

520

437

521 vsubSCode = '''
522 vfpFlushToZero(Fpscr, FpOp1, FpOp2);
523 VfpSavedState state = prepVfpFpscr(Fpscr);
524 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
525 FpDest = fixDest(Fpscr, FpOp1 - FpOp2, FpOp1, FpOp2);
526 __asm__ __volatile__("" :: "m" (FpDest));
527 Fpscr = setVfpFpscr(Fpscr, state)
528 '''
529 vsubSIop = InstObjParams("vsubs", "VsubS", "VfpRegRegRegOp",
530 { "code": vsubSCode,
531 "predicate_test": predicateTest }, [])
532 header_output += VfpRegRegRegOpDeclare.subst(vsubSIop);
533 decoder_output += VfpRegRegRegOpConstructor.subst(vsubSIop);
534 exec_output += PredOpExecute.subst(vsubSIop);

438 buildBinFpOp("vadd", "Vadd", "FpRegRegRegOp", "fpAddS", "fpAddD")
439 buildBinFpOp("vsub", "Vsub", "FpRegRegRegOp", "fpSubS", "fpSubD")
440 buildBinFpOp("vdiv", "Vdiv", "FpRegRegRegOp", "fpDivS", "fpDivD")
441 buildBinFpOp("vmul", "Vmul", "FpRegRegRegOp", "fpMulS", "fpMulD")

535

442

536 vsubDCode = '''
537 IntDoubleUnion cOp1, cOp2, cDest;
538 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
539 cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32));
540 vfpFlushToZero(Fpscr, cOp1.fp, cOp2.fp);
541 VfpSavedState state = prepVfpFpscr(Fpscr);
542 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp));
543 cDest.fp = fixDest(Fpscr, cOp1.fp - cOp2.fp, cOp1.fp, cOp2.fp);
544 __asm__ __volatile__("" :: "m" (cDest.fp));
545 Fpscr = setVfpFpscr(Fpscr, state);
546 FpDestP0.uw = cDest.bits;
547 FpDestP1.uw = cDest.bits >> 32;
548 '''
549 vsubDIop = InstObjParams("vsubd", "VsubD", "VfpRegRegRegOp",
550 { "code": vsubDCode,
551 "predicate_test": predicateTest }, [])
552 header_output += VfpRegRegRegOpDeclare.subst(vsubDIop);
553 decoder_output += VfpRegRegRegOpConstructor.subst(vsubDIop);
554 exec_output += PredOpExecute.subst(vsubDIop);

443 def buildUnaryFpOp(name, Name, base, singleOp, doubleOp = None):
444 if doubleOp is None:
445 doubleOp = singleOp
446 global header_output, decoder_output, exec_output

555

447

556 vdivSCode = '''
557 vfpFlushToZero(Fpscr, FpOp1, FpOp2);
558 VfpSavedState state = prepVfpFpscr(Fpscr);
559 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
560 FpDest = fixDest(Fpscr, FpOp1 / FpOp2, FpOp1, FpOp2);
561 __asm__ __volatile__("" :: "m" (FpDest));
562 Fpscr = setVfpFpscr(Fpscr, state);
563 '''
564 vdivSIop = InstObjParams("vdivs", "VdivS", "VfpRegRegRegOp",
565 { "code": vdivSCode,
566 "predicate_test": predicateTest }, [])
567 header_output += VfpRegRegRegOpDeclare.subst(vdivSIop);
568 decoder_output += VfpRegRegRegOpConstructor.subst(vdivSIop);
569 exec_output += PredOpExecute.subst(vdivSIop);

448 code = singleCode % { "op": singleUnaryOp }
449 code = code % { "func": singleOp }
450 sIop = InstObjParams(name + "s", Name + "S", base,
451 { "code": code, "predicate_test": predicateTest }, [])
452 code = doubleCode % { "op": doubleUnaryOp }
453 code = code % { "func": doubleOp }
454 dIop = InstObjParams(name + "d", Name + "D", base,
455 { "code": code, "predicate_test": predicateTest }, [])

570

456

571 vdivDCode = '''
572 IntDoubleUnion cOp1, cOp2, cDest;
573 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
574 cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32));
575 vfpFlushToZero(Fpscr, cOp1.fp, cOp2.fp);
576 VfpSavedState state = prepVfpFpscr(Fpscr);
577 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cDest.fp));
578 cDest.fp = fixDest(Fpscr, cOp1.fp / cOp2.fp, cOp1.fp, cOp2.fp);
579 __asm__ __volatile__("" :: "m" (cDest.fp));
580 Fpscr = setVfpFpscr(Fpscr, state);
581 FpDestP0.uw = cDest.bits;
582 FpDestP1.uw = cDest.bits >> 32;
583 '''
584 vdivDIop = InstObjParams("vdivd", "VdivD", "VfpRegRegRegOp",
585 { "code": vdivDCode,
586 "predicate_test": predicateTest }, [])
587 header_output += VfpRegRegRegOpDeclare.subst(vdivDIop);
588 decoder_output += VfpRegRegRegOpConstructor.subst(vdivDIop);
589 exec_output += PredOpExecute.subst(vdivDIop);

457 declareTempl = eval(base + "Declare");
458 constructorTempl = eval(base + "Constructor");

590

459

591 vsqrtSCode = '''
592 vfpFlushToZero(Fpscr, FpOp1);
593 VfpSavedState state = prepVfpFpscr(Fpscr);
594 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
595 FpDest = sqrtf(FpOp1);
596 __asm__ __volatile__("" :: "m" (FpDest));
597 Fpscr = setVfpFpscr(Fpscr, state);
598 if (FpOp1 < 0) {
599 FpDest = NAN;
600 }
601 '''
602 vsqrtSIop = InstObjParams("vsqrts", "VsqrtS", "VfpRegRegOp",
603 { "code": vsqrtSCode,
604 "predicate_test": predicateTest }, [])
605 header_output += VfpRegRegOpDeclare.subst(vsqrtSIop);
606 decoder_output += VfpRegRegOpConstructor.subst(vsqrtSIop);
607 exec_output += PredOpExecute.subst(vsqrtSIop);

460 for iop in sIop, dIop:
461 header_output += declareTempl.subst(iop)
462 decoder_output += constructorTempl.subst(iop)
463 exec_output += PredOpExecute.subst(iop)

608

464

609 vsqrtDCode = '''
610 IntDoubleUnion cOp1, cDest;
611 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
612 vfpFlushToZero(Fpscr, cOp1.fp);
613 VfpSavedState state = prepVfpFpscr(Fpscr);
614 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cDest.fp));
615 cDest.fp = sqrt(cOp1.fp);
616 __asm__ __volatile__("" :: "m" (cDest.fp));
617 Fpscr = setVfpFpscr(Fpscr, state);
618 if (cOp1.fp < 0) {
619 cDest.fp = NAN;
620 }
621 FpDestP0.uw = cDest.bits;
622 FpDestP1.uw = cDest.bits >> 32;
623 '''
624 vsqrtDIop = InstObjParams("vsqrtd", "VsqrtD", "VfpRegRegOp",
625 { "code": vsqrtDCode,
626 "predicate_test": predicateTest }, [])
627 header_output += VfpRegRegOpDeclare.subst(vsqrtDIop);
628 decoder_output += VfpRegRegOpConstructor.subst(vsqrtDIop);
629 exec_output += PredOpExecute.subst(vsqrtDIop);

465 buildUnaryFpOp("vsqrt", "Vsqrt", "FpRegRegOp", "sqrtf", "sqrt")
466
467 def buildSimpleUnaryFpOp(name, Name, base, singleOp, doubleOp = None):
468 if doubleOp is None:
469 doubleOp = singleOp
470 global header_output, decoder_output, exec_output
471
472 sIop = InstObjParams(name + "s", Name + "S", base,
473 { "code": singleCode % { "op": singleOp },
474 "predicate_test": predicateTest }, [])
475 dIop = InstObjParams(name + "d", Name + "D", base,
476 { "code": doubleCode % { "op": doubleOp },
477 "predicate_test": predicateTest }, [])
478
479 declareTempl = eval(base + "Declare");
480 constructorTempl = eval(base + "Constructor");
481
482 for iop in sIop, dIop:
483 header_output += declareTempl.subst(iop)
484 decoder_output += constructorTempl.subst(iop)
485 exec_output += PredOpExecute.subst(iop)
486
487 buildSimpleUnaryFpOp("vneg", "Vneg", "FpRegRegOp",
488 "-FpOp1", "-dbl(FpOp1P0.uw, FpOp1P1.uw)")
489 buildSimpleUnaryFpOp("vabs", "Vabs", "FpRegRegOp",
490 "fabsf(FpOp1)", "fabs(dbl(FpOp1P0.uw, FpOp1P1.uw))")

630}};
631
632let {{
633
634 header_output = ""
635 decoder_output = ""
636 exec_output = ""
637
638 vmlaSCode = '''

491}};
492
493let {{
494
495 header_output = ""
496 decoder_output = ""
497 exec_output = ""
498
499 vmlaSCode = '''

639 vfpFlushToZero(Fpscr, FpOp1, FpOp2);
640 VfpSavedState state = prepVfpFpscr(Fpscr);
641 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
642 float mid = fixDest(Fpscr, FpOp1 * FpOp2, FpOp1, FpOp2);
643 if ((isinf(FpOp1) && FpOp2 == 0) || (isinf(FpOp2) && FpOp1 == 0)) {
644 mid = NAN;
645 }
646 vfpFlushToZero(Fpscr, FpDest, mid);
647 FpDest = fixDest(Fpscr, FpDest + mid, FpDest, mid);
648 __asm__ __volatile__("" :: "m" (FpDest));
649 Fpscr = setVfpFpscr(Fpscr, state);

500 FPSCR fpscr = Fpscr;
501 float mid = binaryOp(fpscr, FpOp1, FpOp2,
502 fpMulS, fpscr.fz, fpscr.rMode);
503 FpDest = binaryOp(fpscr, FpDest, mid, fpAddS, fpscr.fz, fpscr.rMode);
504 Fpscr = fpscr;

650 '''

505 '''

651 vmlaSIop = InstObjParams("vmlas", "VmlaS", "VfpRegRegRegOp",

506 vmlaSIop = InstObjParams("vmlas", "VmlaS", "FpRegRegRegOp",

652 { "code": vmlaSCode,
653 "predicate_test": predicateTest }, [])

507 { "code": vmlaSCode,
508 "predicate_test": predicateTest }, [])

654 header_output += VfpRegRegRegOpDeclare.subst(vmlaSIop);
655 decoder_output += VfpRegRegRegOpConstructor.subst(vmlaSIop);

509 header_output += FpRegRegRegOpDeclare.subst(vmlaSIop);
510 decoder_output += FpRegRegRegOpConstructor.subst(vmlaSIop);

656 exec_output += PredOpExecute.subst(vmlaSIop);
657
658 vmlaDCode = '''

511 exec_output += PredOpExecute.subst(vmlaSIop);
512
513 vmlaDCode = '''

659 IntDoubleUnion cOp1, cOp2, cDest;
660 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
661 cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32));
662 cDest.bits = ((uint64_t)FpDestP0.uw | ((uint64_t)FpDestP1.uw << 32));
663 vfpFlushToZero(Fpscr, cOp1.fp, cOp2.fp);
664 VfpSavedState state = prepVfpFpscr(Fpscr);
665 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp));
666 double mid = fixDest(Fpscr, cOp1.fp * cOp2.fp, cOp1.fp, cOp2.fp);
667 if ((isinf(cOp1.fp) && cOp2.fp == 0) ||
668 (isinf(cOp2.fp) && cOp1.fp == 0)) {
669 mid = NAN;
670 }
671 vfpFlushToZero(Fpscr, cDest.fp, mid);
672 cDest.fp = fixDest(Fpscr, cDest.fp + mid, cDest.fp, mid);
673 __asm__ __volatile__("" :: "m" (cDest.fp));
674 Fpscr = setVfpFpscr(Fpscr, state);
675 FpDestP0.uw = cDest.bits;
676 FpDestP1.uw = cDest.bits >> 32;

514 FPSCR fpscr = Fpscr;
515 double mid = binaryOp(fpscr, dbl(FpOp1P0.uw, FpOp1P1.uw),
516 dbl(FpOp2P0.uw, FpOp2P1.uw),
517 fpMulD, fpscr.fz, fpscr.rMode);
518 double dest = binaryOp(fpscr, dbl(FpDestP0.uw, FpDestP1.uw),
519 mid, fpAddD, fpscr.fz, fpscr.rMode);
520 Fpscr = fpscr;
521 FpDestP0.uw = dblLow(dest);
522 FpDestP1.uw = dblHi(dest);

677 '''

523 '''

678 vmlaDIop = InstObjParams("vmlad", "VmlaD", "VfpRegRegRegOp",

524 vmlaDIop = InstObjParams("vmlad", "VmlaD", "FpRegRegRegOp",

679 { "code": vmlaDCode,
680 "predicate_test": predicateTest }, [])

525 { "code": vmlaDCode,
526 "predicate_test": predicateTest }, [])

681 header_output += VfpRegRegRegOpDeclare.subst(vmlaDIop);
682 decoder_output += VfpRegRegRegOpConstructor.subst(vmlaDIop);

527 header_output += FpRegRegRegOpDeclare.subst(vmlaDIop);
528 decoder_output += FpRegRegRegOpConstructor.subst(vmlaDIop);

683 exec_output += PredOpExecute.subst(vmlaDIop);
684
685 vmlsSCode = '''

529 exec_output += PredOpExecute.subst(vmlaDIop);
530
531 vmlsSCode = '''

686 vfpFlushToZero(Fpscr, FpOp1, FpOp2);
687 VfpSavedState state = prepVfpFpscr(Fpscr);
688 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
689 float mid = fixDest(Fpscr, FpOp1 * FpOp2, FpOp1, FpOp2);
690 if ((isinf(FpOp1) && FpOp2 == 0) || (isinf(FpOp2) && FpOp1 == 0)) {
691 mid = NAN;
692 }
693 vfpFlushToZero(Fpscr, FpDest, mid);
694 FpDest = fixDest(Fpscr, FpDest - mid, FpDest, -mid);
695 __asm__ __volatile__("" :: "m" (FpDest));
696 Fpscr = setVfpFpscr(Fpscr, state);

532 FPSCR fpscr = Fpscr;
533 float mid = binaryOp(fpscr, FpOp1, FpOp2,
534 fpMulS, fpscr.fz, fpscr.rMode);
535 FpDest = binaryOp(fpscr, FpDest, -mid, fpAddS, fpscr.fz, fpscr.rMode);
536 Fpscr = fpscr;

697 '''

537 '''

698 vmlsSIop = InstObjParams("vmlss", "VmlsS", "VfpRegRegRegOp",

538 vmlsSIop = InstObjParams("vmlss", "VmlsS", "FpRegRegRegOp",

699 { "code": vmlsSCode,
700 "predicate_test": predicateTest }, [])

539 { "code": vmlsSCode,
540 "predicate_test": predicateTest }, [])

701 header_output += VfpRegRegRegOpDeclare.subst(vmlsSIop);
702 decoder_output += VfpRegRegRegOpConstructor.subst(vmlsSIop);

541 header_output += FpRegRegRegOpDeclare.subst(vmlsSIop);
542 decoder_output += FpRegRegRegOpConstructor.subst(vmlsSIop);

703 exec_output += PredOpExecute.subst(vmlsSIop);
704
705 vmlsDCode = '''

543 exec_output += PredOpExecute.subst(vmlsSIop);
544
545 vmlsDCode = '''

706 IntDoubleUnion cOp1, cOp2, cDest;
707 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
708 cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32));
709 cDest.bits = ((uint64_t)FpDestP0.uw | ((uint64_t)FpDestP1.uw << 32));
710 vfpFlushToZero(Fpscr, cOp1.fp, cOp2.fp);
711 VfpSavedState state = prepVfpFpscr(Fpscr);
712 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp));
713 double mid = fixDest(Fpscr, cOp1.fp * cOp2.fp, cOp1.fp, cOp2.fp);
714 if ((isinf(cOp1.fp) && cOp2.fp == 0) ||
715 (isinf(cOp2.fp) && cOp1.fp == 0)) {
716 mid = NAN;
717 }
718 cDest.fp = fixDest(Fpscr, cDest.fp - mid, cDest.fp, -mid);
719 vfpFlushToZero(Fpscr, cDest.fp, mid);
720 __asm__ __volatile__("" :: "m" (cDest.fp));
721 Fpscr = setVfpFpscr(Fpscr, state);
722 FpDestP0.uw = cDest.bits;
723 FpDestP1.uw = cDest.bits >> 32;

546 FPSCR fpscr = Fpscr;
547 double mid = binaryOp(fpscr, dbl(FpOp1P0.uw, FpOp1P1.uw),
548 dbl(FpOp2P0.uw, FpOp2P1.uw),
549 fpMulD, fpscr.fz, fpscr.rMode);
550 double dest = binaryOp(fpscr, dbl(FpDestP0.uw, FpDestP1.uw),
551 -mid, fpAddD, fpscr.fz, fpscr.rMode);
552 Fpscr = fpscr;
553 FpDestP0.uw = dblLow(dest);
554 FpDestP1.uw = dblHi(dest);

724 '''

555 '''

725 vmlsDIop = InstObjParams("vmlsd", "VmlsD", "VfpRegRegRegOp",

556 vmlsDIop = InstObjParams("vmlsd", "VmlsD", "FpRegRegRegOp",

726 { "code": vmlsDCode,
727 "predicate_test": predicateTest }, [])

557 { "code": vmlsDCode,
558 "predicate_test": predicateTest }, [])

728 header_output += VfpRegRegRegOpDeclare.subst(vmlsDIop);
729 decoder_output += VfpRegRegRegOpConstructor.subst(vmlsDIop);

559 header_output += FpRegRegRegOpDeclare.subst(vmlsDIop);
560 decoder_output += FpRegRegRegOpConstructor.subst(vmlsDIop);

730 exec_output += PredOpExecute.subst(vmlsDIop);
731
732 vnmlaSCode = '''

561 exec_output += PredOpExecute.subst(vmlsDIop);
562
563 vnmlaSCode = '''

733 vfpFlushToZero(Fpscr, FpOp1, FpOp2);
734 VfpSavedState state = prepVfpFpscr(Fpscr);
735 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
736 float mid = fixDest(Fpscr, FpOp1 * FpOp2, FpOp1, FpOp2);
737 if ((isinf(FpOp1) && FpOp2 == 0) || (isinf(FpOp2) && FpOp1 == 0)) {
738 mid = NAN;
739 }
740 vfpFlushToZero(Fpscr, FpDest, mid);
741 FpDest = fixDest(Fpscr, -FpDest - mid, -FpDest, -mid);
742 __asm__ __volatile__("" :: "m" (FpDest));
743 Fpscr = setVfpFpscr(Fpscr, state);

564 FPSCR fpscr = Fpscr;
565 float mid = binaryOp(fpscr, FpOp1, FpOp2,
566 fpMulS, fpscr.fz, fpscr.rMode);
567 FpDest = binaryOp(fpscr, -FpDest, -mid, fpAddS, fpscr.fz, fpscr.rMode);
568 Fpscr = fpscr;

744 '''

569 '''

745 vnmlaSIop = InstObjParams("vnmlas", "VnmlaS", "VfpRegRegRegOp",

570 vnmlaSIop = InstObjParams("vnmlas", "VnmlaS", "FpRegRegRegOp",

746 { "code": vnmlaSCode,
747 "predicate_test": predicateTest }, [])

571 { "code": vnmlaSCode,
572 "predicate_test": predicateTest }, [])

748 header_output += VfpRegRegRegOpDeclare.subst(vnmlaSIop);
749 decoder_output += VfpRegRegRegOpConstructor.subst(vnmlaSIop);

573 header_output += FpRegRegRegOpDeclare.subst(vnmlaSIop);
574 decoder_output += FpRegRegRegOpConstructor.subst(vnmlaSIop);

750 exec_output += PredOpExecute.subst(vnmlaSIop);
751
752 vnmlaDCode = '''

575 exec_output += PredOpExecute.subst(vnmlaSIop);
576
577 vnmlaDCode = '''

753 IntDoubleUnion cOp1, cOp2, cDest;
754 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
755 cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32));
756 cDest.bits = ((uint64_t)FpDestP0.uw | ((uint64_t)FpDestP1.uw << 32));
757 vfpFlushToZero(Fpscr, cOp1.fp, cOp2.fp);
758 VfpSavedState state = prepVfpFpscr(Fpscr);
759 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp));
760 double mid = fixDest(Fpscr, cOp1.fp * cOp2.fp, cOp1.fp, cOp2.fp);
761 if ((isinf(cOp1.fp) && cOp2.fp == 0) ||
762 (isinf(cOp2.fp) && cOp1.fp == 0)) {
763 mid = NAN;
764 }
765 vfpFlushToZero(Fpscr, cDest.fp, mid);
766 cDest.fp = fixDest(Fpscr, -cDest.fp - mid, -cDest.fp, -mid);
767 __asm__ __volatile__("" :: "m" (cDest.fp));
768 Fpscr = setVfpFpscr(Fpscr, state);
769 FpDestP0.uw = cDest.bits;
770 FpDestP1.uw = cDest.bits >> 32;

578 FPSCR fpscr = Fpscr;
579 double mid = binaryOp(fpscr, dbl(FpOp1P0.uw, FpOp1P1.uw),
580 dbl(FpOp2P0.uw, FpOp2P1.uw),
581 fpMulD, fpscr.fz, fpscr.rMode);
582 double dest = binaryOp(fpscr, -dbl(FpDestP0.uw, FpDestP1.uw),
583 -mid, fpAddD, fpscr.fz, fpscr.rMode);
584 Fpscr = fpscr;
585 FpDestP0.uw = dblLow(dest);
586 FpDestP1.uw = dblHi(dest);

771 '''

587 '''

772 vnmlaDIop = InstObjParams("vnmlad", "VnmlaD", "VfpRegRegRegOp",

588 vnmlaDIop = InstObjParams("vnmlad", "VnmlaD", "FpRegRegRegOp",

773 { "code": vnmlaDCode,
774 "predicate_test": predicateTest }, [])

589 { "code": vnmlaDCode,
590 "predicate_test": predicateTest }, [])

775 header_output += VfpRegRegRegOpDeclare.subst(vnmlaDIop);
776 decoder_output += VfpRegRegRegOpConstructor.subst(vnmlaDIop);

591 header_output += FpRegRegRegOpDeclare.subst(vnmlaDIop);
592 decoder_output += FpRegRegRegOpConstructor.subst(vnmlaDIop);

777 exec_output += PredOpExecute.subst(vnmlaDIop);
778
779 vnmlsSCode = '''

593 exec_output += PredOpExecute.subst(vnmlaDIop);
594
595 vnmlsSCode = '''

780 vfpFlushToZero(Fpscr, FpOp1, FpOp2);
781 VfpSavedState state = prepVfpFpscr(Fpscr);
782 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
783 float mid = fixDest(Fpscr, FpOp1 * FpOp2, FpOp1, FpOp2);
784 if ((isinf(FpOp1) && FpOp2 == 0) || (isinf(FpOp2) && FpOp1 == 0)) {
785 mid = NAN;
786 }
787 vfpFlushToZero(Fpscr, FpDest, mid);
788 FpDest = fixDest(Fpscr, -FpDest + mid, -FpDest, mid);
789 __asm__ __volatile__("" :: "m" (FpDest));
790 Fpscr = setVfpFpscr(Fpscr, state);

596 FPSCR fpscr = Fpscr;
597 float mid = binaryOp(fpscr, FpOp1, FpOp2,
598 fpMulS, fpscr.fz, fpscr.rMode);
599 FpDest = binaryOp(fpscr, -FpDest, mid, fpAddS, fpscr.fz, fpscr.rMode);
600 Fpscr = fpscr;

791 '''

601 '''

792 vnmlsSIop = InstObjParams("vnmlss", "VnmlsS", "VfpRegRegRegOp",

602 vnmlsSIop = InstObjParams("vnmlss", "VnmlsS", "FpRegRegRegOp",

793 { "code": vnmlsSCode,
794 "predicate_test": predicateTest }, [])

603 { "code": vnmlsSCode,
604 "predicate_test": predicateTest }, [])

795 header_output += VfpRegRegRegOpDeclare.subst(vnmlsSIop);
796 decoder_output += VfpRegRegRegOpConstructor.subst(vnmlsSIop);

605 header_output += FpRegRegRegOpDeclare.subst(vnmlsSIop);
606 decoder_output += FpRegRegRegOpConstructor.subst(vnmlsSIop);

797 exec_output += PredOpExecute.subst(vnmlsSIop);
798
799 vnmlsDCode = '''

607 exec_output += PredOpExecute.subst(vnmlsSIop);
608
609 vnmlsDCode = '''

800 IntDoubleUnion cOp1, cOp2, cDest;
801 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
802 cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32));
803 cDest.bits = ((uint64_t)FpDestP0.uw | ((uint64_t)FpDestP1.uw << 32));
804 vfpFlushToZero(Fpscr, cOp1.fp, cOp2.fp);
805 VfpSavedState state = prepVfpFpscr(Fpscr);
806 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp));
807 double mid = fixDest(Fpscr, cOp1.fp * cOp2.fp, cOp1.fp, cOp2.fp);
808 if ((isinf(cOp1.fp) && cOp2.fp == 0) ||
809 (isinf(cOp2.fp) && cOp1.fp == 0)) {
810 mid = NAN;
811 }
812 vfpFlushToZero(Fpscr, cDest.fp, mid);
813 cDest.fp = fixDest(Fpscr, -cDest.fp + mid, -cDest.fp, mid);
814 __asm__ __volatile__("" :: "m" (cDest.fp));
815 Fpscr = setVfpFpscr(Fpscr, state);
816 FpDestP0.uw = cDest.bits;
817 FpDestP1.uw = cDest.bits >> 32;

610 FPSCR fpscr = Fpscr;
611 double mid = binaryOp(fpscr, dbl(FpOp1P0.uw, FpOp1P1.uw),
612 dbl(FpOp2P0.uw, FpOp2P1.uw),
613 fpMulD, fpscr.fz, fpscr.rMode);
614 double dest = binaryOp(fpscr, -dbl(FpDestP0.uw, FpDestP1.uw),
615 mid, fpAddD, fpscr.fz, fpscr.rMode);
616 Fpscr = fpscr;
617 FpDestP0.uw = dblLow(dest);
618 FpDestP1.uw = dblHi(dest);

818 '''

619 '''

819 vnmlsDIop = InstObjParams("vnmlsd", "VnmlsD", "VfpRegRegRegOp",

620 vnmlsDIop = InstObjParams("vnmlsd", "VnmlsD", "FpRegRegRegOp",

820 { "code": vnmlsDCode,
821 "predicate_test": predicateTest }, [])

621 { "code": vnmlsDCode,
622 "predicate_test": predicateTest }, [])

822 header_output += VfpRegRegRegOpDeclare.subst(vnmlsDIop);
823 decoder_output += VfpRegRegRegOpConstructor.subst(vnmlsDIop);

623 header_output += FpRegRegRegOpDeclare.subst(vnmlsDIop);
624 decoder_output += FpRegRegRegOpConstructor.subst(vnmlsDIop);

824 exec_output += PredOpExecute.subst(vnmlsDIop);
825
826 vnmulSCode = '''

625 exec_output += PredOpExecute.subst(vnmlsDIop);
626
627 vnmulSCode = '''

827 vfpFlushToZero(Fpscr, FpOp1, FpOp2);
828 VfpSavedState state = prepVfpFpscr(Fpscr);
829 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
830 float mid = fixDest(Fpscr, FpOp1 * FpOp2, FpOp1, FpOp2);
831 if ((isinf(FpOp1) && FpOp2 == 0) || (isinf(FpOp2) && FpOp1 == 0)) {
832 mid = NAN;
833 }
834 FpDest = -mid;
835 __asm__ __volatile__("" :: "m" (FpDest));
836 Fpscr = setVfpFpscr(Fpscr, state);

628 FPSCR fpscr = Fpscr;
629 FpDest = -binaryOp(fpscr, FpOp1, FpOp2, fpMulS, fpscr.fz, fpscr.rMode);
630 Fpscr = fpscr;

837 '''

631 '''

838 vnmulSIop = InstObjParams("vnmuls", "VnmulS", "VfpRegRegRegOp",

632 vnmulSIop = InstObjParams("vnmuls", "VnmulS", "FpRegRegRegOp",

839 { "code": vnmulSCode,
840 "predicate_test": predicateTest }, [])

633 { "code": vnmulSCode,
634 "predicate_test": predicateTest }, [])

841 header_output += VfpRegRegRegOpDeclare.subst(vnmulSIop);
842 decoder_output += VfpRegRegRegOpConstructor.subst(vnmulSIop);

635 header_output += FpRegRegRegOpDeclare.subst(vnmulSIop);
636 decoder_output += FpRegRegRegOpConstructor.subst(vnmulSIop);

843 exec_output += PredOpExecute.subst(vnmulSIop);
844
845 vnmulDCode = '''

637 exec_output += PredOpExecute.subst(vnmulSIop);
638
639 vnmulDCode = '''

846 IntDoubleUnion cOp1, cOp2, cDest;
847 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
848 cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32));
849 cDest.bits = ((uint64_t)FpDestP0.uw | ((uint64_t)FpDestP1.uw << 32));
850 vfpFlushToZero(Fpscr, cOp1.fp, cOp2.fp);
851 VfpSavedState state = prepVfpFpscr(Fpscr);
852 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp));
853 double mid = fixDest(Fpscr, cOp1.fp * cOp2.fp, cOp1.fp, cOp2.fp);
854 if ((isinf(cOp1.fp) && cOp2.fp == 0) ||
855 (isinf(cOp2.fp) && cOp1.fp == 0)) {
856 mid = NAN;
857 }
858 cDest.fp = -mid;
859 __asm__ __volatile__("" :: "m" (cDest.fp));
860 Fpscr = setVfpFpscr(Fpscr, state);
861 FpDestP0.uw = cDest.bits;
862 FpDestP1.uw = cDest.bits >> 32;

640 FPSCR fpscr = Fpscr;
641 double dest = -binaryOp(fpscr, dbl(FpOp1P0.uw, FpOp1P1.uw),
642 dbl(FpOp2P0.uw, FpOp2P1.uw),
643 fpMulD, fpscr.fz, fpscr.rMode);
644 Fpscr = fpscr;
645 FpDestP0.uw = dblLow(dest);
646 FpDestP1.uw = dblHi(dest);

863 '''

647 '''

864 vnmulDIop = InstObjParams("vnmuld", "VnmulD", "VfpRegRegRegOp",

648 vnmulDIop = InstObjParams("vnmuld", "VnmulD", "FpRegRegRegOp",

865 { "code": vnmulDCode,
866 "predicate_test": predicateTest }, [])

649 { "code": vnmulDCode,
650 "predicate_test": predicateTest }, [])

867 header_output += VfpRegRegRegOpDeclare.subst(vnmulDIop);
868 decoder_output += VfpRegRegRegOpConstructor.subst(vnmulDIop);

651 header_output += FpRegRegRegOpDeclare.subst(vnmulDIop);
652 decoder_output += FpRegRegRegOpConstructor.subst(vnmulDIop);

869 exec_output += PredOpExecute.subst(vnmulDIop);
870}};
871
872let {{
873
874 header_output = ""
875 decoder_output = ""
876 exec_output = ""
877
878 vcvtUIntFpSCode = '''
879 VfpSavedState state = prepVfpFpscr(Fpscr);
880 __asm__ __volatile__("" : "=m" (FpOp1.uw) : "m" (FpOp1.uw));
881 FpDest = FpOp1.uw;
882 __asm__ __volatile__("" :: "m" (FpDest));
883 Fpscr = setVfpFpscr(Fpscr, state);
884 '''

653 exec_output += PredOpExecute.subst(vnmulDIop);
654}};
655
656let {{
657
658 header_output = ""
659 decoder_output = ""
660 exec_output = ""
661
662 vcvtUIntFpSCode = '''
663 VfpSavedState state = prepVfpFpscr(Fpscr);
664 __asm__ __volatile__("" : "=m" (FpOp1.uw) : "m" (FpOp1.uw));
665 FpDest = FpOp1.uw;
666 __asm__ __volatile__("" :: "m" (FpDest));
667 Fpscr = setVfpFpscr(Fpscr, state);
668 '''

885 vcvtUIntFpSIop = InstObjParams("vcvt", "VcvtUIntFpS", "VfpRegRegOp",

669 vcvtUIntFpSIop = InstObjParams("vcvt", "VcvtUIntFpS", "FpRegRegOp",

886 { "code": vcvtUIntFpSCode,
887 "predicate_test": predicateTest }, [])

670 { "code": vcvtUIntFpSCode,
671 "predicate_test": predicateTest }, [])

888 header_output += VfpRegRegOpDeclare.subst(vcvtUIntFpSIop);
889 decoder_output += VfpRegRegOpConstructor.subst(vcvtUIntFpSIop);

672 header_output += FpRegRegOpDeclare.subst(vcvtUIntFpSIop);
673 decoder_output += FpRegRegOpConstructor.subst(vcvtUIntFpSIop);

890 exec_output += PredOpExecute.subst(vcvtUIntFpSIop);
891
892 vcvtUIntFpDCode = '''
893 IntDoubleUnion cDest;
894 VfpSavedState state = prepVfpFpscr(Fpscr);
895 __asm__ __volatile__("" : "=m" (FpOp1P0.uw) : "m" (FpOp1P0.uw));
896 cDest.fp = (uint64_t)FpOp1P0.uw;
897 __asm__ __volatile__("" :: "m" (cDest.fp));
898 Fpscr = setVfpFpscr(Fpscr, state);
899 FpDestP0.uw = cDest.bits;
900 FpDestP1.uw = cDest.bits >> 32;
901 '''

674 exec_output += PredOpExecute.subst(vcvtUIntFpSIop);
675
676 vcvtUIntFpDCode = '''
677 IntDoubleUnion cDest;
678 VfpSavedState state = prepVfpFpscr(Fpscr);
679 __asm__ __volatile__("" : "=m" (FpOp1P0.uw) : "m" (FpOp1P0.uw));
680 cDest.fp = (uint64_t)FpOp1P0.uw;
681 __asm__ __volatile__("" :: "m" (cDest.fp));
682 Fpscr = setVfpFpscr(Fpscr, state);
683 FpDestP0.uw = cDest.bits;
684 FpDestP1.uw = cDest.bits >> 32;
685 '''

902 vcvtUIntFpDIop = InstObjParams("vcvt", "VcvtUIntFpD", "VfpRegRegOp",

686 vcvtUIntFpDIop = InstObjParams("vcvt", "VcvtUIntFpD", "FpRegRegOp",

903 { "code": vcvtUIntFpDCode,
904 "predicate_test": predicateTest }, [])

687 { "code": vcvtUIntFpDCode,
688 "predicate_test": predicateTest }, [])

905 header_output += VfpRegRegOpDeclare.subst(vcvtUIntFpDIop);
906 decoder_output += VfpRegRegOpConstructor.subst(vcvtUIntFpDIop);

689 header_output += FpRegRegOpDeclare.subst(vcvtUIntFpDIop);
690 decoder_output += FpRegRegOpConstructor.subst(vcvtUIntFpDIop);

907 exec_output += PredOpExecute.subst(vcvtUIntFpDIop);
908
909 vcvtSIntFpSCode = '''
910 VfpSavedState state = prepVfpFpscr(Fpscr);
911 __asm__ __volatile__("" : "=m" (FpOp1.sw) : "m" (FpOp1.sw));
912 FpDest = FpOp1.sw;
913 __asm__ __volatile__("" :: "m" (FpDest));
914 Fpscr = setVfpFpscr(Fpscr, state);
915 '''

691 exec_output += PredOpExecute.subst(vcvtUIntFpDIop);
692
693 vcvtSIntFpSCode = '''
694 VfpSavedState state = prepVfpFpscr(Fpscr);
695 __asm__ __volatile__("" : "=m" (FpOp1.sw) : "m" (FpOp1.sw));
696 FpDest = FpOp1.sw;
697 __asm__ __volatile__("" :: "m" (FpDest));
698 Fpscr = setVfpFpscr(Fpscr, state);
699 '''

916 vcvtSIntFpSIop = InstObjParams("vcvt", "VcvtSIntFpS", "VfpRegRegOp",

700 vcvtSIntFpSIop = InstObjParams("vcvt", "VcvtSIntFpS", "FpRegRegOp",

917 { "code": vcvtSIntFpSCode,
918 "predicate_test": predicateTest }, [])

701 { "code": vcvtSIntFpSCode,
702 "predicate_test": predicateTest }, [])

919 header_output += VfpRegRegOpDeclare.subst(vcvtSIntFpSIop);
920 decoder_output += VfpRegRegOpConstructor.subst(vcvtSIntFpSIop);

703 header_output += FpRegRegOpDeclare.subst(vcvtSIntFpSIop);
704 decoder_output += FpRegRegOpConstructor.subst(vcvtSIntFpSIop);

921 exec_output += PredOpExecute.subst(vcvtSIntFpSIop);
922
923 vcvtSIntFpDCode = '''
924 IntDoubleUnion cDest;
925 VfpSavedState state = prepVfpFpscr(Fpscr);
926 __asm__ __volatile__("" : "=m" (FpOp1P0.sw) : "m" (FpOp1P0.sw));
927 cDest.fp = FpOp1P0.sw;
928 __asm__ __volatile__("" :: "m" (cDest.fp));
929 Fpscr = setVfpFpscr(Fpscr, state);
930 FpDestP0.uw = cDest.bits;
931 FpDestP1.uw = cDest.bits >> 32;
932 '''

705 exec_output += PredOpExecute.subst(vcvtSIntFpSIop);
706
707 vcvtSIntFpDCode = '''
708 IntDoubleUnion cDest;
709 VfpSavedState state = prepVfpFpscr(Fpscr);
710 __asm__ __volatile__("" : "=m" (FpOp1P0.sw) : "m" (FpOp1P0.sw));
711 cDest.fp = FpOp1P0.sw;
712 __asm__ __volatile__("" :: "m" (cDest.fp));
713 Fpscr = setVfpFpscr(Fpscr, state);
714 FpDestP0.uw = cDest.bits;
715 FpDestP1.uw = cDest.bits >> 32;
716 '''

933 vcvtSIntFpDIop = InstObjParams("vcvt", "VcvtSIntFpD", "VfpRegRegOp",

717 vcvtSIntFpDIop = InstObjParams("vcvt", "VcvtSIntFpD", "FpRegRegOp",

934 { "code": vcvtSIntFpDCode,
935 "predicate_test": predicateTest }, [])

718 { "code": vcvtSIntFpDCode,
719 "predicate_test": predicateTest }, [])

936 header_output += VfpRegRegOpDeclare.subst(vcvtSIntFpDIop);
937 decoder_output += VfpRegRegOpConstructor.subst(vcvtSIntFpDIop);

720 header_output += FpRegRegOpDeclare.subst(vcvtSIntFpDIop);
721 decoder_output += FpRegRegOpConstructor.subst(vcvtSIntFpDIop);

938 exec_output += PredOpExecute.subst(vcvtSIntFpDIop);
939
940 vcvtFpUIntSRCode = '''
941 vfpFlushToZero(Fpscr, FpOp1);
942 VfpSavedState state = prepVfpFpscr(Fpscr);
943 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
944 FpDest.uw = vfpFpSToFixed(FpOp1, false, false, 0, false);
945 __asm__ __volatile__("" :: "m" (FpDest.uw));
946 Fpscr = setVfpFpscr(Fpscr, state);
947 '''

722 exec_output += PredOpExecute.subst(vcvtSIntFpDIop);
723
724 vcvtFpUIntSRCode = '''
725 vfpFlushToZero(Fpscr, FpOp1);
726 VfpSavedState state = prepVfpFpscr(Fpscr);
727 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
728 FpDest.uw = vfpFpSToFixed(FpOp1, false, false, 0, false);
729 __asm__ __volatile__("" :: "m" (FpDest.uw));
730 Fpscr = setVfpFpscr(Fpscr, state);
731 '''

948 vcvtFpUIntSRIop = InstObjParams("vcvt", "VcvtFpUIntSR", "VfpRegRegOp",

732 vcvtFpUIntSRIop = InstObjParams("vcvt", "VcvtFpUIntSR", "FpRegRegOp",

949 { "code": vcvtFpUIntSRCode,
950 "predicate_test": predicateTest }, [])

733 { "code": vcvtFpUIntSRCode,
734 "predicate_test": predicateTest }, [])

951 header_output += VfpRegRegOpDeclare.subst(vcvtFpUIntSRIop);
952 decoder_output += VfpRegRegOpConstructor.subst(vcvtFpUIntSRIop);

735 header_output += FpRegRegOpDeclare.subst(vcvtFpUIntSRIop);
736 decoder_output += FpRegRegOpConstructor.subst(vcvtFpUIntSRIop);

953 exec_output += PredOpExecute.subst(vcvtFpUIntSRIop);
954
955 vcvtFpUIntDRCode = '''
956 IntDoubleUnion cOp1;
957 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
958 vfpFlushToZero(Fpscr, cOp1.fp);
959 VfpSavedState state = prepVfpFpscr(Fpscr);
960 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp));
961 uint64_t result = vfpFpDToFixed(cOp1.fp, false, false, 0, false);
962 __asm__ __volatile__("" :: "m" (result));
963 Fpscr = setVfpFpscr(Fpscr, state);
964 FpDestP0.uw = result;
965 '''

737 exec_output += PredOpExecute.subst(vcvtFpUIntSRIop);
738
739 vcvtFpUIntDRCode = '''
740 IntDoubleUnion cOp1;
741 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
742 vfpFlushToZero(Fpscr, cOp1.fp);
743 VfpSavedState state = prepVfpFpscr(Fpscr);
744 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp));
745 uint64_t result = vfpFpDToFixed(cOp1.fp, false, false, 0, false);
746 __asm__ __volatile__("" :: "m" (result));
747 Fpscr = setVfpFpscr(Fpscr, state);
748 FpDestP0.uw = result;
749 '''

966 vcvtFpUIntDRIop = InstObjParams("vcvtr", "VcvtFpUIntDR", "VfpRegRegOp",

750 vcvtFpUIntDRIop = InstObjParams("vcvtr", "VcvtFpUIntDR", "FpRegRegOp",

967 { "code": vcvtFpUIntDRCode,
968 "predicate_test": predicateTest }, [])

751 { "code": vcvtFpUIntDRCode,
752 "predicate_test": predicateTest }, [])

969 header_output += VfpRegRegOpDeclare.subst(vcvtFpUIntDRIop);
970 decoder_output += VfpRegRegOpConstructor.subst(vcvtFpUIntDRIop);

753 header_output += FpRegRegOpDeclare.subst(vcvtFpUIntDRIop);
754 decoder_output += FpRegRegOpConstructor.subst(vcvtFpUIntDRIop);

971 exec_output += PredOpExecute.subst(vcvtFpUIntDRIop);
972
973 vcvtFpSIntSRCode = '''
974 vfpFlushToZero(Fpscr, FpOp1);
975 VfpSavedState state = prepVfpFpscr(Fpscr);
976 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
977 FpDest.sw = vfpFpSToFixed(FpOp1, true, false, 0, false);
978 __asm__ __volatile__("" :: "m" (FpDest.sw));
979 Fpscr = setVfpFpscr(Fpscr, state);
980 '''

755 exec_output += PredOpExecute.subst(vcvtFpUIntDRIop);
756
757 vcvtFpSIntSRCode = '''
758 vfpFlushToZero(Fpscr, FpOp1);
759 VfpSavedState state = prepVfpFpscr(Fpscr);
760 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
761 FpDest.sw = vfpFpSToFixed(FpOp1, true, false, 0, false);
762 __asm__ __volatile__("" :: "m" (FpDest.sw));
763 Fpscr = setVfpFpscr(Fpscr, state);
764 '''

981 vcvtFpSIntSRIop = InstObjParams("vcvtr", "VcvtFpSIntSR", "VfpRegRegOp",

765 vcvtFpSIntSRIop = InstObjParams("vcvtr", "VcvtFpSIntSR", "FpRegRegOp",

982 { "code": vcvtFpSIntSRCode,
983 "predicate_test": predicateTest }, [])

766 { "code": vcvtFpSIntSRCode,
767 "predicate_test": predicateTest }, [])

984 header_output += VfpRegRegOpDeclare.subst(vcvtFpSIntSRIop);
985 decoder_output += VfpRegRegOpConstructor.subst(vcvtFpSIntSRIop);

768 header_output += FpRegRegOpDeclare.subst(vcvtFpSIntSRIop);
769 decoder_output += FpRegRegOpConstructor.subst(vcvtFpSIntSRIop);

986 exec_output += PredOpExecute.subst(vcvtFpSIntSRIop);
987
988 vcvtFpSIntDRCode = '''
989 IntDoubleUnion cOp1;
990 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
991 vfpFlushToZero(Fpscr, cOp1.fp);
992 VfpSavedState state = prepVfpFpscr(Fpscr);
993 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp));
994 int64_t result = vfpFpDToFixed(cOp1.fp, true, false, 0, false);
995 __asm__ __volatile__("" :: "m" (result));
996 Fpscr = setVfpFpscr(Fpscr, state);
997 FpDestP0.uw = result;
998 '''

770 exec_output += PredOpExecute.subst(vcvtFpSIntSRIop);
771
772 vcvtFpSIntDRCode = '''
773 IntDoubleUnion cOp1;
774 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
775 vfpFlushToZero(Fpscr, cOp1.fp);
776 VfpSavedState state = prepVfpFpscr(Fpscr);
777 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp));
778 int64_t result = vfpFpDToFixed(cOp1.fp, true, false, 0, false);
779 __asm__ __volatile__("" :: "m" (result));
780 Fpscr = setVfpFpscr(Fpscr, state);
781 FpDestP0.uw = result;
782 '''

999 vcvtFpSIntDRIop = InstObjParams("vcvtr", "VcvtFpSIntDR", "VfpRegRegOp",

783 vcvtFpSIntDRIop = InstObjParams("vcvtr", "VcvtFpSIntDR", "FpRegRegOp",

1000 { "code": vcvtFpSIntDRCode,
1001 "predicate_test": predicateTest }, [])

784 { "code": vcvtFpSIntDRCode,
785 "predicate_test": predicateTest }, [])

1002 header_output += VfpRegRegOpDeclare.subst(vcvtFpSIntDRIop);
1003 decoder_output += VfpRegRegOpConstructor.subst(vcvtFpSIntDRIop);

786 header_output += FpRegRegOpDeclare.subst(vcvtFpSIntDRIop);
787 decoder_output += FpRegRegOpConstructor.subst(vcvtFpSIntDRIop);

1004 exec_output += PredOpExecute.subst(vcvtFpSIntDRIop);
1005
1006 vcvtFpUIntSCode = '''
1007 vfpFlushToZero(Fpscr, FpOp1);
1008 VfpSavedState state = prepVfpFpscr(Fpscr);
1009 fesetround(FeRoundZero);
1010 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
1011 FpDest.uw = vfpFpSToFixed(FpOp1, false, false, 0);
1012 __asm__ __volatile__("" :: "m" (FpDest.uw));
1013 Fpscr = setVfpFpscr(Fpscr, state);
1014 '''

788 exec_output += PredOpExecute.subst(vcvtFpSIntDRIop);
789
790 vcvtFpUIntSCode = '''
791 vfpFlushToZero(Fpscr, FpOp1);
792 VfpSavedState state = prepVfpFpscr(Fpscr);
793 fesetround(FeRoundZero);
794 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
795 FpDest.uw = vfpFpSToFixed(FpOp1, false, false, 0);
796 __asm__ __volatile__("" :: "m" (FpDest.uw));
797 Fpscr = setVfpFpscr(Fpscr, state);
798 '''

1015 vcvtFpUIntSIop = InstObjParams("vcvt", "VcvtFpUIntS", "VfpRegRegOp",

799 vcvtFpUIntSIop = InstObjParams("vcvt", "VcvtFpUIntS", "FpRegRegOp",

1016 { "code": vcvtFpUIntSCode,
1017 "predicate_test": predicateTest }, [])

800 { "code": vcvtFpUIntSCode,
801 "predicate_test": predicateTest }, [])

1018 header_output += VfpRegRegOpDeclare.subst(vcvtFpUIntSIop);
1019 decoder_output += VfpRegRegOpConstructor.subst(vcvtFpUIntSIop);

802 header_output += FpRegRegOpDeclare.subst(vcvtFpUIntSIop);
803 decoder_output += FpRegRegOpConstructor.subst(vcvtFpUIntSIop);

1020 exec_output += PredOpExecute.subst(vcvtFpUIntSIop);
1021
1022 vcvtFpUIntDCode = '''
1023 IntDoubleUnion cOp1;
1024 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
1025 vfpFlushToZero(Fpscr, cOp1.fp);
1026 VfpSavedState state = prepVfpFpscr(Fpscr);
1027 fesetround(FeRoundZero);
1028 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp));
1029 uint64_t result = vfpFpDToFixed(cOp1.fp, false, false, 0);
1030 __asm__ __volatile__("" :: "m" (result));
1031 Fpscr = setVfpFpscr(Fpscr, state);
1032 FpDestP0.uw = result;
1033 '''

804 exec_output += PredOpExecute.subst(vcvtFpUIntSIop);
805
806 vcvtFpUIntDCode = '''
807 IntDoubleUnion cOp1;
808 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
809 vfpFlushToZero(Fpscr, cOp1.fp);
810 VfpSavedState state = prepVfpFpscr(Fpscr);
811 fesetround(FeRoundZero);
812 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp));
813 uint64_t result = vfpFpDToFixed(cOp1.fp, false, false, 0);
814 __asm__ __volatile__("" :: "m" (result));
815 Fpscr = setVfpFpscr(Fpscr, state);
816 FpDestP0.uw = result;
817 '''

1034 vcvtFpUIntDIop = InstObjParams("vcvt", "VcvtFpUIntD", "VfpRegRegOp",

818 vcvtFpUIntDIop = InstObjParams("vcvt", "VcvtFpUIntD", "FpRegRegOp",

1035 { "code": vcvtFpUIntDCode,
1036 "predicate_test": predicateTest }, [])

819 { "code": vcvtFpUIntDCode,
820 "predicate_test": predicateTest }, [])

1037 header_output += VfpRegRegOpDeclare.subst(vcvtFpUIntDIop);
1038 decoder_output += VfpRegRegOpConstructor.subst(vcvtFpUIntDIop);

821 header_output += FpRegRegOpDeclare.subst(vcvtFpUIntDIop);
822 decoder_output += FpRegRegOpConstructor.subst(vcvtFpUIntDIop);

1039 exec_output += PredOpExecute.subst(vcvtFpUIntDIop);
1040
1041 vcvtFpSIntSCode = '''
1042 vfpFlushToZero(Fpscr, FpOp1);
1043 VfpSavedState state = prepVfpFpscr(Fpscr);
1044 fesetround(FeRoundZero);
1045 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
1046 FpDest.sw = vfpFpSToFixed(FpOp1, true, false, 0);
1047 __asm__ __volatile__("" :: "m" (FpDest.sw));
1048 Fpscr = setVfpFpscr(Fpscr, state);
1049 '''

823 exec_output += PredOpExecute.subst(vcvtFpUIntDIop);
824
825 vcvtFpSIntSCode = '''
826 vfpFlushToZero(Fpscr, FpOp1);
827 VfpSavedState state = prepVfpFpscr(Fpscr);
828 fesetround(FeRoundZero);
829 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
830 FpDest.sw = vfpFpSToFixed(FpOp1, true, false, 0);
831 __asm__ __volatile__("" :: "m" (FpDest.sw));
832 Fpscr = setVfpFpscr(Fpscr, state);
833 '''

1050 vcvtFpSIntSIop = InstObjParams("vcvt", "VcvtFpSIntS", "VfpRegRegOp",

834 vcvtFpSIntSIop = InstObjParams("vcvt", "VcvtFpSIntS", "FpRegRegOp",

1051 { "code": vcvtFpSIntSCode,
1052 "predicate_test": predicateTest }, [])

835 { "code": vcvtFpSIntSCode,
836 "predicate_test": predicateTest }, [])

1053 header_output += VfpRegRegOpDeclare.subst(vcvtFpSIntSIop);
1054 decoder_output += VfpRegRegOpConstructor.subst(vcvtFpSIntSIop);

837 header_output += FpRegRegOpDeclare.subst(vcvtFpSIntSIop);
838 decoder_output += FpRegRegOpConstructor.subst(vcvtFpSIntSIop);

1055 exec_output += PredOpExecute.subst(vcvtFpSIntSIop);
1056
1057 vcvtFpSIntDCode = '''
1058 IntDoubleUnion cOp1;
1059 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
1060 vfpFlushToZero(Fpscr, cOp1.fp);
1061 VfpSavedState state = prepVfpFpscr(Fpscr);
1062 fesetround(FeRoundZero);
1063 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp));
1064 int64_t result = vfpFpDToFixed(cOp1.fp, true, false, 0);
1065 __asm__ __volatile__("" :: "m" (result));
1066 Fpscr = setVfpFpscr(Fpscr, state);
1067 FpDestP0.uw = result;
1068 '''

839 exec_output += PredOpExecute.subst(vcvtFpSIntSIop);
840
841 vcvtFpSIntDCode = '''
842 IntDoubleUnion cOp1;
843 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
844 vfpFlushToZero(Fpscr, cOp1.fp);
845 VfpSavedState state = prepVfpFpscr(Fpscr);
846 fesetround(FeRoundZero);
847 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp));
848 int64_t result = vfpFpDToFixed(cOp1.fp, true, false, 0);
849 __asm__ __volatile__("" :: "m" (result));
850 Fpscr = setVfpFpscr(Fpscr, state);
851 FpDestP0.uw = result;
852 '''

1069 vcvtFpSIntDIop = InstObjParams("vcvt", "VcvtFpSIntD", "VfpRegRegOp",

853 vcvtFpSIntDIop = InstObjParams("vcvt", "VcvtFpSIntD", "FpRegRegOp",

1070 { "code": vcvtFpSIntDCode,
1071 "predicate_test": predicateTest }, [])

854 { "code": vcvtFpSIntDCode,
855 "predicate_test": predicateTest }, [])

1072 header_output += VfpRegRegOpDeclare.subst(vcvtFpSIntDIop);
1073 decoder_output += VfpRegRegOpConstructor.subst(vcvtFpSIntDIop);

856 header_output += FpRegRegOpDeclare.subst(vcvtFpSIntDIop);
857 decoder_output += FpRegRegOpConstructor.subst(vcvtFpSIntDIop);

1074 exec_output += PredOpExecute.subst(vcvtFpSIntDIop);
1075
1076 vcvtFpSFpDCode = '''
1077 IntDoubleUnion cDest;
1078 vfpFlushToZero(Fpscr, FpOp1);
1079 VfpSavedState state = prepVfpFpscr(Fpscr);
1080 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));

858 exec_output += PredOpExecute.subst(vcvtFpSIntDIop);
859
860 vcvtFpSFpDCode = '''
861 IntDoubleUnion cDest;
862 vfpFlushToZero(Fpscr, FpOp1);
863 VfpSavedState state = prepVfpFpscr(Fpscr);
864 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));

1081 cDest.fp = FpOp1;

865 cDest.fp = fixFpSFpDDest(Fpscr, FpOp1);

1082 __asm__ __volatile__("" :: "m" (cDest.fp));
1083 Fpscr = setVfpFpscr(Fpscr, state);
1084 FpDestP0.uw = cDest.bits;
1085 FpDestP1.uw = cDest.bits >> 32;
1086 '''

866 __asm__ __volatile__("" :: "m" (cDest.fp));
867 Fpscr = setVfpFpscr(Fpscr, state);
868 FpDestP0.uw = cDest.bits;
869 FpDestP1.uw = cDest.bits >> 32;
870 '''

1087 vcvtFpSFpDIop = InstObjParams("vcvt", "VcvtFpSFpD", "VfpRegRegOp",

871 vcvtFpSFpDIop = InstObjParams("vcvt", "VcvtFpSFpD", "FpRegRegOp",

1088 { "code": vcvtFpSFpDCode,
1089 "predicate_test": predicateTest }, [])

872 { "code": vcvtFpSFpDCode,
873 "predicate_test": predicateTest }, [])

1090 header_output += VfpRegRegOpDeclare.subst(vcvtFpSFpDIop);
1091 decoder_output += VfpRegRegOpConstructor.subst(vcvtFpSFpDIop);

874 header_output += FpRegRegOpDeclare.subst(vcvtFpSFpDIop);
875 decoder_output += FpRegRegOpConstructor.subst(vcvtFpSFpDIop);

1092 exec_output += PredOpExecute.subst(vcvtFpSFpDIop);
1093
1094 vcvtFpDFpSCode = '''
1095 IntDoubleUnion cOp1;
1096 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
1097 vfpFlushToZero(Fpscr, cOp1.fp);
1098 VfpSavedState state = prepVfpFpscr(Fpscr);
1099 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp));
1100 FpDest = fixFpDFpSDest(Fpscr, cOp1.fp);
1101 __asm__ __volatile__("" :: "m" (FpDest));
1102 Fpscr = setVfpFpscr(Fpscr, state);
1103 '''

876 exec_output += PredOpExecute.subst(vcvtFpSFpDIop);
877
878 vcvtFpDFpSCode = '''
879 IntDoubleUnion cOp1;
880 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
881 vfpFlushToZero(Fpscr, cOp1.fp);
882 VfpSavedState state = prepVfpFpscr(Fpscr);
883 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp));
884 FpDest = fixFpDFpSDest(Fpscr, cOp1.fp);
885 __asm__ __volatile__("" :: "m" (FpDest));
886 Fpscr = setVfpFpscr(Fpscr, state);
887 '''

1104 vcvtFpDFpSIop = InstObjParams("vcvt", "VcvtFpDFpS", "VfpRegRegOp",

888 vcvtFpDFpSIop = InstObjParams("vcvt", "VcvtFpDFpS", "FpRegRegOp",

1105 { "code": vcvtFpDFpSCode,
1106 "predicate_test": predicateTest }, [])

889 { "code": vcvtFpDFpSCode,
890 "predicate_test": predicateTest }, [])

1107 header_output += VfpRegRegOpDeclare.subst(vcvtFpDFpSIop);
1108 decoder_output += VfpRegRegOpConstructor.subst(vcvtFpDFpSIop);

891 header_output += FpRegRegOpDeclare.subst(vcvtFpDFpSIop);
892 decoder_output += FpRegRegOpConstructor.subst(vcvtFpDFpSIop);

1109 exec_output += PredOpExecute.subst(vcvtFpDFpSIop);
1110
1111 vcmpSCode = '''
1112 vfpFlushToZero(Fpscr, FpDest, FpOp1);
1113 FPSCR fpscr = Fpscr;
1114 if (FpDest == FpOp1) {
1115 fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0;
1116 } else if (FpDest < FpOp1) {
1117 fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0;
1118 } else if (FpDest > FpOp1) {
1119 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0;
1120 } else {
1121 const uint32_t qnan = 0x7fc00000;

893 exec_output += PredOpExecute.subst(vcvtFpDFpSIop);
894
895 vcmpSCode = '''
896 vfpFlushToZero(Fpscr, FpDest, FpOp1);
897 FPSCR fpscr = Fpscr;
898 if (FpDest == FpOp1) {
899 fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0;
900 } else if (FpDest < FpOp1) {
901 fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0;
902 } else if (FpDest > FpOp1) {
903 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0;
904 } else {
905 const uint32_t qnan = 0x7fc00000;

1122 union
1123 {
1124 float fp;
1125 uint32_t bits;
1126 } cvtr;
1127 cvtr.fp = FpDest;

1128 const bool nan1 = std::isnan(FpDest);

906 const bool nan1 = std::isnan(FpDest);

1129 const bool signal1 = nan1 && ((cvtr.bits & qnan) != qnan);
1130 cvtr.fp = FpOp1;

907 const bool signal1 = nan1 && ((fpToBits(FpDest) & qnan) != qnan);

1131 const bool nan2 = std::isnan(FpOp1);

908 const bool nan2 = std::isnan(FpOp1);

1132 const bool signal2 = nan2 && ((cvtr.bits & qnan) != qnan);

909 const bool signal2 = nan2 && ((fpToBits(FpOp1) & qnan) != qnan);

1133 if (signal1 || signal2)
1134 fpscr.ioc = 1;
1135 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1;
1136 }
1137 Fpscr = fpscr;
1138 '''

910 if (signal1 || signal2)
911 fpscr.ioc = 1;
912 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1;
913 }
914 Fpscr = fpscr;
915 '''

1139 vcmpSIop = InstObjParams("vcmps", "VcmpS", "VfpRegRegOp",

916 vcmpSIop = InstObjParams("vcmps", "VcmpS", "FpRegRegOp",

1140 { "code": vcmpSCode,
1141 "predicate_test": predicateTest }, [])

917 { "code": vcmpSCode,
918 "predicate_test": predicateTest }, [])

1142 header_output += VfpRegRegOpDeclare.subst(vcmpSIop);
1143 decoder_output += VfpRegRegOpConstructor.subst(vcmpSIop);

919 header_output += FpRegRegOpDeclare.subst(vcmpSIop);
920 decoder_output += FpRegRegOpConstructor.subst(vcmpSIop);

1144 exec_output += PredOpExecute.subst(vcmpSIop);
1145
1146 vcmpDCode = '''
1147 IntDoubleUnion cOp1, cDest;
1148 cDest.bits = ((uint64_t)FpDestP0.uw | ((uint64_t)FpDestP1.uw << 32));
1149 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
1150 vfpFlushToZero(Fpscr, cDest.fp, cOp1.fp);
1151 FPSCR fpscr = Fpscr;

--- 10 unchanged lines hidden (view full) ---

1162 const bool nan2 = std::isnan(cOp1.fp);
1163 const bool signal2 = nan2 && ((cOp1.bits & qnan) != qnan);
1164 if (signal1 || signal2)
1165 fpscr.ioc = 1;
1166 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1;
1167 }
1168 Fpscr = fpscr;
1169 '''

921 exec_output += PredOpExecute.subst(vcmpSIop);
922
923 vcmpDCode = '''
924 IntDoubleUnion cOp1, cDest;
925 cDest.bits = ((uint64_t)FpDestP0.uw | ((uint64_t)FpDestP1.uw << 32));
926 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
927 vfpFlushToZero(Fpscr, cDest.fp, cOp1.fp);
928 FPSCR fpscr = Fpscr;

--- 10 unchanged lines hidden (view full) ---

939 const bool nan2 = std::isnan(cOp1.fp);
940 const bool signal2 = nan2 && ((cOp1.bits & qnan) != qnan);
941 if (signal1 || signal2)
942 fpscr.ioc = 1;
943 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1;
944 }
945 Fpscr = fpscr;
946 '''

1170 vcmpDIop = InstObjParams("vcmpd", "VcmpD", "VfpRegRegOp",

947 vcmpDIop = InstObjParams("vcmpd", "VcmpD", "FpRegRegOp",

1171 { "code": vcmpDCode,
1172 "predicate_test": predicateTest }, [])

948 { "code": vcmpDCode,
949 "predicate_test": predicateTest }, [])

1173 header_output += VfpRegRegOpDeclare.subst(vcmpDIop);
1174 decoder_output += VfpRegRegOpConstructor.subst(vcmpDIop);

950 header_output += FpRegRegOpDeclare.subst(vcmpDIop);
951 decoder_output += FpRegRegOpConstructor.subst(vcmpDIop);

1175 exec_output += PredOpExecute.subst(vcmpDIop);
1176
1177 vcmpZeroSCode = '''
1178 vfpFlushToZero(Fpscr, FpDest);
1179 FPSCR fpscr = Fpscr;
1180 // This only handles imm == 0 for now.
1181 assert(imm == 0);
1182 if (FpDest == imm) {
1183 fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0;
1184 } else if (FpDest < imm) {
1185 fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0;
1186 } else if (FpDest > imm) {
1187 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0;
1188 } else {
1189 const uint32_t qnan = 0x7fc00000;

952 exec_output += PredOpExecute.subst(vcmpDIop);
953
954 vcmpZeroSCode = '''
955 vfpFlushToZero(Fpscr, FpDest);
956 FPSCR fpscr = Fpscr;
957 // This only handles imm == 0 for now.
958 assert(imm == 0);
959 if (FpDest == imm) {
960 fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0;
961 } else if (FpDest < imm) {
962 fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0;
963 } else if (FpDest > imm) {
964 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0;
965 } else {
966 const uint32_t qnan = 0x7fc00000;

1190 union
1191 {
1192 float fp;
1193 uint32_t bits;
1194 } cvtr;
1195 cvtr.fp = FpDest;

1196 const bool nan = std::isnan(FpDest);

967 const bool nan = std::isnan(FpDest);

1197 const bool signal = nan && ((cvtr.bits & qnan) != qnan);

968 const bool signal = nan && ((fpToBits(FpDest) & qnan) != qnan);

1198 if (signal)
1199 fpscr.ioc = 1;
1200 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1;
1201 }
1202 Fpscr = fpscr;
1203 '''

969 if (signal)
970 fpscr.ioc = 1;
971 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1;
972 }
973 Fpscr = fpscr;
974 '''

1204 vcmpZeroSIop = InstObjParams("vcmpZeros", "VcmpZeroS", "VfpRegImmOp",

975 vcmpZeroSIop = InstObjParams("vcmpZeros", "VcmpZeroS", "FpRegImmOp",

1205 { "code": vcmpZeroSCode,
1206 "predicate_test": predicateTest }, [])

976 { "code": vcmpZeroSCode,
977 "predicate_test": predicateTest }, [])

1207 header_output += VfpRegImmOpDeclare.subst(vcmpZeroSIop);
1208 decoder_output += VfpRegImmOpConstructor.subst(vcmpZeroSIop);

978 header_output += FpRegImmOpDeclare.subst(vcmpZeroSIop);
979 decoder_output += FpRegImmOpConstructor.subst(vcmpZeroSIop);

1209 exec_output += PredOpExecute.subst(vcmpZeroSIop);
1210
1211 vcmpZeroDCode = '''
1212 IntDoubleUnion cDest;
1213 // This only handles imm == 0 for now.
1214 assert(imm == 0);
1215 cDest.bits = ((uint64_t)FpDestP0.uw | ((uint64_t)FpDestP1.uw << 32));
1216 vfpFlushToZero(Fpscr, cDest.fp);

--- 9 unchanged lines hidden (view full) ---

1226 const bool nan = std::isnan(cDest.fp);
1227 const bool signal = nan && ((cDest.bits & qnan) != qnan);
1228 if (signal)
1229 fpscr.ioc = 1;
1230 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1;
1231 }
1232 Fpscr = fpscr;
1233 '''

980 exec_output += PredOpExecute.subst(vcmpZeroSIop);
981
982 vcmpZeroDCode = '''
983 IntDoubleUnion cDest;
984 // This only handles imm == 0 for now.
985 assert(imm == 0);
986 cDest.bits = ((uint64_t)FpDestP0.uw | ((uint64_t)FpDestP1.uw << 32));
987 vfpFlushToZero(Fpscr, cDest.fp);

--- 9 unchanged lines hidden (view full) ---

997 const bool nan = std::isnan(cDest.fp);
998 const bool signal = nan && ((cDest.bits & qnan) != qnan);
999 if (signal)
1000 fpscr.ioc = 1;
1001 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1;
1002 }
1003 Fpscr = fpscr;
1004 '''

1234 vcmpZeroDIop = InstObjParams("vcmpZerod", "VcmpZeroD", "VfpRegImmOp",

1005 vcmpZeroDIop = InstObjParams("vcmpZerod", "VcmpZeroD", "FpRegImmOp",

1235 { "code": vcmpZeroDCode,
1236 "predicate_test": predicateTest }, [])

1006 { "code": vcmpZeroDCode,
1007 "predicate_test": predicateTest }, [])

1237 header_output += VfpRegImmOpDeclare.subst(vcmpZeroDIop);
1238 decoder_output += VfpRegImmOpConstructor.subst(vcmpZeroDIop);

1008 header_output += FpRegImmOpDeclare.subst(vcmpZeroDIop);
1009 decoder_output += FpRegImmOpConstructor.subst(vcmpZeroDIop);

1239 exec_output += PredOpExecute.subst(vcmpZeroDIop);
1240
1241 vcmpeSCode = '''
1242 vfpFlushToZero(Fpscr, FpDest, FpOp1);
1243 FPSCR fpscr = Fpscr;
1244 if (FpDest == FpOp1) {
1245 fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0;
1246 } else if (FpDest < FpOp1) {
1247 fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0;
1248 } else if (FpDest > FpOp1) {
1249 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0;
1250 } else {
1251 fpscr.ioc = 1;
1252 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1;
1253 }
1254 Fpscr = fpscr;
1255 '''

1010 exec_output += PredOpExecute.subst(vcmpZeroDIop);
1011
1012 vcmpeSCode = '''
1013 vfpFlushToZero(Fpscr, FpDest, FpOp1);
1014 FPSCR fpscr = Fpscr;
1015 if (FpDest == FpOp1) {
1016 fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0;
1017 } else if (FpDest < FpOp1) {
1018 fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0;
1019 } else if (FpDest > FpOp1) {
1020 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0;
1021 } else {
1022 fpscr.ioc = 1;
1023 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1;
1024 }
1025 Fpscr = fpscr;
1026 '''

1256 vcmpeSIop = InstObjParams("vcmpes", "VcmpeS", "VfpRegRegOp",

1027 vcmpeSIop = InstObjParams("vcmpes", "VcmpeS", "FpRegRegOp",

1257 { "code": vcmpeSCode,
1258 "predicate_test": predicateTest }, [])

1028 { "code": vcmpeSCode,
1029 "predicate_test": predicateTest }, [])

1259 header_output += VfpRegRegOpDeclare.subst(vcmpeSIop);
1260 decoder_output += VfpRegRegOpConstructor.subst(vcmpeSIop);

1030 header_output += FpRegRegOpDeclare.subst(vcmpeSIop);
1031 decoder_output += FpRegRegOpConstructor.subst(vcmpeSIop);

1261 exec_output += PredOpExecute.subst(vcmpeSIop);
1262
1263 vcmpeDCode = '''
1264 IntDoubleUnion cOp1, cDest;
1265 cDest.bits = ((uint64_t)FpDestP0.uw | ((uint64_t)FpDestP1.uw << 32));
1266 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
1267 vfpFlushToZero(Fpscr, cDest.fp, cOp1.fp);
1268 FPSCR fpscr = Fpscr;

--- 4 unchanged lines hidden (view full) ---

1273 } else if (cDest.fp > cOp1.fp) {
1274 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0;
1275 } else {
1276 fpscr.ioc = 1;
1277 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1;
1278 }
1279 Fpscr = fpscr;
1280 '''

1032 exec_output += PredOpExecute.subst(vcmpeSIop);
1033
1034 vcmpeDCode = '''
1035 IntDoubleUnion cOp1, cDest;
1036 cDest.bits = ((uint64_t)FpDestP0.uw | ((uint64_t)FpDestP1.uw << 32));
1037 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
1038 vfpFlushToZero(Fpscr, cDest.fp, cOp1.fp);
1039 FPSCR fpscr = Fpscr;

--- 4 unchanged lines hidden (view full) ---

1044 } else if (cDest.fp > cOp1.fp) {
1045 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0;
1046 } else {
1047 fpscr.ioc = 1;
1048 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1;
1049 }
1050 Fpscr = fpscr;
1051 '''

1281 vcmpeDIop = InstObjParams("vcmped", "VcmpeD", "VfpRegRegOp",

1052 vcmpeDIop = InstObjParams("vcmped", "VcmpeD", "FpRegRegOp",

1282 { "code": vcmpeDCode,
1283 "predicate_test": predicateTest }, [])

1053 { "code": vcmpeDCode,
1054 "predicate_test": predicateTest }, [])

1284 header_output += VfpRegRegOpDeclare.subst(vcmpeDIop);
1285 decoder_output += VfpRegRegOpConstructor.subst(vcmpeDIop);

1055 header_output += FpRegRegOpDeclare.subst(vcmpeDIop);
1056 decoder_output += FpRegRegOpConstructor.subst(vcmpeDIop);

1286 exec_output += PredOpExecute.subst(vcmpeDIop);
1287
1288 vcmpeZeroSCode = '''
1289 vfpFlushToZero(Fpscr, FpDest);
1290 FPSCR fpscr = Fpscr;
1291 if (FpDest == imm) {
1292 fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0;
1293 } else if (FpDest < imm) {
1294 fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0;
1295 } else if (FpDest > imm) {
1296 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0;
1297 } else {
1298 fpscr.ioc = 1;
1299 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1;
1300 }
1301 Fpscr = fpscr;
1302 '''

1057 exec_output += PredOpExecute.subst(vcmpeDIop);
1058
1059 vcmpeZeroSCode = '''
1060 vfpFlushToZero(Fpscr, FpDest);
1061 FPSCR fpscr = Fpscr;
1062 if (FpDest == imm) {
1063 fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0;
1064 } else if (FpDest < imm) {
1065 fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0;
1066 } else if (FpDest > imm) {
1067 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0;
1068 } else {
1069 fpscr.ioc = 1;
1070 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1;
1071 }
1072 Fpscr = fpscr;
1073 '''

1303 vcmpeZeroSIop = InstObjParams("vcmpeZeros", "VcmpeZeroS", "VfpRegImmOp",

1074 vcmpeZeroSIop = InstObjParams("vcmpeZeros", "VcmpeZeroS", "FpRegImmOp",

1304 { "code": vcmpeZeroSCode,
1305 "predicate_test": predicateTest }, [])

1075 { "code": vcmpeZeroSCode,
1076 "predicate_test": predicateTest }, [])

1306 header_output += VfpRegImmOpDeclare.subst(vcmpeZeroSIop);
1307 decoder_output += VfpRegImmOpConstructor.subst(vcmpeZeroSIop);

1077 header_output += FpRegImmOpDeclare.subst(vcmpeZeroSIop);
1078 decoder_output += FpRegImmOpConstructor.subst(vcmpeZeroSIop);

1308 exec_output += PredOpExecute.subst(vcmpeZeroSIop);
1309
1310 vcmpeZeroDCode = '''
1311 IntDoubleUnion cDest;
1312 cDest.bits = ((uint64_t)FpDestP0.uw | ((uint64_t)FpDestP1.uw << 32));
1313 vfpFlushToZero(Fpscr, cDest.fp);
1314 FPSCR fpscr = Fpscr;
1315 if (cDest.fp == imm) {
1316 fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0;
1317 } else if (cDest.fp < imm) {
1318 fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0;
1319 } else if (cDest.fp > imm) {
1320 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0;
1321 } else {
1322 fpscr.ioc = 1;
1323 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1;
1324 }
1325 Fpscr = fpscr;
1326 '''

1079 exec_output += PredOpExecute.subst(vcmpeZeroSIop);
1080
1081 vcmpeZeroDCode = '''
1082 IntDoubleUnion cDest;
1083 cDest.bits = ((uint64_t)FpDestP0.uw | ((uint64_t)FpDestP1.uw << 32));
1084 vfpFlushToZero(Fpscr, cDest.fp);
1085 FPSCR fpscr = Fpscr;
1086 if (cDest.fp == imm) {
1087 fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0;
1088 } else if (cDest.fp < imm) {
1089 fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0;
1090 } else if (cDest.fp > imm) {
1091 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0;
1092 } else {
1093 fpscr.ioc = 1;
1094 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1;
1095 }
1096 Fpscr = fpscr;
1097 '''

1327 vcmpeZeroDIop = InstObjParams("vcmpeZerod", "VcmpeZeroD", "VfpRegImmOp",

1098 vcmpeZeroDIop = InstObjParams("vcmpeZerod", "VcmpeZeroD", "FpRegImmOp",

1328 { "code": vcmpeZeroDCode,
1329 "predicate_test": predicateTest }, [])

1099 { "code": vcmpeZeroDCode,
1100 "predicate_test": predicateTest }, [])

1330 header_output += VfpRegImmOpDeclare.subst(vcmpeZeroDIop);
1331 decoder_output += VfpRegImmOpConstructor.subst(vcmpeZeroDIop);

1101 header_output += FpRegImmOpDeclare.subst(vcmpeZeroDIop);
1102 decoder_output += FpRegImmOpConstructor.subst(vcmpeZeroDIop);

1332 exec_output += PredOpExecute.subst(vcmpeZeroDIop);
1333}};
1334
1335let {{
1336
1337 header_output = ""
1338 decoder_output = ""
1339 exec_output = ""
1340
1341 vcvtFpSFixedSCode = '''
1342 vfpFlushToZero(Fpscr, FpOp1);
1343 VfpSavedState state = prepVfpFpscr(Fpscr);
1344 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
1345 FpDest.sw = vfpFpSToFixed(FpOp1, true, false, imm);
1346 __asm__ __volatile__("" :: "m" (FpDest.sw));
1347 Fpscr = setVfpFpscr(Fpscr, state);
1348 '''

1103 exec_output += PredOpExecute.subst(vcmpeZeroDIop);
1104}};
1105
1106let {{
1107
1108 header_output = ""
1109 decoder_output = ""
1110 exec_output = ""
1111
1112 vcvtFpSFixedSCode = '''
1113 vfpFlushToZero(Fpscr, FpOp1);
1114 VfpSavedState state = prepVfpFpscr(Fpscr);
1115 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
1116 FpDest.sw = vfpFpSToFixed(FpOp1, true, false, imm);
1117 __asm__ __volatile__("" :: "m" (FpDest.sw));
1118 Fpscr = setVfpFpscr(Fpscr, state);
1119 '''

1349 vcvtFpSFixedSIop = InstObjParams("vcvt", "VcvtFpSFixedS", "VfpRegRegImmOp",

1120 vcvtFpSFixedSIop = InstObjParams("vcvt", "VcvtFpSFixedS", "FpRegRegImmOp",

1350 { "code": vcvtFpSFixedSCode,
1351 "predicate_test": predicateTest }, [])

1121 { "code": vcvtFpSFixedSCode,
1122 "predicate_test": predicateTest }, [])

1352 header_output += VfpRegRegImmOpDeclare.subst(vcvtFpSFixedSIop);
1353 decoder_output += VfpRegRegImmOpConstructor.subst(vcvtFpSFixedSIop);

1123 header_output += FpRegRegImmOpDeclare.subst(vcvtFpSFixedSIop);
1124 decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpSFixedSIop);

1354 exec_output += PredOpExecute.subst(vcvtFpSFixedSIop);
1355
1356 vcvtFpSFixedDCode = '''
1357 IntDoubleUnion cOp1;
1358 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
1359 vfpFlushToZero(Fpscr, cOp1.fp);
1360 VfpSavedState state = prepVfpFpscr(Fpscr);
1361 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp));
1362 uint64_t mid = vfpFpDToFixed(cOp1.fp, true, false, imm);
1363 __asm__ __volatile__("" :: "m" (mid));
1364 Fpscr = setVfpFpscr(Fpscr, state);
1365 FpDestP0.uw = mid;
1366 FpDestP1.uw = mid >> 32;
1367 '''

1125 exec_output += PredOpExecute.subst(vcvtFpSFixedSIop);
1126
1127 vcvtFpSFixedDCode = '''
1128 IntDoubleUnion cOp1;
1129 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
1130 vfpFlushToZero(Fpscr, cOp1.fp);
1131 VfpSavedState state = prepVfpFpscr(Fpscr);
1132 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp));
1133 uint64_t mid = vfpFpDToFixed(cOp1.fp, true, false, imm);
1134 __asm__ __volatile__("" :: "m" (mid));
1135 Fpscr = setVfpFpscr(Fpscr, state);
1136 FpDestP0.uw = mid;
1137 FpDestP1.uw = mid >> 32;
1138 '''

1368 vcvtFpSFixedDIop = InstObjParams("vcvt", "VcvtFpSFixedD", "VfpRegRegImmOp",

1139 vcvtFpSFixedDIop = InstObjParams("vcvt", "VcvtFpSFixedD", "FpRegRegImmOp",

1369 { "code": vcvtFpSFixedDCode,
1370 "predicate_test": predicateTest }, [])

1140 { "code": vcvtFpSFixedDCode,
1141 "predicate_test": predicateTest }, [])

1371 header_output += VfpRegRegImmOpDeclare.subst(vcvtFpSFixedDIop);
1372 decoder_output += VfpRegRegImmOpConstructor.subst(vcvtFpSFixedDIop);

1142 header_output += FpRegRegImmOpDeclare.subst(vcvtFpSFixedDIop);
1143 decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpSFixedDIop);

1373 exec_output += PredOpExecute.subst(vcvtFpSFixedDIop);
1374
1375 vcvtFpUFixedSCode = '''
1376 vfpFlushToZero(Fpscr, FpOp1);
1377 VfpSavedState state = prepVfpFpscr(Fpscr);
1378 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
1379 FpDest.uw = vfpFpSToFixed(FpOp1, false, false, imm);
1380 __asm__ __volatile__("" :: "m" (FpDest.uw));
1381 Fpscr = setVfpFpscr(Fpscr, state);
1382 '''

1144 exec_output += PredOpExecute.subst(vcvtFpSFixedDIop);
1145
1146 vcvtFpUFixedSCode = '''
1147 vfpFlushToZero(Fpscr, FpOp1);
1148 VfpSavedState state = prepVfpFpscr(Fpscr);
1149 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
1150 FpDest.uw = vfpFpSToFixed(FpOp1, false, false, imm);
1151 __asm__ __volatile__("" :: "m" (FpDest.uw));
1152 Fpscr = setVfpFpscr(Fpscr, state);
1153 '''

1383 vcvtFpUFixedSIop = InstObjParams("vcvt", "VcvtFpUFixedS", "VfpRegRegImmOp",

1154 vcvtFpUFixedSIop = InstObjParams("vcvt", "VcvtFpUFixedS", "FpRegRegImmOp",

1384 { "code": vcvtFpUFixedSCode,
1385 "predicate_test": predicateTest }, [])

1155 { "code": vcvtFpUFixedSCode,
1156 "predicate_test": predicateTest }, [])

1386 header_output += VfpRegRegImmOpDeclare.subst(vcvtFpUFixedSIop);
1387 decoder_output += VfpRegRegImmOpConstructor.subst(vcvtFpUFixedSIop);

1157 header_output += FpRegRegImmOpDeclare.subst(vcvtFpUFixedSIop);
1158 decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpUFixedSIop);

1388 exec_output += PredOpExecute.subst(vcvtFpUFixedSIop);
1389
1390 vcvtFpUFixedDCode = '''
1391 IntDoubleUnion cOp1;
1392 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
1393 vfpFlushToZero(Fpscr, cOp1.fp);
1394 VfpSavedState state = prepVfpFpscr(Fpscr);
1395 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp));
1396 uint64_t mid = vfpFpDToFixed(cOp1.fp, false, false, imm);
1397 __asm__ __volatile__("" :: "m" (mid));
1398 Fpscr = setVfpFpscr(Fpscr, state);
1399 FpDestP0.uw = mid;
1400 FpDestP1.uw = mid >> 32;
1401 '''

1159 exec_output += PredOpExecute.subst(vcvtFpUFixedSIop);
1160
1161 vcvtFpUFixedDCode = '''
1162 IntDoubleUnion cOp1;
1163 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
1164 vfpFlushToZero(Fpscr, cOp1.fp);
1165 VfpSavedState state = prepVfpFpscr(Fpscr);
1166 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp));
1167 uint64_t mid = vfpFpDToFixed(cOp1.fp, false, false, imm);
1168 __asm__ __volatile__("" :: "m" (mid));
1169 Fpscr = setVfpFpscr(Fpscr, state);
1170 FpDestP0.uw = mid;
1171 FpDestP1.uw = mid >> 32;
1172 '''

1402 vcvtFpUFixedDIop = InstObjParams("vcvt", "VcvtFpUFixedD", "VfpRegRegImmOp",

1173 vcvtFpUFixedDIop = InstObjParams("vcvt", "VcvtFpUFixedD", "FpRegRegImmOp",

1403 { "code": vcvtFpUFixedDCode,
1404 "predicate_test": predicateTest }, [])

1174 { "code": vcvtFpUFixedDCode,
1175 "predicate_test": predicateTest }, [])

1405 header_output += VfpRegRegImmOpDeclare.subst(vcvtFpUFixedDIop);
1406 decoder_output += VfpRegRegImmOpConstructor.subst(vcvtFpUFixedDIop);

1176 header_output += FpRegRegImmOpDeclare.subst(vcvtFpUFixedDIop);
1177 decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpUFixedDIop);

1407 exec_output += PredOpExecute.subst(vcvtFpUFixedDIop);
1408
1409 vcvtSFixedFpSCode = '''
1410 VfpSavedState state = prepVfpFpscr(Fpscr);
1411 __asm__ __volatile__("" : "=m" (FpOp1.sw) : "m" (FpOp1.sw));
1412 FpDest = vfpSFixedToFpS(Fpscr, FpOp1.sw, false, imm);
1413 __asm__ __volatile__("" :: "m" (FpDest));
1414 Fpscr = setVfpFpscr(Fpscr, state);
1415 '''

1178 exec_output += PredOpExecute.subst(vcvtFpUFixedDIop);
1179
1180 vcvtSFixedFpSCode = '''
1181 VfpSavedState state = prepVfpFpscr(Fpscr);
1182 __asm__ __volatile__("" : "=m" (FpOp1.sw) : "m" (FpOp1.sw));
1183 FpDest = vfpSFixedToFpS(Fpscr, FpOp1.sw, false, imm);
1184 __asm__ __volatile__("" :: "m" (FpDest));
1185 Fpscr = setVfpFpscr(Fpscr, state);
1186 '''

1416 vcvtSFixedFpSIop = InstObjParams("vcvt", "VcvtSFixedFpS", "VfpRegRegImmOp",

1187 vcvtSFixedFpSIop = InstObjParams("vcvt", "VcvtSFixedFpS", "FpRegRegImmOp",

1417 { "code": vcvtSFixedFpSCode,
1418 "predicate_test": predicateTest }, [])

1188 { "code": vcvtSFixedFpSCode,
1189 "predicate_test": predicateTest }, [])

1419 header_output += VfpRegRegImmOpDeclare.subst(vcvtSFixedFpSIop);
1420 decoder_output += VfpRegRegImmOpConstructor.subst(vcvtSFixedFpSIop);

1190 header_output += FpRegRegImmOpDeclare.subst(vcvtSFixedFpSIop);
1191 decoder_output += FpRegRegImmOpConstructor.subst(vcvtSFixedFpSIop);

1421 exec_output += PredOpExecute.subst(vcvtSFixedFpSIop);
1422
1423 vcvtSFixedFpDCode = '''
1424 IntDoubleUnion cDest;
1425 uint64_t mid = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
1426 VfpSavedState state = prepVfpFpscr(Fpscr);
1427 __asm__ __volatile__("" : "=m" (mid) : "m" (mid));
1428 cDest.fp = vfpSFixedToFpD(Fpscr, mid, false, imm);
1429 __asm__ __volatile__("" :: "m" (cDest.fp));
1430 Fpscr = setVfpFpscr(Fpscr, state);
1431 FpDestP0.uw = cDest.bits;
1432 FpDestP1.uw = cDest.bits >> 32;
1433 '''

1192 exec_output += PredOpExecute.subst(vcvtSFixedFpSIop);
1193
1194 vcvtSFixedFpDCode = '''
1195 IntDoubleUnion cDest;
1196 uint64_t mid = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
1197 VfpSavedState state = prepVfpFpscr(Fpscr);
1198 __asm__ __volatile__("" : "=m" (mid) : "m" (mid));
1199 cDest.fp = vfpSFixedToFpD(Fpscr, mid, false, imm);
1200 __asm__ __volatile__("" :: "m" (cDest.fp));
1201 Fpscr = setVfpFpscr(Fpscr, state);
1202 FpDestP0.uw = cDest.bits;
1203 FpDestP1.uw = cDest.bits >> 32;
1204 '''

1434 vcvtSFixedFpDIop = InstObjParams("vcvt", "VcvtSFixedFpD", "VfpRegRegImmOp",

1205 vcvtSFixedFpDIop = InstObjParams("vcvt", "VcvtSFixedFpD", "FpRegRegImmOp",

1435 { "code": vcvtSFixedFpDCode,
1436 "predicate_test": predicateTest }, [])

1206 { "code": vcvtSFixedFpDCode,
1207 "predicate_test": predicateTest }, [])

1437 header_output += VfpRegRegImmOpDeclare.subst(vcvtSFixedFpDIop);
1438 decoder_output += VfpRegRegImmOpConstructor.subst(vcvtSFixedFpDIop);

1208 header_output += FpRegRegImmOpDeclare.subst(vcvtSFixedFpDIop);
1209 decoder_output += FpRegRegImmOpConstructor.subst(vcvtSFixedFpDIop);

1439 exec_output += PredOpExecute.subst(vcvtSFixedFpDIop);
1440
1441 vcvtUFixedFpSCode = '''
1442 VfpSavedState state = prepVfpFpscr(Fpscr);
1443 __asm__ __volatile__("" : "=m" (FpOp1.uw) : "m" (FpOp1.uw));
1444 FpDest = vfpUFixedToFpS(Fpscr, FpOp1.uw, false, imm);
1445 __asm__ __volatile__("" :: "m" (FpDest));
1446 Fpscr = setVfpFpscr(Fpscr, state);
1447 '''

1210 exec_output += PredOpExecute.subst(vcvtSFixedFpDIop);
1211
1212 vcvtUFixedFpSCode = '''
1213 VfpSavedState state = prepVfpFpscr(Fpscr);
1214 __asm__ __volatile__("" : "=m" (FpOp1.uw) : "m" (FpOp1.uw));
1215 FpDest = vfpUFixedToFpS(Fpscr, FpOp1.uw, false, imm);
1216 __asm__ __volatile__("" :: "m" (FpDest));
1217 Fpscr = setVfpFpscr(Fpscr, state);
1218 '''

1448 vcvtUFixedFpSIop = InstObjParams("vcvt", "VcvtUFixedFpS", "VfpRegRegImmOp",

1219 vcvtUFixedFpSIop = InstObjParams("vcvt", "VcvtUFixedFpS", "FpRegRegImmOp",

1449 { "code": vcvtUFixedFpSCode,
1450 "predicate_test": predicateTest }, [])

1220 { "code": vcvtUFixedFpSCode,
1221 "predicate_test": predicateTest }, [])

1451 header_output += VfpRegRegImmOpDeclare.subst(vcvtUFixedFpSIop);
1452 decoder_output += VfpRegRegImmOpConstructor.subst(vcvtUFixedFpSIop);

1222 header_output += FpRegRegImmOpDeclare.subst(vcvtUFixedFpSIop);
1223 decoder_output += FpRegRegImmOpConstructor.subst(vcvtUFixedFpSIop);

1453 exec_output += PredOpExecute.subst(vcvtUFixedFpSIop);
1454
1455 vcvtUFixedFpDCode = '''
1456 IntDoubleUnion cDest;
1457 uint64_t mid = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
1458 VfpSavedState state = prepVfpFpscr(Fpscr);
1459 __asm__ __volatile__("" : "=m" (mid) : "m" (mid));
1460 cDest.fp = vfpUFixedToFpD(Fpscr, mid, false, imm);
1461 __asm__ __volatile__("" :: "m" (cDest.fp));
1462 Fpscr = setVfpFpscr(Fpscr, state);
1463 FpDestP0.uw = cDest.bits;
1464 FpDestP1.uw = cDest.bits >> 32;
1465 '''

1224 exec_output += PredOpExecute.subst(vcvtUFixedFpSIop);
1225
1226 vcvtUFixedFpDCode = '''
1227 IntDoubleUnion cDest;
1228 uint64_t mid = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
1229 VfpSavedState state = prepVfpFpscr(Fpscr);
1230 __asm__ __volatile__("" : "=m" (mid) : "m" (mid));
1231 cDest.fp = vfpUFixedToFpD(Fpscr, mid, false, imm);
1232 __asm__ __volatile__("" :: "m" (cDest.fp));
1233 Fpscr = setVfpFpscr(Fpscr, state);
1234 FpDestP0.uw = cDest.bits;
1235 FpDestP1.uw = cDest.bits >> 32;
1236 '''

1466 vcvtUFixedFpDIop = InstObjParams("vcvt", "VcvtUFixedFpD", "VfpRegRegImmOp",

1237 vcvtUFixedFpDIop = InstObjParams("vcvt", "VcvtUFixedFpD", "FpRegRegImmOp",

1467 { "code": vcvtUFixedFpDCode,
1468 "predicate_test": predicateTest }, [])

1238 { "code": vcvtUFixedFpDCode,
1239 "predicate_test": predicateTest }, [])

1469 header_output += VfpRegRegImmOpDeclare.subst(vcvtUFixedFpDIop);
1470 decoder_output += VfpRegRegImmOpConstructor.subst(vcvtUFixedFpDIop);

1240 header_output += FpRegRegImmOpDeclare.subst(vcvtUFixedFpDIop);
1241 decoder_output += FpRegRegImmOpConstructor.subst(vcvtUFixedFpDIop);

1471 exec_output += PredOpExecute.subst(vcvtUFixedFpDIop);
1472
1473 vcvtFpSHFixedSCode = '''
1474 vfpFlushToZero(Fpscr, FpOp1);
1475 VfpSavedState state = prepVfpFpscr(Fpscr);
1476 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
1477 FpDest.sh = vfpFpSToFixed(FpOp1, true, true, imm);
1478 __asm__ __volatile__("" :: "m" (FpDest.sh));
1479 Fpscr = setVfpFpscr(Fpscr, state);
1480 '''
1481 vcvtFpSHFixedSIop = InstObjParams("vcvt", "VcvtFpSHFixedS",

1242 exec_output += PredOpExecute.subst(vcvtUFixedFpDIop);
1243
1244 vcvtFpSHFixedSCode = '''
1245 vfpFlushToZero(Fpscr, FpOp1);
1246 VfpSavedState state = prepVfpFpscr(Fpscr);
1247 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
1248 FpDest.sh = vfpFpSToFixed(FpOp1, true, true, imm);
1249 __asm__ __volatile__("" :: "m" (FpDest.sh));
1250 Fpscr = setVfpFpscr(Fpscr, state);
1251 '''
1252 vcvtFpSHFixedSIop = InstObjParams("vcvt", "VcvtFpSHFixedS",

1482 "VfpRegRegImmOp",

1253 "FpRegRegImmOp",

1483 { "code": vcvtFpSHFixedSCode,
1484 "predicate_test": predicateTest }, [])

1254 { "code": vcvtFpSHFixedSCode,
1255 "predicate_test": predicateTest }, [])

1485 header_output += VfpRegRegImmOpDeclare.subst(vcvtFpSHFixedSIop);
1486 decoder_output += VfpRegRegImmOpConstructor.subst(vcvtFpSHFixedSIop);

1256 header_output += FpRegRegImmOpDeclare.subst(vcvtFpSHFixedSIop);
1257 decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpSHFixedSIop);

1487 exec_output += PredOpExecute.subst(vcvtFpSHFixedSIop);
1488
1489 vcvtFpSHFixedDCode = '''
1490 IntDoubleUnion cOp1;
1491 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
1492 vfpFlushToZero(Fpscr, cOp1.fp);
1493 VfpSavedState state = prepVfpFpscr(Fpscr);
1494 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp));
1495 uint64_t result = vfpFpDToFixed(cOp1.fp, true, true, imm);
1496 __asm__ __volatile__("" :: "m" (result));
1497 Fpscr = setVfpFpscr(Fpscr, state);
1498 FpDestP0.uw = result;
1499 FpDestP1.uw = result >> 32;
1500 '''
1501 vcvtFpSHFixedDIop = InstObjParams("vcvt", "VcvtFpSHFixedD",

1258 exec_output += PredOpExecute.subst(vcvtFpSHFixedSIop);
1259
1260 vcvtFpSHFixedDCode = '''
1261 IntDoubleUnion cOp1;
1262 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
1263 vfpFlushToZero(Fpscr, cOp1.fp);
1264 VfpSavedState state = prepVfpFpscr(Fpscr);
1265 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp));
1266 uint64_t result = vfpFpDToFixed(cOp1.fp, true, true, imm);
1267 __asm__ __volatile__("" :: "m" (result));
1268 Fpscr = setVfpFpscr(Fpscr, state);
1269 FpDestP0.uw = result;
1270 FpDestP1.uw = result >> 32;
1271 '''
1272 vcvtFpSHFixedDIop = InstObjParams("vcvt", "VcvtFpSHFixedD",

1502 "VfpRegRegImmOp",

1273 "FpRegRegImmOp",

1503 { "code": vcvtFpSHFixedDCode,
1504 "predicate_test": predicateTest }, [])

1274 { "code": vcvtFpSHFixedDCode,
1275 "predicate_test": predicateTest }, [])

1505 header_output += VfpRegRegImmOpDeclare.subst(vcvtFpSHFixedDIop);
1506 decoder_output += VfpRegRegImmOpConstructor.subst(vcvtFpSHFixedDIop);

1276 header_output += FpRegRegImmOpDeclare.subst(vcvtFpSHFixedDIop);
1277 decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpSHFixedDIop);

1507 exec_output += PredOpExecute.subst(vcvtFpSHFixedDIop);
1508
1509 vcvtFpUHFixedSCode = '''
1510 vfpFlushToZero(Fpscr, FpOp1);
1511 VfpSavedState state = prepVfpFpscr(Fpscr);
1512 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
1513 FpDest.uh = vfpFpSToFixed(FpOp1, false, true, imm);
1514 __asm__ __volatile__("" :: "m" (FpDest.uh));
1515 Fpscr = setVfpFpscr(Fpscr, state);
1516 '''
1517 vcvtFpUHFixedSIop = InstObjParams("vcvt", "VcvtFpUHFixedS",

1278 exec_output += PredOpExecute.subst(vcvtFpSHFixedDIop);
1279
1280 vcvtFpUHFixedSCode = '''
1281 vfpFlushToZero(Fpscr, FpOp1);
1282 VfpSavedState state = prepVfpFpscr(Fpscr);
1283 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
1284 FpDest.uh = vfpFpSToFixed(FpOp1, false, true, imm);
1285 __asm__ __volatile__("" :: "m" (FpDest.uh));
1286 Fpscr = setVfpFpscr(Fpscr, state);
1287 '''
1288 vcvtFpUHFixedSIop = InstObjParams("vcvt", "VcvtFpUHFixedS",

1518 "VfpRegRegImmOp",

1289 "FpRegRegImmOp",

1519 { "code": vcvtFpUHFixedSCode,
1520 "predicate_test": predicateTest }, [])

1290 { "code": vcvtFpUHFixedSCode,
1291 "predicate_test": predicateTest }, [])

1521 header_output += VfpRegRegImmOpDeclare.subst(vcvtFpUHFixedSIop);
1522 decoder_output += VfpRegRegImmOpConstructor.subst(vcvtFpUHFixedSIop);

1292 header_output += FpRegRegImmOpDeclare.subst(vcvtFpUHFixedSIop);
1293 decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpUHFixedSIop);

1523 exec_output += PredOpExecute.subst(vcvtFpUHFixedSIop);
1524
1525 vcvtFpUHFixedDCode = '''
1526 IntDoubleUnion cOp1;
1527 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
1528 vfpFlushToZero(Fpscr, cOp1.fp);
1529 VfpSavedState state = prepVfpFpscr(Fpscr);
1530 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp));
1531 uint64_t mid = vfpFpDToFixed(cOp1.fp, false, true, imm);
1532 __asm__ __volatile__("" :: "m" (mid));
1533 Fpscr = setVfpFpscr(Fpscr, state);
1534 FpDestP0.uw = mid;
1535 FpDestP1.uw = mid >> 32;
1536 '''
1537 vcvtFpUHFixedDIop = InstObjParams("vcvt", "VcvtFpUHFixedD",

1294 exec_output += PredOpExecute.subst(vcvtFpUHFixedSIop);
1295
1296 vcvtFpUHFixedDCode = '''
1297 IntDoubleUnion cOp1;
1298 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
1299 vfpFlushToZero(Fpscr, cOp1.fp);
1300 VfpSavedState state = prepVfpFpscr(Fpscr);
1301 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp));
1302 uint64_t mid = vfpFpDToFixed(cOp1.fp, false, true, imm);
1303 __asm__ __volatile__("" :: "m" (mid));
1304 Fpscr = setVfpFpscr(Fpscr, state);
1305 FpDestP0.uw = mid;
1306 FpDestP1.uw = mid >> 32;
1307 '''
1308 vcvtFpUHFixedDIop = InstObjParams("vcvt", "VcvtFpUHFixedD",

1538 "VfpRegRegImmOp",

1309 "FpRegRegImmOp",

1539 { "code": vcvtFpUHFixedDCode,
1540 "predicate_test": predicateTest }, [])

1310 { "code": vcvtFpUHFixedDCode,
1311 "predicate_test": predicateTest }, [])

1541 header_output += VfpRegRegImmOpDeclare.subst(vcvtFpUHFixedDIop);
1542 decoder_output += VfpRegRegImmOpConstructor.subst(vcvtFpUHFixedDIop);

1312 header_output += FpRegRegImmOpDeclare.subst(vcvtFpUHFixedDIop);
1313 decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpUHFixedDIop);

1543 exec_output += PredOpExecute.subst(vcvtFpUHFixedDIop);
1544
1545 vcvtSHFixedFpSCode = '''
1546 VfpSavedState state = prepVfpFpscr(Fpscr);
1547 __asm__ __volatile__("" : "=m" (FpOp1.sh) : "m" (FpOp1.sh));
1548 FpDest = vfpSFixedToFpS(Fpscr, FpOp1.sh, true, imm);
1549 __asm__ __volatile__("" :: "m" (FpDest));
1550 Fpscr = setVfpFpscr(Fpscr, state);
1551 '''
1552 vcvtSHFixedFpSIop = InstObjParams("vcvt", "VcvtSHFixedFpS",

1314 exec_output += PredOpExecute.subst(vcvtFpUHFixedDIop);
1315
1316 vcvtSHFixedFpSCode = '''
1317 VfpSavedState state = prepVfpFpscr(Fpscr);
1318 __asm__ __volatile__("" : "=m" (FpOp1.sh) : "m" (FpOp1.sh));
1319 FpDest = vfpSFixedToFpS(Fpscr, FpOp1.sh, true, imm);
1320 __asm__ __volatile__("" :: "m" (FpDest));
1321 Fpscr = setVfpFpscr(Fpscr, state);
1322 '''
1323 vcvtSHFixedFpSIop = InstObjParams("vcvt", "VcvtSHFixedFpS",

1553 "VfpRegRegImmOp",

1324 "FpRegRegImmOp",

1554 { "code": vcvtSHFixedFpSCode,
1555 "predicate_test": predicateTest }, [])

1325 { "code": vcvtSHFixedFpSCode,
1326 "predicate_test": predicateTest }, [])

1556 header_output += VfpRegRegImmOpDeclare.subst(vcvtSHFixedFpSIop);
1557 decoder_output += VfpRegRegImmOpConstructor.subst(vcvtSHFixedFpSIop);

1327 header_output += FpRegRegImmOpDeclare.subst(vcvtSHFixedFpSIop);
1328 decoder_output += FpRegRegImmOpConstructor.subst(vcvtSHFixedFpSIop);

1558 exec_output += PredOpExecute.subst(vcvtSHFixedFpSIop);
1559
1560 vcvtSHFixedFpDCode = '''
1561 IntDoubleUnion cDest;
1562 uint64_t mid = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
1563 VfpSavedState state = prepVfpFpscr(Fpscr);
1564 __asm__ __volatile__("" : "=m" (mid) : "m" (mid));
1565 cDest.fp = vfpSFixedToFpD(Fpscr, mid, true, imm);
1566 __asm__ __volatile__("" :: "m" (cDest.fp));
1567 Fpscr = setVfpFpscr(Fpscr, state);
1568 FpDestP0.uw = cDest.bits;
1569 FpDestP1.uw = cDest.bits >> 32;
1570 '''
1571 vcvtSHFixedFpDIop = InstObjParams("vcvt", "VcvtSHFixedFpD",

1329 exec_output += PredOpExecute.subst(vcvtSHFixedFpSIop);
1330
1331 vcvtSHFixedFpDCode = '''
1332 IntDoubleUnion cDest;
1333 uint64_t mid = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
1334 VfpSavedState state = prepVfpFpscr(Fpscr);
1335 __asm__ __volatile__("" : "=m" (mid) : "m" (mid));
1336 cDest.fp = vfpSFixedToFpD(Fpscr, mid, true, imm);
1337 __asm__ __volatile__("" :: "m" (cDest.fp));
1338 Fpscr = setVfpFpscr(Fpscr, state);
1339 FpDestP0.uw = cDest.bits;
1340 FpDestP1.uw = cDest.bits >> 32;
1341 '''
1342 vcvtSHFixedFpDIop = InstObjParams("vcvt", "VcvtSHFixedFpD",

1572 "VfpRegRegImmOp",

1343 "FpRegRegImmOp",

1573 { "code": vcvtSHFixedFpDCode,
1574 "predicate_test": predicateTest }, [])

1344 { "code": vcvtSHFixedFpDCode,
1345 "predicate_test": predicateTest }, [])

1575 header_output += VfpRegRegImmOpDeclare.subst(vcvtSHFixedFpDIop);
1576 decoder_output += VfpRegRegImmOpConstructor.subst(vcvtSHFixedFpDIop);

1346 header_output += FpRegRegImmOpDeclare.subst(vcvtSHFixedFpDIop);
1347 decoder_output += FpRegRegImmOpConstructor.subst(vcvtSHFixedFpDIop);

1577 exec_output += PredOpExecute.subst(vcvtSHFixedFpDIop);
1578
1579 vcvtUHFixedFpSCode = '''
1580 VfpSavedState state = prepVfpFpscr(Fpscr);
1581 __asm__ __volatile__("" : "=m" (FpOp1.uh) : "m" (FpOp1.uh));
1582 FpDest = vfpUFixedToFpS(Fpscr, FpOp1.uh, true, imm);
1583 __asm__ __volatile__("" :: "m" (FpDest));
1584 Fpscr = setVfpFpscr(Fpscr, state);
1585 '''
1586 vcvtUHFixedFpSIop = InstObjParams("vcvt", "VcvtUHFixedFpS",

1348 exec_output += PredOpExecute.subst(vcvtSHFixedFpDIop);
1349
1350 vcvtUHFixedFpSCode = '''
1351 VfpSavedState state = prepVfpFpscr(Fpscr);
1352 __asm__ __volatile__("" : "=m" (FpOp1.uh) : "m" (FpOp1.uh));
1353 FpDest = vfpUFixedToFpS(Fpscr, FpOp1.uh, true, imm);
1354 __asm__ __volatile__("" :: "m" (FpDest));
1355 Fpscr = setVfpFpscr(Fpscr, state);
1356 '''
1357 vcvtUHFixedFpSIop = InstObjParams("vcvt", "VcvtUHFixedFpS",

1587 "VfpRegRegImmOp",

1358 "FpRegRegImmOp",

1588 { "code": vcvtUHFixedFpSCode,
1589 "predicate_test": predicateTest }, [])

1359 { "code": vcvtUHFixedFpSCode,
1360 "predicate_test": predicateTest }, [])

1590 header_output += VfpRegRegImmOpDeclare.subst(vcvtUHFixedFpSIop);
1591 decoder_output += VfpRegRegImmOpConstructor.subst(vcvtUHFixedFpSIop);

1361 header_output += FpRegRegImmOpDeclare.subst(vcvtUHFixedFpSIop);
1362 decoder_output += FpRegRegImmOpConstructor.subst(vcvtUHFixedFpSIop);

1592 exec_output += PredOpExecute.subst(vcvtUHFixedFpSIop);
1593
1594 vcvtUHFixedFpDCode = '''
1595 IntDoubleUnion cDest;
1596 uint64_t mid = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
1597 VfpSavedState state = prepVfpFpscr(Fpscr);
1598 __asm__ __volatile__("" : "=m" (mid) : "m" (mid));
1599 cDest.fp = vfpUFixedToFpD(Fpscr, mid, true, imm);
1600 __asm__ __volatile__("" :: "m" (cDest.fp));
1601 Fpscr = setVfpFpscr(Fpscr, state);
1602 FpDestP0.uw = cDest.bits;
1603 FpDestP1.uw = cDest.bits >> 32;
1604 '''
1605 vcvtUHFixedFpDIop = InstObjParams("vcvt", "VcvtUHFixedFpD",

1363 exec_output += PredOpExecute.subst(vcvtUHFixedFpSIop);
1364
1365 vcvtUHFixedFpDCode = '''
1366 IntDoubleUnion cDest;
1367 uint64_t mid = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
1368 VfpSavedState state = prepVfpFpscr(Fpscr);
1369 __asm__ __volatile__("" : "=m" (mid) : "m" (mid));
1370 cDest.fp = vfpUFixedToFpD(Fpscr, mid, true, imm);
1371 __asm__ __volatile__("" :: "m" (cDest.fp));
1372 Fpscr = setVfpFpscr(Fpscr, state);
1373 FpDestP0.uw = cDest.bits;
1374 FpDestP1.uw = cDest.bits >> 32;
1375 '''
1376 vcvtUHFixedFpDIop = InstObjParams("vcvt", "VcvtUHFixedFpD",

1606 "VfpRegRegImmOp",

1377 "FpRegRegImmOp",

1607 { "code": vcvtUHFixedFpDCode,
1608 "predicate_test": predicateTest }, [])

1378 { "code": vcvtUHFixedFpDCode,
1379 "predicate_test": predicateTest }, [])

1609 header_output += VfpRegRegImmOpDeclare.subst(vcvtUHFixedFpDIop);
1610 decoder_output += VfpRegRegImmOpConstructor.subst(vcvtUHFixedFpDIop);

1380 header_output += FpRegRegImmOpDeclare.subst(vcvtUHFixedFpDIop);
1381 decoder_output += FpRegRegImmOpConstructor.subst(vcvtUHFixedFpDIop);