fp.isa (7386:23065556d48e) fp.isa (7387:079af601946a)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 919 unchanged lines hidden (view full) ---

928 header_output += VfpRegRegOpDeclare.subst(vcvtSIntFpDIop);
929 decoder_output += VfpRegRegOpConstructor.subst(vcvtSIntFpDIop);
930 exec_output += PredOpExecute.subst(vcvtSIntFpDIop);
931
932 vcvtFpUIntSRCode = '''
933 vfpFlushToZero(Fpscr, FpOp1);
934 VfpSavedState state = prepVfpFpscr(Fpscr);
935 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 919 unchanged lines hidden (view full) ---

928 header_output += VfpRegRegOpDeclare.subst(vcvtSIntFpDIop);
929 decoder_output += VfpRegRegOpConstructor.subst(vcvtSIntFpDIop);
930 exec_output += PredOpExecute.subst(vcvtSIntFpDIop);
931
932 vcvtFpUIntSRCode = '''
933 vfpFlushToZero(Fpscr, FpOp1);
934 VfpSavedState state = prepVfpFpscr(Fpscr);
935 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
936 FpDest.uw = FpOp1;
936 FpDest.uw = vfpFpSToFixed(FpOp1, false, false, 0);
937 __asm__ __volatile__("" :: "m" (FpDest.uw));
938 Fpscr = setVfpFpscr(Fpscr, state);
939 '''
940 vcvtFpUIntSRIop = InstObjParams("vcvt", "VcvtFpUIntSR", "VfpRegRegOp",
941 { "code": vcvtFpUIntSRCode,
942 "predicate_test": predicateTest }, [])
943 header_output += VfpRegRegOpDeclare.subst(vcvtFpUIntSRIop);
944 decoder_output += VfpRegRegOpConstructor.subst(vcvtFpUIntSRIop);
945 exec_output += PredOpExecute.subst(vcvtFpUIntSRIop);
946
947 vcvtFpUIntDRCode = '''
948 IntDoubleUnion cOp1;
949 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
950 vfpFlushToZero(Fpscr, cOp1.fp);
951 VfpSavedState state = prepVfpFpscr(Fpscr);
952 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp));
937 __asm__ __volatile__("" :: "m" (FpDest.uw));
938 Fpscr = setVfpFpscr(Fpscr, state);
939 '''
940 vcvtFpUIntSRIop = InstObjParams("vcvt", "VcvtFpUIntSR", "VfpRegRegOp",
941 { "code": vcvtFpUIntSRCode,
942 "predicate_test": predicateTest }, [])
943 header_output += VfpRegRegOpDeclare.subst(vcvtFpUIntSRIop);
944 decoder_output += VfpRegRegOpConstructor.subst(vcvtFpUIntSRIop);
945 exec_output += PredOpExecute.subst(vcvtFpUIntSRIop);
946
947 vcvtFpUIntDRCode = '''
948 IntDoubleUnion cOp1;
949 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
950 vfpFlushToZero(Fpscr, cOp1.fp);
951 VfpSavedState state = prepVfpFpscr(Fpscr);
952 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp));
953 uint64_t result = cOp1.fp;
953 uint64_t result = vfpFpDToFixed(cOp1.fp, false, false, 0);
954 __asm__ __volatile__("" :: "m" (result));
955 Fpscr = setVfpFpscr(Fpscr, state);
956 FpDestP0.uw = result;
957 '''
958 vcvtFpUIntDRIop = InstObjParams("vcvtr", "VcvtFpUIntDR", "VfpRegRegOp",
959 { "code": vcvtFpUIntDRCode,
960 "predicate_test": predicateTest }, [])
961 header_output += VfpRegRegOpDeclare.subst(vcvtFpUIntDRIop);
962 decoder_output += VfpRegRegOpConstructor.subst(vcvtFpUIntDRIop);
963 exec_output += PredOpExecute.subst(vcvtFpUIntDRIop);
964
965 vcvtFpSIntSRCode = '''
966 vfpFlushToZero(Fpscr, FpOp1);
967 VfpSavedState state = prepVfpFpscr(Fpscr);
968 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
954 __asm__ __volatile__("" :: "m" (result));
955 Fpscr = setVfpFpscr(Fpscr, state);
956 FpDestP0.uw = result;
957 '''
958 vcvtFpUIntDRIop = InstObjParams("vcvtr", "VcvtFpUIntDR", "VfpRegRegOp",
959 { "code": vcvtFpUIntDRCode,
960 "predicate_test": predicateTest }, [])
961 header_output += VfpRegRegOpDeclare.subst(vcvtFpUIntDRIop);
962 decoder_output += VfpRegRegOpConstructor.subst(vcvtFpUIntDRIop);
963 exec_output += PredOpExecute.subst(vcvtFpUIntDRIop);
964
965 vcvtFpSIntSRCode = '''
966 vfpFlushToZero(Fpscr, FpOp1);
967 VfpSavedState state = prepVfpFpscr(Fpscr);
968 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
969 FpDest.sw = FpOp1;
969 FpDest.sw = vfpFpSToFixed(FpOp1, true, false, 0);
970 __asm__ __volatile__("" :: "m" (FpDest.sw));
971 Fpscr = setVfpFpscr(Fpscr, state);
972 '''
973 vcvtFpSIntSRIop = InstObjParams("vcvtr", "VcvtFpSIntSR", "VfpRegRegOp",
974 { "code": vcvtFpSIntSRCode,
975 "predicate_test": predicateTest }, [])
976 header_output += VfpRegRegOpDeclare.subst(vcvtFpSIntSRIop);
977 decoder_output += VfpRegRegOpConstructor.subst(vcvtFpSIntSRIop);
978 exec_output += PredOpExecute.subst(vcvtFpSIntSRIop);
979
980 vcvtFpSIntDRCode = '''
981 IntDoubleUnion cOp1;
982 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
983 vfpFlushToZero(Fpscr, cOp1.fp);
984 VfpSavedState state = prepVfpFpscr(Fpscr);
985 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp));
970 __asm__ __volatile__("" :: "m" (FpDest.sw));
971 Fpscr = setVfpFpscr(Fpscr, state);
972 '''
973 vcvtFpSIntSRIop = InstObjParams("vcvtr", "VcvtFpSIntSR", "VfpRegRegOp",
974 { "code": vcvtFpSIntSRCode,
975 "predicate_test": predicateTest }, [])
976 header_output += VfpRegRegOpDeclare.subst(vcvtFpSIntSRIop);
977 decoder_output += VfpRegRegOpConstructor.subst(vcvtFpSIntSRIop);
978 exec_output += PredOpExecute.subst(vcvtFpSIntSRIop);
979
980 vcvtFpSIntDRCode = '''
981 IntDoubleUnion cOp1;
982 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
983 vfpFlushToZero(Fpscr, cOp1.fp);
984 VfpSavedState state = prepVfpFpscr(Fpscr);
985 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp));
986 int64_t result = cOp1.fp;
986 int64_t result = vfpFpDToFixed(cOp1.fp, true, false, 0);
987 __asm__ __volatile__("" :: "m" (result));
988 Fpscr = setVfpFpscr(Fpscr, state);
989 FpDestP0.uw = result;
990 '''
991 vcvtFpSIntDRIop = InstObjParams("vcvtr", "VcvtFpSIntDR", "VfpRegRegOp",
992 { "code": vcvtFpSIntDRCode,
993 "predicate_test": predicateTest }, [])
994 header_output += VfpRegRegOpDeclare.subst(vcvtFpSIntDRIop);
995 decoder_output += VfpRegRegOpConstructor.subst(vcvtFpSIntDRIop);
996 exec_output += PredOpExecute.subst(vcvtFpSIntDRIop);
997
998 vcvtFpUIntSCode = '''
999 vfpFlushToZero(Fpscr, FpOp1);
1000 VfpSavedState state = prepVfpFpscr(Fpscr);
1001 fesetround(FeRoundZero);
1002 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
987 __asm__ __volatile__("" :: "m" (result));
988 Fpscr = setVfpFpscr(Fpscr, state);
989 FpDestP0.uw = result;
990 '''
991 vcvtFpSIntDRIop = InstObjParams("vcvtr", "VcvtFpSIntDR", "VfpRegRegOp",
992 { "code": vcvtFpSIntDRCode,
993 "predicate_test": predicateTest }, [])
994 header_output += VfpRegRegOpDeclare.subst(vcvtFpSIntDRIop);
995 decoder_output += VfpRegRegOpConstructor.subst(vcvtFpSIntDRIop);
996 exec_output += PredOpExecute.subst(vcvtFpSIntDRIop);
997
998 vcvtFpUIntSCode = '''
999 vfpFlushToZero(Fpscr, FpOp1);
1000 VfpSavedState state = prepVfpFpscr(Fpscr);
1001 fesetround(FeRoundZero);
1002 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
1003 FpDest.uw = FpOp1;
1003 FpDest.uw = vfpFpSToFixed(FpOp1, false, false, 0);
1004 __asm__ __volatile__("" :: "m" (FpDest.uw));
1005 Fpscr = setVfpFpscr(Fpscr, state);
1006 '''
1007 vcvtFpUIntSIop = InstObjParams("vcvt", "VcvtFpUIntS", "VfpRegRegOp",
1008 { "code": vcvtFpUIntSCode,
1009 "predicate_test": predicateTest }, [])
1010 header_output += VfpRegRegOpDeclare.subst(vcvtFpUIntSIop);
1011 decoder_output += VfpRegRegOpConstructor.subst(vcvtFpUIntSIop);
1012 exec_output += PredOpExecute.subst(vcvtFpUIntSIop);
1013
1014 vcvtFpUIntDCode = '''
1015 IntDoubleUnion cOp1;
1016 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
1017 vfpFlushToZero(Fpscr, cOp1.fp);
1018 VfpSavedState state = prepVfpFpscr(Fpscr);
1019 fesetround(FeRoundZero);
1020 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp));
1004 __asm__ __volatile__("" :: "m" (FpDest.uw));
1005 Fpscr = setVfpFpscr(Fpscr, state);
1006 '''
1007 vcvtFpUIntSIop = InstObjParams("vcvt", "VcvtFpUIntS", "VfpRegRegOp",
1008 { "code": vcvtFpUIntSCode,
1009 "predicate_test": predicateTest }, [])
1010 header_output += VfpRegRegOpDeclare.subst(vcvtFpUIntSIop);
1011 decoder_output += VfpRegRegOpConstructor.subst(vcvtFpUIntSIop);
1012 exec_output += PredOpExecute.subst(vcvtFpUIntSIop);
1013
1014 vcvtFpUIntDCode = '''
1015 IntDoubleUnion cOp1;
1016 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
1017 vfpFlushToZero(Fpscr, cOp1.fp);
1018 VfpSavedState state = prepVfpFpscr(Fpscr);
1019 fesetround(FeRoundZero);
1020 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp));
1021 uint64_t result = cOp1.fp;
1021 uint64_t result = vfpFpDToFixed(cOp1.fp, false, false, 0);
1022 __asm__ __volatile__("" :: "m" (result));
1023 Fpscr = setVfpFpscr(Fpscr, state);
1024 FpDestP0.uw = result;
1025 '''
1026 vcvtFpUIntDIop = InstObjParams("vcvt", "VcvtFpUIntD", "VfpRegRegOp",
1027 { "code": vcvtFpUIntDCode,
1028 "predicate_test": predicateTest }, [])
1029 header_output += VfpRegRegOpDeclare.subst(vcvtFpUIntDIop);
1030 decoder_output += VfpRegRegOpConstructor.subst(vcvtFpUIntDIop);
1031 exec_output += PredOpExecute.subst(vcvtFpUIntDIop);
1032
1033 vcvtFpSIntSCode = '''
1034 vfpFlushToZero(Fpscr, FpOp1);
1035 VfpSavedState state = prepVfpFpscr(Fpscr);
1036 fesetround(FeRoundZero);
1037 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
1022 __asm__ __volatile__("" :: "m" (result));
1023 Fpscr = setVfpFpscr(Fpscr, state);
1024 FpDestP0.uw = result;
1025 '''
1026 vcvtFpUIntDIop = InstObjParams("vcvt", "VcvtFpUIntD", "VfpRegRegOp",
1027 { "code": vcvtFpUIntDCode,
1028 "predicate_test": predicateTest }, [])
1029 header_output += VfpRegRegOpDeclare.subst(vcvtFpUIntDIop);
1030 decoder_output += VfpRegRegOpConstructor.subst(vcvtFpUIntDIop);
1031 exec_output += PredOpExecute.subst(vcvtFpUIntDIop);
1032
1033 vcvtFpSIntSCode = '''
1034 vfpFlushToZero(Fpscr, FpOp1);
1035 VfpSavedState state = prepVfpFpscr(Fpscr);
1036 fesetround(FeRoundZero);
1037 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
1038 FpDest.sw = FpOp1;
1038 FpDest.sw = vfpFpSToFixed(FpOp1, true, false, 0);
1039 __asm__ __volatile__("" :: "m" (FpDest.sw));
1040 Fpscr = setVfpFpscr(Fpscr, state);
1041 '''
1042 vcvtFpSIntSIop = InstObjParams("vcvt", "VcvtFpSIntS", "VfpRegRegOp",
1043 { "code": vcvtFpSIntSCode,
1044 "predicate_test": predicateTest }, [])
1045 header_output += VfpRegRegOpDeclare.subst(vcvtFpSIntSIop);
1046 decoder_output += VfpRegRegOpConstructor.subst(vcvtFpSIntSIop);
1047 exec_output += PredOpExecute.subst(vcvtFpSIntSIop);
1048
1049 vcvtFpSIntDCode = '''
1050 IntDoubleUnion cOp1;
1051 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
1052 vfpFlushToZero(Fpscr, cOp1.fp);
1053 VfpSavedState state = prepVfpFpscr(Fpscr);
1054 fesetround(FeRoundZero);
1055 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp));
1039 __asm__ __volatile__("" :: "m" (FpDest.sw));
1040 Fpscr = setVfpFpscr(Fpscr, state);
1041 '''
1042 vcvtFpSIntSIop = InstObjParams("vcvt", "VcvtFpSIntS", "VfpRegRegOp",
1043 { "code": vcvtFpSIntSCode,
1044 "predicate_test": predicateTest }, [])
1045 header_output += VfpRegRegOpDeclare.subst(vcvtFpSIntSIop);
1046 decoder_output += VfpRegRegOpConstructor.subst(vcvtFpSIntSIop);
1047 exec_output += PredOpExecute.subst(vcvtFpSIntSIop);
1048
1049 vcvtFpSIntDCode = '''
1050 IntDoubleUnion cOp1;
1051 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
1052 vfpFlushToZero(Fpscr, cOp1.fp);
1053 VfpSavedState state = prepVfpFpscr(Fpscr);
1054 fesetround(FeRoundZero);
1055 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp));
1056 int64_t result = cOp1.fp;
1056 int64_t result = vfpFpDToFixed(cOp1.fp, true, false, 0);
1057 __asm__ __volatile__("" :: "m" (result));
1058 Fpscr = setVfpFpscr(Fpscr, state);
1059 FpDestP0.uw = result;
1060 '''
1061 vcvtFpSIntDIop = InstObjParams("vcvt", "VcvtFpSIntD", "VfpRegRegOp",
1062 { "code": vcvtFpSIntDCode,
1063 "predicate_test": predicateTest }, [])
1064 header_output += VfpRegRegOpDeclare.subst(vcvtFpSIntDIop);

--- 406 unchanged lines hidden --- 		1057 __asm__ __volatile__("" :: "m" (result));
1058 Fpscr = setVfpFpscr(Fpscr, state);
1059 FpDestP0.uw = result;
1060 '''
1061 vcvtFpSIntDIop = InstObjParams("vcvt", "VcvtFpSIntD", "VfpRegRegOp",
1062 { "code": vcvtFpSIntDCode,
1063 "predicate_test": predicateTest }, [])
1064 header_output += VfpRegRegOpDeclare.subst(vcvtFpSIntDIop);

--- 406 unchanged lines hidden ---