fp.isa (7385:493aea5e1006) | fp.isa (7386:23065556d48e) |
---|---|
1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating --- 372 unchanged lines hidden (view full) --- 381 header_output = "" 382 decoder_output = "" 383 exec_output = "" 384 385 vmulSCode = ''' 386 vfpFlushToZero(Fpscr, FpOp1, FpOp2); 387 VfpSavedState state = prepVfpFpscr(Fpscr); 388 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); | 1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating --- 372 unchanged lines hidden (view full) --- 381 header_output = "" 382 decoder_output = "" 383 exec_output = "" 384 385 vmulSCode = ''' 386 vfpFlushToZero(Fpscr, FpOp1, FpOp2); 387 VfpSavedState state = prepVfpFpscr(Fpscr); 388 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); |
389 FpDest = fixDest(Fpscr, FpOp1 * FpOp2, FpOp1, FpOp2); | 389 FpDest = fixMultDest(Fpscr, FpOp1 * FpOp2, FpOp1, FpOp2); |
390 __asm__ __volatile__("" :: "m" (FpDest)); 391 Fpscr = setVfpFpscr(Fpscr, state); 392 if ((isinf(FpOp1) && FpOp2 == 0) || (isinf(FpOp2) && FpOp1 == 0)) { 393 FpDest = NAN; 394 } 395 ''' 396 vmulSIop = InstObjParams("vmuls", "VmulS", "VfpRegRegRegOp", 397 { "code": vmulSCode, --- 4 unchanged lines hidden (view full) --- 402 403 vmulDCode = ''' 404 IntDoubleUnion cOp1, cOp2, cDest; 405 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 406 cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32)); 407 vfpFlushToZero(Fpscr, cOp1.fp, cOp2.fp); 408 VfpSavedState state = prepVfpFpscr(Fpscr); 409 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp)); | 390 __asm__ __volatile__("" :: "m" (FpDest)); 391 Fpscr = setVfpFpscr(Fpscr, state); 392 if ((isinf(FpOp1) && FpOp2 == 0) || (isinf(FpOp2) && FpOp1 == 0)) { 393 FpDest = NAN; 394 } 395 ''' 396 vmulSIop = InstObjParams("vmuls", "VmulS", "VfpRegRegRegOp", 397 { "code": vmulSCode, --- 4 unchanged lines hidden (view full) --- 402 403 vmulDCode = ''' 404 IntDoubleUnion cOp1, cOp2, cDest; 405 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 406 cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32)); 407 vfpFlushToZero(Fpscr, cOp1.fp, cOp2.fp); 408 VfpSavedState state = prepVfpFpscr(Fpscr); 409 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp)); |
410 cDest.fp = fixDest(Fpscr, cOp1.fp * cOp2.fp, cOp1.fp, cOp2.fp); | 410 cDest.fp = fixMultDest(Fpscr, cOp1.fp * cOp2.fp, cOp1.fp, cOp2.fp); |
411 __asm__ __volatile__("" :: "m" (cDest.fp)); 412 Fpscr = setVfpFpscr(Fpscr, state); 413 if ((isinf(cOp1.fp) && cOp2.fp == 0) || 414 (isinf(cOp2.fp) && cOp1.fp == 0)) { 415 cDest.fp = NAN; 416 } 417 FpDestP0.uw = cDest.bits; 418 FpDestP1.uw = cDest.bits >> 32; --- 259 unchanged lines hidden (view full) --- 678 vfpFlushToZero(Fpscr, FpOp1, FpOp2); 679 VfpSavedState state = prepVfpFpscr(Fpscr); 680 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 681 float mid = fixDest(Fpscr, FpOp1 * FpOp2, FpOp1, FpOp2); 682 if ((isinf(FpOp1) && FpOp2 == 0) || (isinf(FpOp2) && FpOp1 == 0)) { 683 mid = NAN; 684 } 685 vfpFlushToZero(Fpscr, FpDest, mid); | 411 __asm__ __volatile__("" :: "m" (cDest.fp)); 412 Fpscr = setVfpFpscr(Fpscr, state); 413 if ((isinf(cOp1.fp) && cOp2.fp == 0) || 414 (isinf(cOp2.fp) && cOp1.fp == 0)) { 415 cDest.fp = NAN; 416 } 417 FpDestP0.uw = cDest.bits; 418 FpDestP1.uw = cDest.bits >> 32; --- 259 unchanged lines hidden (view full) --- 678 vfpFlushToZero(Fpscr, FpOp1, FpOp2); 679 VfpSavedState state = prepVfpFpscr(Fpscr); 680 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 681 float mid = fixDest(Fpscr, FpOp1 * FpOp2, FpOp1, FpOp2); 682 if ((isinf(FpOp1) && FpOp2 == 0) || (isinf(FpOp2) && FpOp1 == 0)) { 683 mid = NAN; 684 } 685 vfpFlushToZero(Fpscr, FpDest, mid); |
686 FpDest = fixDest(Fpscr, FpDest - mid, FpDest, mid); | 686 FpDest = fixDest(Fpscr, FpDest - mid, FpDest, -mid); |
687 __asm__ __volatile__("" :: "m" (FpDest)); 688 Fpscr = setVfpFpscr(Fpscr, state); 689 ''' 690 vmlsSIop = InstObjParams("vmlss", "VmlsS", "VfpRegRegRegOp", 691 { "code": vmlsSCode, 692 "predicate_test": predicateTest }, []) 693 header_output += VfpRegRegRegOpDeclare.subst(vmlsSIop); 694 decoder_output += VfpRegRegRegOpConstructor.subst(vmlsSIop); --- 7 unchanged lines hidden (view full) --- 702 vfpFlushToZero(Fpscr, cOp1.fp, cOp2.fp); 703 VfpSavedState state = prepVfpFpscr(Fpscr); 704 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp)); 705 double mid = fixDest(Fpscr, cOp1.fp * cOp2.fp, cOp1.fp, cOp2.fp); 706 if ((isinf(cOp1.fp) && cOp2.fp == 0) || 707 (isinf(cOp2.fp) && cOp1.fp == 0)) { 708 mid = NAN; 709 } | 687 __asm__ __volatile__("" :: "m" (FpDest)); 688 Fpscr = setVfpFpscr(Fpscr, state); 689 ''' 690 vmlsSIop = InstObjParams("vmlss", "VmlsS", "VfpRegRegRegOp", 691 { "code": vmlsSCode, 692 "predicate_test": predicateTest }, []) 693 header_output += VfpRegRegRegOpDeclare.subst(vmlsSIop); 694 decoder_output += VfpRegRegRegOpConstructor.subst(vmlsSIop); --- 7 unchanged lines hidden (view full) --- 702 vfpFlushToZero(Fpscr, cOp1.fp, cOp2.fp); 703 VfpSavedState state = prepVfpFpscr(Fpscr); 704 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp)); 705 double mid = fixDest(Fpscr, cOp1.fp * cOp2.fp, cOp1.fp, cOp2.fp); 706 if ((isinf(cOp1.fp) && cOp2.fp == 0) || 707 (isinf(cOp2.fp) && cOp1.fp == 0)) { 708 mid = NAN; 709 } |
710 cDest.fp = fixDest(Fpscr, cDest.fp - mid, cDest.fp, mid); | 710 cDest.fp = fixDest(Fpscr, cDest.fp - mid, cDest.fp, -mid); |
711 vfpFlushToZero(Fpscr, cDest.fp, mid); 712 __asm__ __volatile__("" :: "m" (cDest.fp)); 713 Fpscr = setVfpFpscr(Fpscr, state); 714 FpDestP0.uw = cDest.bits; 715 FpDestP1.uw = cDest.bits >> 32; 716 ''' 717 vmlsDIop = InstObjParams("vmlsd", "VmlsD", "VfpRegRegRegOp", 718 { "code": vmlsDCode, --- 6 unchanged lines hidden (view full) --- 725 vfpFlushToZero(Fpscr, FpOp1, FpOp2); 726 VfpSavedState state = prepVfpFpscr(Fpscr); 727 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 728 float mid = fixDest(Fpscr, FpOp1 * FpOp2, FpOp1, FpOp2); 729 if ((isinf(FpOp1) && FpOp2 == 0) || (isinf(FpOp2) && FpOp1 == 0)) { 730 mid = NAN; 731 } 732 vfpFlushToZero(Fpscr, FpDest, mid); | 711 vfpFlushToZero(Fpscr, cDest.fp, mid); 712 __asm__ __volatile__("" :: "m" (cDest.fp)); 713 Fpscr = setVfpFpscr(Fpscr, state); 714 FpDestP0.uw = cDest.bits; 715 FpDestP1.uw = cDest.bits >> 32; 716 ''' 717 vmlsDIop = InstObjParams("vmlsd", "VmlsD", "VfpRegRegRegOp", 718 { "code": vmlsDCode, --- 6 unchanged lines hidden (view full) --- 725 vfpFlushToZero(Fpscr, FpOp1, FpOp2); 726 VfpSavedState state = prepVfpFpscr(Fpscr); 727 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 728 float mid = fixDest(Fpscr, FpOp1 * FpOp2, FpOp1, FpOp2); 729 if ((isinf(FpOp1) && FpOp2 == 0) || (isinf(FpOp2) && FpOp1 == 0)) { 730 mid = NAN; 731 } 732 vfpFlushToZero(Fpscr, FpDest, mid); |
733 FpDest = fixDest(Fpscr, -FpDest - mid, FpDest, mid); | 733 FpDest = fixDest(Fpscr, -FpDest - mid, -FpDest, -mid); |
734 __asm__ __volatile__("" :: "m" (FpDest)); 735 Fpscr = setVfpFpscr(Fpscr, state); 736 ''' 737 vnmlaSIop = InstObjParams("vnmlas", "VnmlaS", "VfpRegRegRegOp", 738 { "code": vnmlaSCode, 739 "predicate_test": predicateTest }, []) 740 header_output += VfpRegRegRegOpDeclare.subst(vnmlaSIop); 741 decoder_output += VfpRegRegRegOpConstructor.subst(vnmlaSIop); --- 8 unchanged lines hidden (view full) --- 750 VfpSavedState state = prepVfpFpscr(Fpscr); 751 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp)); 752 double mid = fixDest(Fpscr, cOp1.fp * cOp2.fp, cOp1.fp, cOp2.fp); 753 if ((isinf(cOp1.fp) && cOp2.fp == 0) || 754 (isinf(cOp2.fp) && cOp1.fp == 0)) { 755 mid = NAN; 756 } 757 vfpFlushToZero(Fpscr, cDest.fp, mid); | 734 __asm__ __volatile__("" :: "m" (FpDest)); 735 Fpscr = setVfpFpscr(Fpscr, state); 736 ''' 737 vnmlaSIop = InstObjParams("vnmlas", "VnmlaS", "VfpRegRegRegOp", 738 { "code": vnmlaSCode, 739 "predicate_test": predicateTest }, []) 740 header_output += VfpRegRegRegOpDeclare.subst(vnmlaSIop); 741 decoder_output += VfpRegRegRegOpConstructor.subst(vnmlaSIop); --- 8 unchanged lines hidden (view full) --- 750 VfpSavedState state = prepVfpFpscr(Fpscr); 751 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp)); 752 double mid = fixDest(Fpscr, cOp1.fp * cOp2.fp, cOp1.fp, cOp2.fp); 753 if ((isinf(cOp1.fp) && cOp2.fp == 0) || 754 (isinf(cOp2.fp) && cOp1.fp == 0)) { 755 mid = NAN; 756 } 757 vfpFlushToZero(Fpscr, cDest.fp, mid); |
758 cDest.fp = fixDest(Fpscr, -cDest.fp - mid, cDest.fp, mid); | 758 cDest.fp = fixDest(Fpscr, -cDest.fp - mid, -cDest.fp, -mid); |
759 __asm__ __volatile__("" :: "m" (cDest.fp)); 760 Fpscr = setVfpFpscr(Fpscr, state); 761 FpDestP0.uw = cDest.bits; 762 FpDestP1.uw = cDest.bits >> 32; 763 ''' 764 vnmlaDIop = InstObjParams("vnmlad", "VnmlaD", "VfpRegRegRegOp", 765 { "code": vnmlaDCode, 766 "predicate_test": predicateTest }, []) --- 5 unchanged lines hidden (view full) --- 772 vfpFlushToZero(Fpscr, FpOp1, FpOp2); 773 VfpSavedState state = prepVfpFpscr(Fpscr); 774 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 775 float mid = fixDest(Fpscr, FpOp1 * FpOp2, FpOp1, FpOp2); 776 if ((isinf(FpOp1) && FpOp2 == 0) || (isinf(FpOp2) && FpOp1 == 0)) { 777 mid = NAN; 778 } 779 vfpFlushToZero(Fpscr, FpDest, mid); | 759 __asm__ __volatile__("" :: "m" (cDest.fp)); 760 Fpscr = setVfpFpscr(Fpscr, state); 761 FpDestP0.uw = cDest.bits; 762 FpDestP1.uw = cDest.bits >> 32; 763 ''' 764 vnmlaDIop = InstObjParams("vnmlad", "VnmlaD", "VfpRegRegRegOp", 765 { "code": vnmlaDCode, 766 "predicate_test": predicateTest }, []) --- 5 unchanged lines hidden (view full) --- 772 vfpFlushToZero(Fpscr, FpOp1, FpOp2); 773 VfpSavedState state = prepVfpFpscr(Fpscr); 774 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 775 float mid = fixDest(Fpscr, FpOp1 * FpOp2, FpOp1, FpOp2); 776 if ((isinf(FpOp1) && FpOp2 == 0) || (isinf(FpOp2) && FpOp1 == 0)) { 777 mid = NAN; 778 } 779 vfpFlushToZero(Fpscr, FpDest, mid); |
780 FpDest = fixDest(Fpscr, -FpDest + mid, FpDest, mid); | 780 FpDest = fixDest(Fpscr, -FpDest + mid, -FpDest, mid); |
781 __asm__ __volatile__("" :: "m" (FpDest)); 782 Fpscr = setVfpFpscr(Fpscr, state); 783 ''' 784 vnmlsSIop = InstObjParams("vnmlss", "VnmlsS", "VfpRegRegRegOp", 785 { "code": vnmlsSCode, 786 "predicate_test": predicateTest }, []) 787 header_output += VfpRegRegRegOpDeclare.subst(vnmlsSIop); 788 decoder_output += VfpRegRegRegOpConstructor.subst(vnmlsSIop); --- 8 unchanged lines hidden (view full) --- 797 VfpSavedState state = prepVfpFpscr(Fpscr); 798 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp)); 799 double mid = fixDest(Fpscr, cOp1.fp * cOp2.fp, cOp1.fp, cOp2.fp); 800 if ((isinf(cOp1.fp) && cOp2.fp == 0) || 801 (isinf(cOp2.fp) && cOp1.fp == 0)) { 802 mid = NAN; 803 } 804 vfpFlushToZero(Fpscr, cDest.fp, mid); | 781 __asm__ __volatile__("" :: "m" (FpDest)); 782 Fpscr = setVfpFpscr(Fpscr, state); 783 ''' 784 vnmlsSIop = InstObjParams("vnmlss", "VnmlsS", "VfpRegRegRegOp", 785 { "code": vnmlsSCode, 786 "predicate_test": predicateTest }, []) 787 header_output += VfpRegRegRegOpDeclare.subst(vnmlsSIop); 788 decoder_output += VfpRegRegRegOpConstructor.subst(vnmlsSIop); --- 8 unchanged lines hidden (view full) --- 797 VfpSavedState state = prepVfpFpscr(Fpscr); 798 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp)); 799 double mid = fixDest(Fpscr, cOp1.fp * cOp2.fp, cOp1.fp, cOp2.fp); 800 if ((isinf(cOp1.fp) && cOp2.fp == 0) || 801 (isinf(cOp2.fp) && cOp1.fp == 0)) { 802 mid = NAN; 803 } 804 vfpFlushToZero(Fpscr, cDest.fp, mid); |
805 cDest.fp = fixDest(Fpscr, -cDest.fp + mid, cDest.fp, mid); | 805 cDest.fp = fixDest(Fpscr, -cDest.fp + mid, -cDest.fp, mid); |
806 __asm__ __volatile__("" :: "m" (cDest.fp)); 807 Fpscr = setVfpFpscr(Fpscr, state); 808 FpDestP0.uw = cDest.bits; 809 FpDestP1.uw = cDest.bits >> 32; 810 ''' 811 vnmlsDIop = InstObjParams("vnmlsd", "VnmlsD", "VfpRegRegRegOp", 812 { "code": vnmlsDCode, 813 "predicate_test": predicateTest }, []) --- 270 unchanged lines hidden (view full) --- 1084 exec_output += PredOpExecute.subst(vcvtFpSFpDIop); 1085 1086 vcvtFpDFpSCode = ''' 1087 IntDoubleUnion cOp1; 1088 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 1089 vfpFlushToZero(Fpscr, cOp1.fp); 1090 VfpSavedState state = prepVfpFpscr(Fpscr); 1091 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp)); | 806 __asm__ __volatile__("" :: "m" (cDest.fp)); 807 Fpscr = setVfpFpscr(Fpscr, state); 808 FpDestP0.uw = cDest.bits; 809 FpDestP1.uw = cDest.bits >> 32; 810 ''' 811 vnmlsDIop = InstObjParams("vnmlsd", "VnmlsD", "VfpRegRegRegOp", 812 { "code": vnmlsDCode, 813 "predicate_test": predicateTest }, []) --- 270 unchanged lines hidden (view full) --- 1084 exec_output += PredOpExecute.subst(vcvtFpSFpDIop); 1085 1086 vcvtFpDFpSCode = ''' 1087 IntDoubleUnion cOp1; 1088 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 1089 vfpFlushToZero(Fpscr, cOp1.fp); 1090 VfpSavedState state = prepVfpFpscr(Fpscr); 1091 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp)); |
1092 FpDest = cOp1.fp; | 1092 FpDest = fixFpDFpSDest(Fpscr, cOp1.fp); |
1093 __asm__ __volatile__("" :: "m" (FpDest)); 1094 Fpscr = setVfpFpscr(Fpscr, state); 1095 ''' 1096 vcvtFpDFpSIop = InstObjParams("vcvt", "VcvtFpDFpS", "VfpRegRegOp", 1097 { "code": vcvtFpDFpSCode, 1098 "predicate_test": predicateTest }, []) 1099 header_output += VfpRegRegOpDeclare.subst(vcvtFpDFpSIop); 1100 decoder_output += VfpRegRegOpConstructor.subst(vcvtFpDFpSIop); --- 161 unchanged lines hidden (view full) --- 1262 "predicate_test": predicateTest }, []) 1263 header_output += VfpRegRegImmOpDeclare.subst(vcvtFpUFixedDIop); 1264 decoder_output += VfpRegRegImmOpConstructor.subst(vcvtFpUFixedDIop); 1265 exec_output += PredOpExecute.subst(vcvtFpUFixedDIop); 1266 1267 vcvtSFixedFpSCode = ''' 1268 VfpSavedState state = prepVfpFpscr(Fpscr); 1269 __asm__ __volatile__("" : "=m" (FpOp1.sw) : "m" (FpOp1.sw)); | 1093 __asm__ __volatile__("" :: "m" (FpDest)); 1094 Fpscr = setVfpFpscr(Fpscr, state); 1095 ''' 1096 vcvtFpDFpSIop = InstObjParams("vcvt", "VcvtFpDFpS", "VfpRegRegOp", 1097 { "code": vcvtFpDFpSCode, 1098 "predicate_test": predicateTest }, []) 1099 header_output += VfpRegRegOpDeclare.subst(vcvtFpDFpSIop); 1100 decoder_output += VfpRegRegOpConstructor.subst(vcvtFpDFpSIop); --- 161 unchanged lines hidden (view full) --- 1262 "predicate_test": predicateTest }, []) 1263 header_output += VfpRegRegImmOpDeclare.subst(vcvtFpUFixedDIop); 1264 decoder_output += VfpRegRegImmOpConstructor.subst(vcvtFpUFixedDIop); 1265 exec_output += PredOpExecute.subst(vcvtFpUFixedDIop); 1266 1267 vcvtSFixedFpSCode = ''' 1268 VfpSavedState state = prepVfpFpscr(Fpscr); 1269 __asm__ __volatile__("" : "=m" (FpOp1.sw) : "m" (FpOp1.sw)); |
1270 FpDest = vfpSFixedToFpS(FpOp1.sw, false, imm); | 1270 FpDest = vfpSFixedToFpS(Fpscr, FpOp1.sw, false, imm); |
1271 __asm__ __volatile__("" :: "m" (FpDest)); 1272 Fpscr = setVfpFpscr(Fpscr, state); 1273 ''' 1274 vcvtSFixedFpSIop = InstObjParams("vcvt", "VcvtSFixedFpS", "VfpRegRegImmOp", 1275 { "code": vcvtSFixedFpSCode, 1276 "predicate_test": predicateTest }, []) 1277 header_output += VfpRegRegImmOpDeclare.subst(vcvtSFixedFpSIop); 1278 decoder_output += VfpRegRegImmOpConstructor.subst(vcvtSFixedFpSIop); 1279 exec_output += PredOpExecute.subst(vcvtSFixedFpSIop); 1280 1281 vcvtSFixedFpDCode = ''' 1282 IntDoubleUnion cDest; 1283 uint64_t mid = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 1284 VfpSavedState state = prepVfpFpscr(Fpscr); 1285 __asm__ __volatile__("" : "=m" (mid) : "m" (mid)); | 1271 __asm__ __volatile__("" :: "m" (FpDest)); 1272 Fpscr = setVfpFpscr(Fpscr, state); 1273 ''' 1274 vcvtSFixedFpSIop = InstObjParams("vcvt", "VcvtSFixedFpS", "VfpRegRegImmOp", 1275 { "code": vcvtSFixedFpSCode, 1276 "predicate_test": predicateTest }, []) 1277 header_output += VfpRegRegImmOpDeclare.subst(vcvtSFixedFpSIop); 1278 decoder_output += VfpRegRegImmOpConstructor.subst(vcvtSFixedFpSIop); 1279 exec_output += PredOpExecute.subst(vcvtSFixedFpSIop); 1280 1281 vcvtSFixedFpDCode = ''' 1282 IntDoubleUnion cDest; 1283 uint64_t mid = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 1284 VfpSavedState state = prepVfpFpscr(Fpscr); 1285 __asm__ __volatile__("" : "=m" (mid) : "m" (mid)); |
1286 cDest.fp = vfpSFixedToFpD(mid, false, imm); | 1286 cDest.fp = vfpSFixedToFpD(Fpscr, mid, false, imm); |
1287 __asm__ __volatile__("" :: "m" (cDest.fp)); 1288 Fpscr = setVfpFpscr(Fpscr, state); 1289 FpDestP0.uw = cDest.bits; 1290 FpDestP1.uw = cDest.bits >> 32; 1291 ''' 1292 vcvtSFixedFpDIop = InstObjParams("vcvt", "VcvtSFixedFpD", "VfpRegRegImmOp", 1293 { "code": vcvtSFixedFpDCode, 1294 "predicate_test": predicateTest }, []) 1295 header_output += VfpRegRegImmOpDeclare.subst(vcvtSFixedFpDIop); 1296 decoder_output += VfpRegRegImmOpConstructor.subst(vcvtSFixedFpDIop); 1297 exec_output += PredOpExecute.subst(vcvtSFixedFpDIop); 1298 1299 vcvtUFixedFpSCode = ''' 1300 VfpSavedState state = prepVfpFpscr(Fpscr); 1301 __asm__ __volatile__("" : "=m" (FpOp1.uw) : "m" (FpOp1.uw)); | 1287 __asm__ __volatile__("" :: "m" (cDest.fp)); 1288 Fpscr = setVfpFpscr(Fpscr, state); 1289 FpDestP0.uw = cDest.bits; 1290 FpDestP1.uw = cDest.bits >> 32; 1291 ''' 1292 vcvtSFixedFpDIop = InstObjParams("vcvt", "VcvtSFixedFpD", "VfpRegRegImmOp", 1293 { "code": vcvtSFixedFpDCode, 1294 "predicate_test": predicateTest }, []) 1295 header_output += VfpRegRegImmOpDeclare.subst(vcvtSFixedFpDIop); 1296 decoder_output += VfpRegRegImmOpConstructor.subst(vcvtSFixedFpDIop); 1297 exec_output += PredOpExecute.subst(vcvtSFixedFpDIop); 1298 1299 vcvtUFixedFpSCode = ''' 1300 VfpSavedState state = prepVfpFpscr(Fpscr); 1301 __asm__ __volatile__("" : "=m" (FpOp1.uw) : "m" (FpOp1.uw)); |
1302 FpDest = vfpUFixedToFpS(FpOp1.uw, false, imm); | 1302 FpDest = vfpUFixedToFpS(Fpscr, FpOp1.uw, false, imm); |
1303 __asm__ __volatile__("" :: "m" (FpDest)); 1304 Fpscr = setVfpFpscr(Fpscr, state); 1305 ''' 1306 vcvtUFixedFpSIop = InstObjParams("vcvt", "VcvtUFixedFpS", "VfpRegRegImmOp", 1307 { "code": vcvtUFixedFpSCode, 1308 "predicate_test": predicateTest }, []) 1309 header_output += VfpRegRegImmOpDeclare.subst(vcvtUFixedFpSIop); 1310 decoder_output += VfpRegRegImmOpConstructor.subst(vcvtUFixedFpSIop); 1311 exec_output += PredOpExecute.subst(vcvtUFixedFpSIop); 1312 1313 vcvtUFixedFpDCode = ''' 1314 IntDoubleUnion cDest; 1315 uint64_t mid = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 1316 VfpSavedState state = prepVfpFpscr(Fpscr); 1317 __asm__ __volatile__("" : "=m" (mid) : "m" (mid)); | 1303 __asm__ __volatile__("" :: "m" (FpDest)); 1304 Fpscr = setVfpFpscr(Fpscr, state); 1305 ''' 1306 vcvtUFixedFpSIop = InstObjParams("vcvt", "VcvtUFixedFpS", "VfpRegRegImmOp", 1307 { "code": vcvtUFixedFpSCode, 1308 "predicate_test": predicateTest }, []) 1309 header_output += VfpRegRegImmOpDeclare.subst(vcvtUFixedFpSIop); 1310 decoder_output += VfpRegRegImmOpConstructor.subst(vcvtUFixedFpSIop); 1311 exec_output += PredOpExecute.subst(vcvtUFixedFpSIop); 1312 1313 vcvtUFixedFpDCode = ''' 1314 IntDoubleUnion cDest; 1315 uint64_t mid = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 1316 VfpSavedState state = prepVfpFpscr(Fpscr); 1317 __asm__ __volatile__("" : "=m" (mid) : "m" (mid)); |
1318 cDest.fp = vfpUFixedToFpD(mid, false, imm); | 1318 cDest.fp = vfpUFixedToFpD(Fpscr, mid, false, imm); |
1319 __asm__ __volatile__("" :: "m" (cDest.fp)); 1320 Fpscr = setVfpFpscr(Fpscr, state); 1321 FpDestP0.uw = cDest.bits; 1322 FpDestP1.uw = cDest.bits >> 32; 1323 ''' 1324 vcvtUFixedFpDIop = InstObjParams("vcvt", "VcvtUFixedFpD", "VfpRegRegImmOp", 1325 { "code": vcvtUFixedFpDCode, 1326 "predicate_test": predicateTest }, []) --- 71 unchanged lines hidden (view full) --- 1398 "predicate_test": predicateTest }, []) 1399 header_output += VfpRegRegImmOpDeclare.subst(vcvtFpUHFixedDIop); 1400 decoder_output += VfpRegRegImmOpConstructor.subst(vcvtFpUHFixedDIop); 1401 exec_output += PredOpExecute.subst(vcvtFpUHFixedDIop); 1402 1403 vcvtSHFixedFpSCode = ''' 1404 VfpSavedState state = prepVfpFpscr(Fpscr); 1405 __asm__ __volatile__("" : "=m" (FpOp1.sh) : "m" (FpOp1.sh)); | 1319 __asm__ __volatile__("" :: "m" (cDest.fp)); 1320 Fpscr = setVfpFpscr(Fpscr, state); 1321 FpDestP0.uw = cDest.bits; 1322 FpDestP1.uw = cDest.bits >> 32; 1323 ''' 1324 vcvtUFixedFpDIop = InstObjParams("vcvt", "VcvtUFixedFpD", "VfpRegRegImmOp", 1325 { "code": vcvtUFixedFpDCode, 1326 "predicate_test": predicateTest }, []) --- 71 unchanged lines hidden (view full) --- 1398 "predicate_test": predicateTest }, []) 1399 header_output += VfpRegRegImmOpDeclare.subst(vcvtFpUHFixedDIop); 1400 decoder_output += VfpRegRegImmOpConstructor.subst(vcvtFpUHFixedDIop); 1401 exec_output += PredOpExecute.subst(vcvtFpUHFixedDIop); 1402 1403 vcvtSHFixedFpSCode = ''' 1404 VfpSavedState state = prepVfpFpscr(Fpscr); 1405 __asm__ __volatile__("" : "=m" (FpOp1.sh) : "m" (FpOp1.sh)); |
1406 FpDest = vfpSFixedToFpS(FpOp1.sh, true, imm); | 1406 FpDest = vfpSFixedToFpS(Fpscr, FpOp1.sh, true, imm); |
1407 __asm__ __volatile__("" :: "m" (FpDest)); 1408 Fpscr = setVfpFpscr(Fpscr, state); 1409 ''' 1410 vcvtSHFixedFpSIop = InstObjParams("vcvt", "VcvtSHFixedFpS", 1411 "VfpRegRegImmOp", 1412 { "code": vcvtSHFixedFpSCode, 1413 "predicate_test": predicateTest }, []) 1414 header_output += VfpRegRegImmOpDeclare.subst(vcvtSHFixedFpSIop); 1415 decoder_output += VfpRegRegImmOpConstructor.subst(vcvtSHFixedFpSIop); 1416 exec_output += PredOpExecute.subst(vcvtSHFixedFpSIop); 1417 1418 vcvtSHFixedFpDCode = ''' 1419 IntDoubleUnion cDest; 1420 uint64_t mid = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 1421 VfpSavedState state = prepVfpFpscr(Fpscr); 1422 __asm__ __volatile__("" : "=m" (mid) : "m" (mid)); | 1407 __asm__ __volatile__("" :: "m" (FpDest)); 1408 Fpscr = setVfpFpscr(Fpscr, state); 1409 ''' 1410 vcvtSHFixedFpSIop = InstObjParams("vcvt", "VcvtSHFixedFpS", 1411 "VfpRegRegImmOp", 1412 { "code": vcvtSHFixedFpSCode, 1413 "predicate_test": predicateTest }, []) 1414 header_output += VfpRegRegImmOpDeclare.subst(vcvtSHFixedFpSIop); 1415 decoder_output += VfpRegRegImmOpConstructor.subst(vcvtSHFixedFpSIop); 1416 exec_output += PredOpExecute.subst(vcvtSHFixedFpSIop); 1417 1418 vcvtSHFixedFpDCode = ''' 1419 IntDoubleUnion cDest; 1420 uint64_t mid = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 1421 VfpSavedState state = prepVfpFpscr(Fpscr); 1422 __asm__ __volatile__("" : "=m" (mid) : "m" (mid)); |
1423 cDest.fp = vfpSFixedToFpD(mid, true, imm); | 1423 cDest.fp = vfpSFixedToFpD(Fpscr, mid, true, imm); |
1424 __asm__ __volatile__("" :: "m" (cDest.fp)); 1425 Fpscr = setVfpFpscr(Fpscr, state); 1426 FpDestP0.uw = cDest.bits; 1427 FpDestP1.uw = cDest.bits >> 32; 1428 ''' 1429 vcvtSHFixedFpDIop = InstObjParams("vcvt", "VcvtSHFixedFpD", 1430 "VfpRegRegImmOp", 1431 { "code": vcvtSHFixedFpDCode, 1432 "predicate_test": predicateTest }, []) 1433 header_output += VfpRegRegImmOpDeclare.subst(vcvtSHFixedFpDIop); 1434 decoder_output += VfpRegRegImmOpConstructor.subst(vcvtSHFixedFpDIop); 1435 exec_output += PredOpExecute.subst(vcvtSHFixedFpDIop); 1436 1437 vcvtUHFixedFpSCode = ''' 1438 VfpSavedState state = prepVfpFpscr(Fpscr); 1439 __asm__ __volatile__("" : "=m" (FpOp1.uh) : "m" (FpOp1.uh)); | 1424 __asm__ __volatile__("" :: "m" (cDest.fp)); 1425 Fpscr = setVfpFpscr(Fpscr, state); 1426 FpDestP0.uw = cDest.bits; 1427 FpDestP1.uw = cDest.bits >> 32; 1428 ''' 1429 vcvtSHFixedFpDIop = InstObjParams("vcvt", "VcvtSHFixedFpD", 1430 "VfpRegRegImmOp", 1431 { "code": vcvtSHFixedFpDCode, 1432 "predicate_test": predicateTest }, []) 1433 header_output += VfpRegRegImmOpDeclare.subst(vcvtSHFixedFpDIop); 1434 decoder_output += VfpRegRegImmOpConstructor.subst(vcvtSHFixedFpDIop); 1435 exec_output += PredOpExecute.subst(vcvtSHFixedFpDIop); 1436 1437 vcvtUHFixedFpSCode = ''' 1438 VfpSavedState state = prepVfpFpscr(Fpscr); 1439 __asm__ __volatile__("" : "=m" (FpOp1.uh) : "m" (FpOp1.uh)); |
1440 FpDest = vfpUFixedToFpS(FpOp1.uh, true, imm); | 1440 FpDest = vfpUFixedToFpS(Fpscr, FpOp1.uh, true, imm); |
1441 __asm__ __volatile__("" :: "m" (FpDest)); 1442 Fpscr = setVfpFpscr(Fpscr, state); 1443 ''' 1444 vcvtUHFixedFpSIop = InstObjParams("vcvt", "VcvtUHFixedFpS", 1445 "VfpRegRegImmOp", 1446 { "code": vcvtUHFixedFpSCode, 1447 "predicate_test": predicateTest }, []) 1448 header_output += VfpRegRegImmOpDeclare.subst(vcvtUHFixedFpSIop); 1449 decoder_output += VfpRegRegImmOpConstructor.subst(vcvtUHFixedFpSIop); 1450 exec_output += PredOpExecute.subst(vcvtUHFixedFpSIop); 1451 1452 vcvtUHFixedFpDCode = ''' 1453 IntDoubleUnion cDest; 1454 uint64_t mid = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 1455 VfpSavedState state = prepVfpFpscr(Fpscr); 1456 __asm__ __volatile__("" : "=m" (mid) : "m" (mid)); | 1441 __asm__ __volatile__("" :: "m" (FpDest)); 1442 Fpscr = setVfpFpscr(Fpscr, state); 1443 ''' 1444 vcvtUHFixedFpSIop = InstObjParams("vcvt", "VcvtUHFixedFpS", 1445 "VfpRegRegImmOp", 1446 { "code": vcvtUHFixedFpSCode, 1447 "predicate_test": predicateTest }, []) 1448 header_output += VfpRegRegImmOpDeclare.subst(vcvtUHFixedFpSIop); 1449 decoder_output += VfpRegRegImmOpConstructor.subst(vcvtUHFixedFpSIop); 1450 exec_output += PredOpExecute.subst(vcvtUHFixedFpSIop); 1451 1452 vcvtUHFixedFpDCode = ''' 1453 IntDoubleUnion cDest; 1454 uint64_t mid = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 1455 VfpSavedState state = prepVfpFpscr(Fpscr); 1456 __asm__ __volatile__("" : "=m" (mid) : "m" (mid)); |
1457 cDest.fp = vfpUFixedToFpD(mid, true, imm); | 1457 cDest.fp = vfpUFixedToFpD(Fpscr, mid, true, imm); |
1458 __asm__ __volatile__("" :: "m" (cDest.fp)); 1459 Fpscr = setVfpFpscr(Fpscr, state); 1460 FpDestP0.uw = cDest.bits; 1461 FpDestP1.uw = cDest.bits >> 32; 1462 ''' 1463 vcvtUHFixedFpDIop = InstObjParams("vcvt", "VcvtUHFixedFpD", 1464 "VfpRegRegImmOp", 1465 { "code": vcvtUHFixedFpDCode, 1466 "predicate_test": predicateTest }, []) 1467 header_output += VfpRegRegImmOpDeclare.subst(vcvtUHFixedFpDIop); 1468 decoder_output += VfpRegRegImmOpConstructor.subst(vcvtUHFixedFpDIop); 1469 exec_output += PredOpExecute.subst(vcvtUHFixedFpDIop); 1470}}; | 1458 __asm__ __volatile__("" :: "m" (cDest.fp)); 1459 Fpscr = setVfpFpscr(Fpscr, state); 1460 FpDestP0.uw = cDest.bits; 1461 FpDestP1.uw = cDest.bits >> 32; 1462 ''' 1463 vcvtUHFixedFpDIop = InstObjParams("vcvt", "VcvtUHFixedFpD", 1464 "VfpRegRegImmOp", 1465 { "code": vcvtUHFixedFpDCode, 1466 "predicate_test": predicateTest }, []) 1467 header_output += VfpRegRegImmOpDeclare.subst(vcvtUHFixedFpDIop); 1468 decoder_output += VfpRegRegImmOpConstructor.subst(vcvtUHFixedFpDIop); 1469 exec_output += PredOpExecute.subst(vcvtUHFixedFpDIop); 1470}}; |