fp.isa (7382:b3c768629a54) fp.isa (7384:f12b4f28e5eb)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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381 header_output = ""
382 decoder_output = ""
383 exec_output = ""
384
385 vmulSCode = '''
386 vfpFlushToZero(Fpscr, FpOp1, FpOp2);
387 VfpSavedState state = prepVfpFpscr(Fpscr);
388 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 372 unchanged lines hidden (view full) ---

381 header_output = ""
382 decoder_output = ""
383 exec_output = ""
384
385 vmulSCode = '''
386 vfpFlushToZero(Fpscr, FpOp1, FpOp2);
387 VfpSavedState state = prepVfpFpscr(Fpscr);
388 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
389 FpDest = FpOp1 * FpOp2;
389 FpDest = fixNan(Fpscr, FpOp1 * FpOp2, FpOp1, FpOp2);
390 __asm__ __volatile__("" :: "m" (FpDest));
391 Fpscr = setVfpFpscr(Fpscr, state);
392 if ((isinf(FpOp1) && FpOp2 == 0) || (isinf(FpOp2) && FpOp1 == 0)) {
393 FpDest = NAN;
394 }
395 '''
396 vmulSIop = InstObjParams("vmuls", "VmulS", "VfpRegRegRegOp",
397 { "code": vmulSCode,

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402
403 vmulDCode = '''
404 IntDoubleUnion cOp1, cOp2, cDest;
405 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
406 cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32));
407 vfpFlushToZero(Fpscr, cOp1.fp, cOp2.fp);
408 VfpSavedState state = prepVfpFpscr(Fpscr);
409 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp));
390 __asm__ __volatile__("" :: "m" (FpDest));
391 Fpscr = setVfpFpscr(Fpscr, state);
392 if ((isinf(FpOp1) && FpOp2 == 0) || (isinf(FpOp2) && FpOp1 == 0)) {
393 FpDest = NAN;
394 }
395 '''
396 vmulSIop = InstObjParams("vmuls", "VmulS", "VfpRegRegRegOp",
397 { "code": vmulSCode,

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402
403 vmulDCode = '''
404 IntDoubleUnion cOp1, cOp2, cDest;
405 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
406 cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32));
407 vfpFlushToZero(Fpscr, cOp1.fp, cOp2.fp);
408 VfpSavedState state = prepVfpFpscr(Fpscr);
409 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp));
410 cDest.fp = cOp1.fp * cOp2.fp;
410 cDest.fp = fixNan(Fpscr, cOp1.fp * cOp2.fp, cOp1.fp, cOp2.fp);
411 __asm__ __volatile__("" :: "m" (cDest.fp));
412 Fpscr = setVfpFpscr(Fpscr, state);
413 if ((isinf(cOp1.fp) && cOp2.fp == 0) ||
414 (isinf(cOp2.fp) && cOp1.fp == 0)) {
415 cDest.fp = NAN;
416 }
417 FpDestP0.uw = cDest.bits;
418 FpDestP1.uw = cDest.bits >> 32;

--- 52 unchanged lines hidden (view full) ---

471 header_output += VfpRegRegOpDeclare.subst(vabsDIop);
472 decoder_output += VfpRegRegOpConstructor.subst(vabsDIop);
473 exec_output += PredOpExecute.subst(vabsDIop);
474
475 vaddSCode = '''
476 vfpFlushToZero(Fpscr, FpOp1, FpOp2);
477 VfpSavedState state = prepVfpFpscr(Fpscr);
478 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
411 __asm__ __volatile__("" :: "m" (cDest.fp));
412 Fpscr = setVfpFpscr(Fpscr, state);
413 if ((isinf(cOp1.fp) && cOp2.fp == 0) ||
414 (isinf(cOp2.fp) && cOp1.fp == 0)) {
415 cDest.fp = NAN;
416 }
417 FpDestP0.uw = cDest.bits;
418 FpDestP1.uw = cDest.bits >> 32;

--- 52 unchanged lines hidden (view full) ---

471 header_output += VfpRegRegOpDeclare.subst(vabsDIop);
472 decoder_output += VfpRegRegOpConstructor.subst(vabsDIop);
473 exec_output += PredOpExecute.subst(vabsDIop);
474
475 vaddSCode = '''
476 vfpFlushToZero(Fpscr, FpOp1, FpOp2);
477 VfpSavedState state = prepVfpFpscr(Fpscr);
478 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
479 FpDest = FpOp1 + FpOp2;
479 FpDest = fixNan(Fpscr, FpOp1 + FpOp2, FpOp1, FpOp2);
480 __asm__ __volatile__("" :: "m" (FpDest));
481 Fpscr = setVfpFpscr(Fpscr, state);
482 '''
483 vaddSIop = InstObjParams("vadds", "VaddS", "VfpRegRegRegOp",
484 { "code": vaddSCode,
485 "predicate_test": predicateTest }, [])
486 header_output += VfpRegRegRegOpDeclare.subst(vaddSIop);
487 decoder_output += VfpRegRegRegOpConstructor.subst(vaddSIop);
488 exec_output += PredOpExecute.subst(vaddSIop);
489
490 vaddDCode = '''
491 IntDoubleUnion cOp1, cOp2, cDest;
492 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
493 cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32));
494 vfpFlushToZero(Fpscr, cOp1.fp, cOp2.fp);
495 VfpSavedState state = prepVfpFpscr(Fpscr);
496 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp));
480 __asm__ __volatile__("" :: "m" (FpDest));
481 Fpscr = setVfpFpscr(Fpscr, state);
482 '''
483 vaddSIop = InstObjParams("vadds", "VaddS", "VfpRegRegRegOp",
484 { "code": vaddSCode,
485 "predicate_test": predicateTest }, [])
486 header_output += VfpRegRegRegOpDeclare.subst(vaddSIop);
487 decoder_output += VfpRegRegRegOpConstructor.subst(vaddSIop);
488 exec_output += PredOpExecute.subst(vaddSIop);
489
490 vaddDCode = '''
491 IntDoubleUnion cOp1, cOp2, cDest;
492 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
493 cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32));
494 vfpFlushToZero(Fpscr, cOp1.fp, cOp2.fp);
495 VfpSavedState state = prepVfpFpscr(Fpscr);
496 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp));
497 cDest.fp = cOp1.fp + cOp2.fp;
497 cDest.fp = fixNan(Fpscr, cOp1.fp + cOp2.fp, cOp1.fp, cOp2.fp);
498 __asm__ __volatile__("" :: "m" (cDest.fp));
499 Fpscr = setVfpFpscr(Fpscr, state);
500 FpDestP0.uw = cDest.bits;
501 FpDestP1.uw = cDest.bits >> 32;
502 '''
503 vaddDIop = InstObjParams("vaddd", "VaddD", "VfpRegRegRegOp",
504 { "code": vaddDCode,
505 "predicate_test": predicateTest }, [])
506 header_output += VfpRegRegRegOpDeclare.subst(vaddDIop);
507 decoder_output += VfpRegRegRegOpConstructor.subst(vaddDIop);
508 exec_output += PredOpExecute.subst(vaddDIop);
509
510 vsubSCode = '''
511 vfpFlushToZero(Fpscr, FpOp1, FpOp2);
512 VfpSavedState state = prepVfpFpscr(Fpscr);
513 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
498 __asm__ __volatile__("" :: "m" (cDest.fp));
499 Fpscr = setVfpFpscr(Fpscr, state);
500 FpDestP0.uw = cDest.bits;
501 FpDestP1.uw = cDest.bits >> 32;
502 '''
503 vaddDIop = InstObjParams("vaddd", "VaddD", "VfpRegRegRegOp",
504 { "code": vaddDCode,
505 "predicate_test": predicateTest }, [])
506 header_output += VfpRegRegRegOpDeclare.subst(vaddDIop);
507 decoder_output += VfpRegRegRegOpConstructor.subst(vaddDIop);
508 exec_output += PredOpExecute.subst(vaddDIop);
509
510 vsubSCode = '''
511 vfpFlushToZero(Fpscr, FpOp1, FpOp2);
512 VfpSavedState state = prepVfpFpscr(Fpscr);
513 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
514 FpDest = FpOp1 - FpOp2;
514 FpDest = fixNan(Fpscr, FpOp1 - FpOp2, FpOp1, FpOp2);
515 __asm__ __volatile__("" :: "m" (FpDest));
516 Fpscr = setVfpFpscr(Fpscr, state)
517 '''
518 vsubSIop = InstObjParams("vsubs", "VsubS", "VfpRegRegRegOp",
519 { "code": vsubSCode,
520 "predicate_test": predicateTest }, [])
521 header_output += VfpRegRegRegOpDeclare.subst(vsubSIop);
522 decoder_output += VfpRegRegRegOpConstructor.subst(vsubSIop);
523 exec_output += PredOpExecute.subst(vsubSIop);
524
525 vsubDCode = '''
526 IntDoubleUnion cOp1, cOp2, cDest;
527 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
528 cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32));
529 vfpFlushToZero(Fpscr, cOp1.fp, cOp2.fp);
530 VfpSavedState state = prepVfpFpscr(Fpscr);
531 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp));
515 __asm__ __volatile__("" :: "m" (FpDest));
516 Fpscr = setVfpFpscr(Fpscr, state)
517 '''
518 vsubSIop = InstObjParams("vsubs", "VsubS", "VfpRegRegRegOp",
519 { "code": vsubSCode,
520 "predicate_test": predicateTest }, [])
521 header_output += VfpRegRegRegOpDeclare.subst(vsubSIop);
522 decoder_output += VfpRegRegRegOpConstructor.subst(vsubSIop);
523 exec_output += PredOpExecute.subst(vsubSIop);
524
525 vsubDCode = '''
526 IntDoubleUnion cOp1, cOp2, cDest;
527 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
528 cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32));
529 vfpFlushToZero(Fpscr, cOp1.fp, cOp2.fp);
530 VfpSavedState state = prepVfpFpscr(Fpscr);
531 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp));
532 cDest.fp = cOp1.fp - cOp2.fp;
532 cDest.fp = fixNan(Fpscr, cOp1.fp - cOp2.fp, cOp1.fp, cOp2.fp);
533 __asm__ __volatile__("" :: "m" (cDest.fp));
534 Fpscr = setVfpFpscr(Fpscr, state);
535 FpDestP0.uw = cDest.bits;
536 FpDestP1.uw = cDest.bits >> 32;
537 '''
538 vsubDIop = InstObjParams("vsubd", "VsubD", "VfpRegRegRegOp",
539 { "code": vsubDCode,
540 "predicate_test": predicateTest }, [])
541 header_output += VfpRegRegRegOpDeclare.subst(vsubDIop);
542 decoder_output += VfpRegRegRegOpConstructor.subst(vsubDIop);
543 exec_output += PredOpExecute.subst(vsubDIop);
544
545 vdivSCode = '''
546 vfpFlushToZero(Fpscr, FpOp1, FpOp2);
547 VfpSavedState state = prepVfpFpscr(Fpscr);
548 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
533 __asm__ __volatile__("" :: "m" (cDest.fp));
534 Fpscr = setVfpFpscr(Fpscr, state);
535 FpDestP0.uw = cDest.bits;
536 FpDestP1.uw = cDest.bits >> 32;
537 '''
538 vsubDIop = InstObjParams("vsubd", "VsubD", "VfpRegRegRegOp",
539 { "code": vsubDCode,
540 "predicate_test": predicateTest }, [])
541 header_output += VfpRegRegRegOpDeclare.subst(vsubDIop);
542 decoder_output += VfpRegRegRegOpConstructor.subst(vsubDIop);
543 exec_output += PredOpExecute.subst(vsubDIop);
544
545 vdivSCode = '''
546 vfpFlushToZero(Fpscr, FpOp1, FpOp2);
547 VfpSavedState state = prepVfpFpscr(Fpscr);
548 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
549 FpDest = FpOp1 / FpOp2;
549 FpDest = fixNan(Fpscr, FpOp1 / FpOp2, FpOp1, FpOp2);
550 __asm__ __volatile__("" :: "m" (FpDest));
551 Fpscr = setVfpFpscr(Fpscr, state);
552 '''
553 vdivSIop = InstObjParams("vdivs", "VdivS", "VfpRegRegRegOp",
554 { "code": vdivSCode,
555 "predicate_test": predicateTest }, [])
556 header_output += VfpRegRegRegOpDeclare.subst(vdivSIop);
557 decoder_output += VfpRegRegRegOpConstructor.subst(vdivSIop);
558 exec_output += PredOpExecute.subst(vdivSIop);
559
560 vdivDCode = '''
561 IntDoubleUnion cOp1, cOp2, cDest;
562 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
563 cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32));
564 vfpFlushToZero(Fpscr, cOp1.fp, cOp2.fp);
565 VfpSavedState state = prepVfpFpscr(Fpscr);
566 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cDest.fp));
550 __asm__ __volatile__("" :: "m" (FpDest));
551 Fpscr = setVfpFpscr(Fpscr, state);
552 '''
553 vdivSIop = InstObjParams("vdivs", "VdivS", "VfpRegRegRegOp",
554 { "code": vdivSCode,
555 "predicate_test": predicateTest }, [])
556 header_output += VfpRegRegRegOpDeclare.subst(vdivSIop);
557 decoder_output += VfpRegRegRegOpConstructor.subst(vdivSIop);
558 exec_output += PredOpExecute.subst(vdivSIop);
559
560 vdivDCode = '''
561 IntDoubleUnion cOp1, cOp2, cDest;
562 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
563 cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32));
564 vfpFlushToZero(Fpscr, cOp1.fp, cOp2.fp);
565 VfpSavedState state = prepVfpFpscr(Fpscr);
566 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cDest.fp));
567 cDest.fp = cOp1.fp / cOp2.fp;
567 cDest.fp = fixNan(Fpscr, cOp1.fp / cOp2.fp, cOp1.fp, cOp2.fp);
568 __asm__ __volatile__("" :: "m" (cDest.fp));
569 Fpscr = setVfpFpscr(Fpscr, state);
570 FpDestP0.uw = cDest.bits;
571 FpDestP1.uw = cDest.bits >> 32;
572 '''
573 vdivDIop = InstObjParams("vdivd", "VdivD", "VfpRegRegRegOp",
574 { "code": vdivDCode,
575 "predicate_test": predicateTest }, [])

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623 header_output = ""
624 decoder_output = ""
625 exec_output = ""
626
627 vmlaSCode = '''
628 vfpFlushToZero(Fpscr, FpOp1, FpOp2);
629 VfpSavedState state = prepVfpFpscr(Fpscr);
630 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
568 __asm__ __volatile__("" :: "m" (cDest.fp));
569 Fpscr = setVfpFpscr(Fpscr, state);
570 FpDestP0.uw = cDest.bits;
571 FpDestP1.uw = cDest.bits >> 32;
572 '''
573 vdivDIop = InstObjParams("vdivd", "VdivD", "VfpRegRegRegOp",
574 { "code": vdivDCode,
575 "predicate_test": predicateTest }, [])

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623 header_output = ""
624 decoder_output = ""
625 exec_output = ""
626
627 vmlaSCode = '''
628 vfpFlushToZero(Fpscr, FpOp1, FpOp2);
629 VfpSavedState state = prepVfpFpscr(Fpscr);
630 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
631 float mid = FpOp1 * FpOp2;
631 float mid = fixNan(Fpscr, FpOp1 * FpOp2, FpOp1, FpOp2);
632 if ((isinf(FpOp1) && FpOp2 == 0) || (isinf(FpOp2) && FpOp1 == 0)) {
633 mid = NAN;
634 }
635 vfpFlushToZero(Fpscr, FpDest, mid);
632 if ((isinf(FpOp1) && FpOp2 == 0) || (isinf(FpOp2) && FpOp1 == 0)) {
633 mid = NAN;
634 }
635 vfpFlushToZero(Fpscr, FpDest, mid);
636 FpDest = FpDest + mid;
636 FpDest = fixNan(Fpscr, FpDest + mid, FpDest, mid);
637 __asm__ __volatile__("" :: "m" (FpDest));
638 Fpscr = setVfpFpscr(Fpscr, state);
639 '''
640 vmlaSIop = InstObjParams("vmlas", "VmlaS", "VfpRegRegRegOp",
641 { "code": vmlaSCode,
642 "predicate_test": predicateTest }, [])
643 header_output += VfpRegRegRegOpDeclare.subst(vmlaSIop);
644 decoder_output += VfpRegRegRegOpConstructor.subst(vmlaSIop);
645 exec_output += PredOpExecute.subst(vmlaSIop);
646
647 vmlaDCode = '''
648 IntDoubleUnion cOp1, cOp2, cDest;
649 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
650 cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32));
651 cDest.bits = ((uint64_t)FpDestP0.uw | ((uint64_t)FpDestP1.uw << 32));
652 vfpFlushToZero(Fpscr, cOp1.fp, cOp2.fp);
653 VfpSavedState state = prepVfpFpscr(Fpscr);
654 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp));
637 __asm__ __volatile__("" :: "m" (FpDest));
638 Fpscr = setVfpFpscr(Fpscr, state);
639 '''
640 vmlaSIop = InstObjParams("vmlas", "VmlaS", "VfpRegRegRegOp",
641 { "code": vmlaSCode,
642 "predicate_test": predicateTest }, [])
643 header_output += VfpRegRegRegOpDeclare.subst(vmlaSIop);
644 decoder_output += VfpRegRegRegOpConstructor.subst(vmlaSIop);
645 exec_output += PredOpExecute.subst(vmlaSIop);
646
647 vmlaDCode = '''
648 IntDoubleUnion cOp1, cOp2, cDest;
649 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
650 cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32));
651 cDest.bits = ((uint64_t)FpDestP0.uw | ((uint64_t)FpDestP1.uw << 32));
652 vfpFlushToZero(Fpscr, cOp1.fp, cOp2.fp);
653 VfpSavedState state = prepVfpFpscr(Fpscr);
654 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp));
655 double mid = cOp1.fp * cOp2.fp;
655 double mid = fixNan(Fpscr, cOp1.fp * cOp2.fp, cOp1.fp, cOp2.fp);
656 if ((isinf(cOp1.fp) && cOp2.fp == 0) ||
657 (isinf(cOp2.fp) && cOp1.fp == 0)) {
658 mid = NAN;
659 }
660 vfpFlushToZero(Fpscr, cDest.fp, mid);
656 if ((isinf(cOp1.fp) && cOp2.fp == 0) ||
657 (isinf(cOp2.fp) && cOp1.fp == 0)) {
658 mid = NAN;
659 }
660 vfpFlushToZero(Fpscr, cDest.fp, mid);
661 cDest.fp = cDest.fp + mid;
661 cDest.fp = fixNan(Fpscr, cDest.fp + mid, cDest.fp, mid);
662 __asm__ __volatile__("" :: "m" (cDest.fp));
663 Fpscr = setVfpFpscr(Fpscr, state);
664 FpDestP0.uw = cDest.bits;
665 FpDestP1.uw = cDest.bits >> 32;
666 '''
667 vmlaDIop = InstObjParams("vmlad", "VmlaD", "VfpRegRegRegOp",
668 { "code": vmlaDCode,
669 "predicate_test": predicateTest }, [])
670 header_output += VfpRegRegRegOpDeclare.subst(vmlaDIop);
671 decoder_output += VfpRegRegRegOpConstructor.subst(vmlaDIop);
672 exec_output += PredOpExecute.subst(vmlaDIop);
673
674 vmlsSCode = '''
675 vfpFlushToZero(Fpscr, FpOp1, FpOp2);
676 VfpSavedState state = prepVfpFpscr(Fpscr);
677 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
662 __asm__ __volatile__("" :: "m" (cDest.fp));
663 Fpscr = setVfpFpscr(Fpscr, state);
664 FpDestP0.uw = cDest.bits;
665 FpDestP1.uw = cDest.bits >> 32;
666 '''
667 vmlaDIop = InstObjParams("vmlad", "VmlaD", "VfpRegRegRegOp",
668 { "code": vmlaDCode,
669 "predicate_test": predicateTest }, [])
670 header_output += VfpRegRegRegOpDeclare.subst(vmlaDIop);
671 decoder_output += VfpRegRegRegOpConstructor.subst(vmlaDIop);
672 exec_output += PredOpExecute.subst(vmlaDIop);
673
674 vmlsSCode = '''
675 vfpFlushToZero(Fpscr, FpOp1, FpOp2);
676 VfpSavedState state = prepVfpFpscr(Fpscr);
677 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
678 float mid = FpOp1 * FpOp2;
678 float mid = fixNan(Fpscr, FpOp1 * FpOp2, FpOp1, FpOp2);
679 if ((isinf(FpOp1) && FpOp2 == 0) || (isinf(FpOp2) && FpOp1 == 0)) {
680 mid = NAN;
681 }
682 vfpFlushToZero(Fpscr, FpDest, mid);
679 if ((isinf(FpOp1) && FpOp2 == 0) || (isinf(FpOp2) && FpOp1 == 0)) {
680 mid = NAN;
681 }
682 vfpFlushToZero(Fpscr, FpDest, mid);
683 FpDest = FpDest - mid;
683 FpDest = fixNan(Fpscr, FpDest - mid, FpDest, mid);
684 __asm__ __volatile__("" :: "m" (FpDest));
685 Fpscr = setVfpFpscr(Fpscr, state);
686 '''
687 vmlsSIop = InstObjParams("vmlss", "VmlsS", "VfpRegRegRegOp",
688 { "code": vmlsSCode,
689 "predicate_test": predicateTest }, [])
690 header_output += VfpRegRegRegOpDeclare.subst(vmlsSIop);
691 decoder_output += VfpRegRegRegOpConstructor.subst(vmlsSIop);
692 exec_output += PredOpExecute.subst(vmlsSIop);
693
694 vmlsDCode = '''
695 IntDoubleUnion cOp1, cOp2, cDest;
696 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
697 cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32));
698 cDest.bits = ((uint64_t)FpDestP0.uw | ((uint64_t)FpDestP1.uw << 32));
699 vfpFlushToZero(Fpscr, cOp1.fp, cOp2.fp);
700 VfpSavedState state = prepVfpFpscr(Fpscr);
701 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp));
684 __asm__ __volatile__("" :: "m" (FpDest));
685 Fpscr = setVfpFpscr(Fpscr, state);
686 '''
687 vmlsSIop = InstObjParams("vmlss", "VmlsS", "VfpRegRegRegOp",
688 { "code": vmlsSCode,
689 "predicate_test": predicateTest }, [])
690 header_output += VfpRegRegRegOpDeclare.subst(vmlsSIop);
691 decoder_output += VfpRegRegRegOpConstructor.subst(vmlsSIop);
692 exec_output += PredOpExecute.subst(vmlsSIop);
693
694 vmlsDCode = '''
695 IntDoubleUnion cOp1, cOp2, cDest;
696 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
697 cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32));
698 cDest.bits = ((uint64_t)FpDestP0.uw | ((uint64_t)FpDestP1.uw << 32));
699 vfpFlushToZero(Fpscr, cOp1.fp, cOp2.fp);
700 VfpSavedState state = prepVfpFpscr(Fpscr);
701 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp));
702 double mid = cOp1.fp * cOp2.fp;
702 double mid = fixNan(Fpscr, cOp1.fp * cOp2.fp, cOp1.fp, cOp2.fp);
703 if ((isinf(cOp1.fp) && cOp2.fp == 0) ||
704 (isinf(cOp2.fp) && cOp1.fp == 0)) {
705 mid = NAN;
706 }
703 if ((isinf(cOp1.fp) && cOp2.fp == 0) ||
704 (isinf(cOp2.fp) && cOp1.fp == 0)) {
705 mid = NAN;
706 }
707 cDest.fp = cDest.fp - mid;
707 cDest.fp = fixNan(Fpscr, cDest.fp - mid, cDest.fp, mid);
708 vfpFlushToZero(Fpscr, cDest.fp, mid);
709 __asm__ __volatile__("" :: "m" (cDest.fp));
710 Fpscr = setVfpFpscr(Fpscr, state);
711 FpDestP0.uw = cDest.bits;
712 FpDestP1.uw = cDest.bits >> 32;
713 '''
714 vmlsDIop = InstObjParams("vmlsd", "VmlsD", "VfpRegRegRegOp",
715 { "code": vmlsDCode,
716 "predicate_test": predicateTest }, [])
717 header_output += VfpRegRegRegOpDeclare.subst(vmlsDIop);
718 decoder_output += VfpRegRegRegOpConstructor.subst(vmlsDIop);
719 exec_output += PredOpExecute.subst(vmlsDIop);
720
721 vnmlaSCode = '''
722 vfpFlushToZero(Fpscr, FpOp1, FpOp2);
723 VfpSavedState state = prepVfpFpscr(Fpscr);
724 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
708 vfpFlushToZero(Fpscr, cDest.fp, mid);
709 __asm__ __volatile__("" :: "m" (cDest.fp));
710 Fpscr = setVfpFpscr(Fpscr, state);
711 FpDestP0.uw = cDest.bits;
712 FpDestP1.uw = cDest.bits >> 32;
713 '''
714 vmlsDIop = InstObjParams("vmlsd", "VmlsD", "VfpRegRegRegOp",
715 { "code": vmlsDCode,
716 "predicate_test": predicateTest }, [])
717 header_output += VfpRegRegRegOpDeclare.subst(vmlsDIop);
718 decoder_output += VfpRegRegRegOpConstructor.subst(vmlsDIop);
719 exec_output += PredOpExecute.subst(vmlsDIop);
720
721 vnmlaSCode = '''
722 vfpFlushToZero(Fpscr, FpOp1, FpOp2);
723 VfpSavedState state = prepVfpFpscr(Fpscr);
724 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
725 float mid = FpOp1 * FpOp2;
725 float mid = fixNan(Fpscr, FpOp1 * FpOp2, FpOp1, FpOp2);
726 if ((isinf(FpOp1) && FpOp2 == 0) || (isinf(FpOp2) && FpOp1 == 0)) {
727 mid = NAN;
728 }
729 vfpFlushToZero(Fpscr, FpDest, mid);
726 if ((isinf(FpOp1) && FpOp2 == 0) || (isinf(FpOp2) && FpOp1 == 0)) {
727 mid = NAN;
728 }
729 vfpFlushToZero(Fpscr, FpDest, mid);
730 FpDest = -FpDest - mid;
730 FpDest = fixNan(Fpscr, -FpDest - mid, FpDest, mid);
731 __asm__ __volatile__("" :: "m" (FpDest));
732 Fpscr = setVfpFpscr(Fpscr, state);
733 '''
734 vnmlaSIop = InstObjParams("vnmlas", "VnmlaS", "VfpRegRegRegOp",
735 { "code": vnmlaSCode,
736 "predicate_test": predicateTest }, [])
737 header_output += VfpRegRegRegOpDeclare.subst(vnmlaSIop);
738 decoder_output += VfpRegRegRegOpConstructor.subst(vnmlaSIop);
739 exec_output += PredOpExecute.subst(vnmlaSIop);
740
741 vnmlaDCode = '''
742 IntDoubleUnion cOp1, cOp2, cDest;
743 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
744 cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32));
745 cDest.bits = ((uint64_t)FpDestP0.uw | ((uint64_t)FpDestP1.uw << 32));
746 vfpFlushToZero(Fpscr, cOp1.fp, cOp2.fp);
747 VfpSavedState state = prepVfpFpscr(Fpscr);
748 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp));
731 __asm__ __volatile__("" :: "m" (FpDest));
732 Fpscr = setVfpFpscr(Fpscr, state);
733 '''
734 vnmlaSIop = InstObjParams("vnmlas", "VnmlaS", "VfpRegRegRegOp",
735 { "code": vnmlaSCode,
736 "predicate_test": predicateTest }, [])
737 header_output += VfpRegRegRegOpDeclare.subst(vnmlaSIop);
738 decoder_output += VfpRegRegRegOpConstructor.subst(vnmlaSIop);
739 exec_output += PredOpExecute.subst(vnmlaSIop);
740
741 vnmlaDCode = '''
742 IntDoubleUnion cOp1, cOp2, cDest;
743 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
744 cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32));
745 cDest.bits = ((uint64_t)FpDestP0.uw | ((uint64_t)FpDestP1.uw << 32));
746 vfpFlushToZero(Fpscr, cOp1.fp, cOp2.fp);
747 VfpSavedState state = prepVfpFpscr(Fpscr);
748 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp));
749 double mid = cOp1.fp * cOp2.fp;
749 double mid = fixNan(Fpscr, cOp1.fp * cOp2.fp, cOp1.fp, cOp2.fp);
750 if ((isinf(cOp1.fp) && cOp2.fp == 0) ||
751 (isinf(cOp2.fp) && cOp1.fp == 0)) {
752 mid = NAN;
753 }
754 vfpFlushToZero(Fpscr, cDest.fp, mid);
750 if ((isinf(cOp1.fp) && cOp2.fp == 0) ||
751 (isinf(cOp2.fp) && cOp1.fp == 0)) {
752 mid = NAN;
753 }
754 vfpFlushToZero(Fpscr, cDest.fp, mid);
755 cDest.fp = -cDest.fp - mid;
755 cDest.fp = fixNan(Fpscr, -cDest.fp - mid, cDest.fp, mid);
756 __asm__ __volatile__("" :: "m" (cDest.fp));
757 Fpscr = setVfpFpscr(Fpscr, state);
758 FpDestP0.uw = cDest.bits;
759 FpDestP1.uw = cDest.bits >> 32;
760 '''
761 vnmlaDIop = InstObjParams("vnmlad", "VnmlaD", "VfpRegRegRegOp",
762 { "code": vnmlaDCode,
763 "predicate_test": predicateTest }, [])
764 header_output += VfpRegRegRegOpDeclare.subst(vnmlaDIop);
765 decoder_output += VfpRegRegRegOpConstructor.subst(vnmlaDIop);
766 exec_output += PredOpExecute.subst(vnmlaDIop);
767
768 vnmlsSCode = '''
769 vfpFlushToZero(Fpscr, FpOp1, FpOp2);
770 VfpSavedState state = prepVfpFpscr(Fpscr);
771 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
756 __asm__ __volatile__("" :: "m" (cDest.fp));
757 Fpscr = setVfpFpscr(Fpscr, state);
758 FpDestP0.uw = cDest.bits;
759 FpDestP1.uw = cDest.bits >> 32;
760 '''
761 vnmlaDIop = InstObjParams("vnmlad", "VnmlaD", "VfpRegRegRegOp",
762 { "code": vnmlaDCode,
763 "predicate_test": predicateTest }, [])
764 header_output += VfpRegRegRegOpDeclare.subst(vnmlaDIop);
765 decoder_output += VfpRegRegRegOpConstructor.subst(vnmlaDIop);
766 exec_output += PredOpExecute.subst(vnmlaDIop);
767
768 vnmlsSCode = '''
769 vfpFlushToZero(Fpscr, FpOp1, FpOp2);
770 VfpSavedState state = prepVfpFpscr(Fpscr);
771 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
772 float mid = FpOp1 * FpOp2;
772 float mid = fixNan(Fpscr, FpOp1 * FpOp2, FpOp1, FpOp2);
773 if ((isinf(FpOp1) && FpOp2 == 0) || (isinf(FpOp2) && FpOp1 == 0)) {
774 mid = NAN;
775 }
776 vfpFlushToZero(Fpscr, FpDest, mid);
773 if ((isinf(FpOp1) && FpOp2 == 0) || (isinf(FpOp2) && FpOp1 == 0)) {
774 mid = NAN;
775 }
776 vfpFlushToZero(Fpscr, FpDest, mid);
777 FpDest = -FpDest + mid;
777 FpDest = fixNan(Fpscr, -FpDest + mid, FpDest, mid);
778 __asm__ __volatile__("" :: "m" (FpDest));
779 Fpscr = setVfpFpscr(Fpscr, state);
780 '''
781 vnmlsSIop = InstObjParams("vnmlss", "VnmlsS", "VfpRegRegRegOp",
782 { "code": vnmlsSCode,
783 "predicate_test": predicateTest }, [])
784 header_output += VfpRegRegRegOpDeclare.subst(vnmlsSIop);
785 decoder_output += VfpRegRegRegOpConstructor.subst(vnmlsSIop);
786 exec_output += PredOpExecute.subst(vnmlsSIop);
787
788 vnmlsDCode = '''
789 IntDoubleUnion cOp1, cOp2, cDest;
790 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
791 cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32));
792 cDest.bits = ((uint64_t)FpDestP0.uw | ((uint64_t)FpDestP1.uw << 32));
793 vfpFlushToZero(Fpscr, cOp1.fp, cOp2.fp);
794 VfpSavedState state = prepVfpFpscr(Fpscr);
795 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp));
778 __asm__ __volatile__("" :: "m" (FpDest));
779 Fpscr = setVfpFpscr(Fpscr, state);
780 '''
781 vnmlsSIop = InstObjParams("vnmlss", "VnmlsS", "VfpRegRegRegOp",
782 { "code": vnmlsSCode,
783 "predicate_test": predicateTest }, [])
784 header_output += VfpRegRegRegOpDeclare.subst(vnmlsSIop);
785 decoder_output += VfpRegRegRegOpConstructor.subst(vnmlsSIop);
786 exec_output += PredOpExecute.subst(vnmlsSIop);
787
788 vnmlsDCode = '''
789 IntDoubleUnion cOp1, cOp2, cDest;
790 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
791 cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32));
792 cDest.bits = ((uint64_t)FpDestP0.uw | ((uint64_t)FpDestP1.uw << 32));
793 vfpFlushToZero(Fpscr, cOp1.fp, cOp2.fp);
794 VfpSavedState state = prepVfpFpscr(Fpscr);
795 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp));
796 double mid = cOp1.fp * cOp2.fp;
796 double mid = fixNan(Fpscr, cOp1.fp * cOp2.fp, cOp1.fp, cOp2.fp);
797 if ((isinf(cOp1.fp) && cOp2.fp == 0) ||
798 (isinf(cOp2.fp) && cOp1.fp == 0)) {
799 mid = NAN;
800 }
801 vfpFlushToZero(Fpscr, cDest.fp, mid);
797 if ((isinf(cOp1.fp) && cOp2.fp == 0) ||
798 (isinf(cOp2.fp) && cOp1.fp == 0)) {
799 mid = NAN;
800 }
801 vfpFlushToZero(Fpscr, cDest.fp, mid);
802 cDest.fp = -cDest.fp + mid;
802 cDest.fp = fixNan(Fpscr, -cDest.fp + mid, cDest.fp, mid);
803 __asm__ __volatile__("" :: "m" (cDest.fp));
804 Fpscr = setVfpFpscr(Fpscr, state);
805 FpDestP0.uw = cDest.bits;
806 FpDestP1.uw = cDest.bits >> 32;
807 '''
808 vnmlsDIop = InstObjParams("vnmlsd", "VnmlsD", "VfpRegRegRegOp",
809 { "code": vnmlsDCode,
810 "predicate_test": predicateTest }, [])
811 header_output += VfpRegRegRegOpDeclare.subst(vnmlsDIop);
812 decoder_output += VfpRegRegRegOpConstructor.subst(vnmlsDIop);
813 exec_output += PredOpExecute.subst(vnmlsDIop);
814
815 vnmulSCode = '''
816 vfpFlushToZero(Fpscr, FpOp1, FpOp2);
817 VfpSavedState state = prepVfpFpscr(Fpscr);
818 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
803 __asm__ __volatile__("" :: "m" (cDest.fp));
804 Fpscr = setVfpFpscr(Fpscr, state);
805 FpDestP0.uw = cDest.bits;
806 FpDestP1.uw = cDest.bits >> 32;
807 '''
808 vnmlsDIop = InstObjParams("vnmlsd", "VnmlsD", "VfpRegRegRegOp",
809 { "code": vnmlsDCode,
810 "predicate_test": predicateTest }, [])
811 header_output += VfpRegRegRegOpDeclare.subst(vnmlsDIop);
812 decoder_output += VfpRegRegRegOpConstructor.subst(vnmlsDIop);
813 exec_output += PredOpExecute.subst(vnmlsDIop);
814
815 vnmulSCode = '''
816 vfpFlushToZero(Fpscr, FpOp1, FpOp2);
817 VfpSavedState state = prepVfpFpscr(Fpscr);
818 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
819 float mid = FpOp1 * FpOp2;
819 float mid = fixNan(Fpscr, FpOp1 * FpOp2, FpOp1, FpOp2);
820 if ((isinf(FpOp1) && FpOp2 == 0) || (isinf(FpOp2) && FpOp1 == 0)) {
821 mid = NAN;
822 }
823 FpDest = -mid;
824 __asm__ __volatile__("" :: "m" (FpDest));
825 Fpscr = setVfpFpscr(Fpscr, state);
826 '''
827 vnmulSIop = InstObjParams("vnmuls", "VnmulS", "VfpRegRegRegOp",

--- 6 unchanged lines hidden (view full) ---

834 vnmulDCode = '''
835 IntDoubleUnion cOp1, cOp2, cDest;
836 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
837 cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32));
838 cDest.bits = ((uint64_t)FpDestP0.uw | ((uint64_t)FpDestP1.uw << 32));
839 vfpFlushToZero(Fpscr, cOp1.fp, cOp2.fp);
840 VfpSavedState state = prepVfpFpscr(Fpscr);
841 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp));
820 if ((isinf(FpOp1) && FpOp2 == 0) || (isinf(FpOp2) && FpOp1 == 0)) {
821 mid = NAN;
822 }
823 FpDest = -mid;
824 __asm__ __volatile__("" :: "m" (FpDest));
825 Fpscr = setVfpFpscr(Fpscr, state);
826 '''
827 vnmulSIop = InstObjParams("vnmuls", "VnmulS", "VfpRegRegRegOp",

--- 6 unchanged lines hidden (view full) ---

834 vnmulDCode = '''
835 IntDoubleUnion cOp1, cOp2, cDest;
836 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
837 cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32));
838 cDest.bits = ((uint64_t)FpDestP0.uw | ((uint64_t)FpDestP1.uw << 32));
839 vfpFlushToZero(Fpscr, cOp1.fp, cOp2.fp);
840 VfpSavedState state = prepVfpFpscr(Fpscr);
841 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp));
842 double mid = cOp1.fp * cOp2.fp;
842 double mid = fixNan(Fpscr, cOp1.fp * cOp2.fp, cOp1.fp, cOp2.fp);
843 if ((isinf(cOp1.fp) && cOp2.fp == 0) ||
844 (isinf(cOp2.fp) && cOp1.fp == 0)) {
845 mid = NAN;
846 }
847 cDest.fp = -mid;
848 __asm__ __volatile__("" :: "m" (cDest.fp));
849 Fpscr = setVfpFpscr(Fpscr, state);
850 FpDestP0.uw = cDest.bits;

--- 617 unchanged lines hidden --- 		843 if ((isinf(cOp1.fp) && cOp2.fp == 0) ||
844 (isinf(cOp2.fp) && cOp1.fp == 0)) {
845 mid = NAN;
846 }
847 cDest.fp = -mid;
848 __asm__ __volatile__("" :: "m" (cDest.fp));
849 Fpscr = setVfpFpscr(Fpscr, state);
850 FpDestP0.uw = cDest.bits;

--- 617 unchanged lines hidden ---