fp.isa (7381:bc68c91e9814) fp.isa (7382:b3c768629a54)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 369 unchanged lines hidden (view full) ---

378
379let {{
380
381 header_output = ""
382 decoder_output = ""
383 exec_output = ""
384
385 vmulSCode = '''
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 369 unchanged lines hidden (view full) ---

378
379let {{
380
381 header_output = ""
382 decoder_output = ""
383 exec_output = ""
384
385 vmulSCode = '''
386 vfpFlushToZero(Fpscr, FpOp1, FpOp2);
386 VfpSavedState state = prepVfpFpscr(Fpscr);
387 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
388 FpDest = FpOp1 * FpOp2;
389 __asm__ __volatile__("" :: "m" (FpDest));
390 Fpscr = setVfpFpscr(Fpscr, state);
391 if ((isinf(FpOp1) && FpOp2 == 0) || (isinf(FpOp2) && FpOp1 == 0)) {
392 FpDest = NAN;
393 }

--- 4 unchanged lines hidden (view full) ---

398 header_output += VfpRegRegRegOpDeclare.subst(vmulSIop);
399 decoder_output += VfpRegRegRegOpConstructor.subst(vmulSIop);
400 exec_output += PredOpExecute.subst(vmulSIop);
401
402 vmulDCode = '''
403 IntDoubleUnion cOp1, cOp2, cDest;
404 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
405 cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32));
387 VfpSavedState state = prepVfpFpscr(Fpscr);
388 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
389 FpDest = FpOp1 * FpOp2;
390 __asm__ __volatile__("" :: "m" (FpDest));
391 Fpscr = setVfpFpscr(Fpscr, state);
392 if ((isinf(FpOp1) && FpOp2 == 0) || (isinf(FpOp2) && FpOp1 == 0)) {
393 FpDest = NAN;
394 }

--- 4 unchanged lines hidden (view full) ---

399 header_output += VfpRegRegRegOpDeclare.subst(vmulSIop);
400 decoder_output += VfpRegRegRegOpConstructor.subst(vmulSIop);
401 exec_output += PredOpExecute.subst(vmulSIop);
402
403 vmulDCode = '''
404 IntDoubleUnion cOp1, cOp2, cDest;
405 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
406 cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32));
407 vfpFlushToZero(Fpscr, cOp1.fp, cOp2.fp);
406 VfpSavedState state = prepVfpFpscr(Fpscr);
407 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp));
408 cDest.fp = cOp1.fp * cOp2.fp;
409 __asm__ __volatile__("" :: "m" (cDest.fp));
410 Fpscr = setVfpFpscr(Fpscr, state);
411 if ((isinf(cOp1.fp) && cOp2.fp == 0) ||
412 (isinf(cOp2.fp) && cOp1.fp == 0)) {
413 cDest.fp = NAN;

--- 52 unchanged lines hidden (view full) ---

466 vabsDIop = InstObjParams("vabsd", "VabsD", "VfpRegRegOp",
467 { "code": vabsDCode,
468 "predicate_test": predicateTest }, [])
469 header_output += VfpRegRegOpDeclare.subst(vabsDIop);
470 decoder_output += VfpRegRegOpConstructor.subst(vabsDIop);
471 exec_output += PredOpExecute.subst(vabsDIop);
472
473 vaddSCode = '''
408 VfpSavedState state = prepVfpFpscr(Fpscr);
409 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp));
410 cDest.fp = cOp1.fp * cOp2.fp;
411 __asm__ __volatile__("" :: "m" (cDest.fp));
412 Fpscr = setVfpFpscr(Fpscr, state);
413 if ((isinf(cOp1.fp) && cOp2.fp == 0) ||
414 (isinf(cOp2.fp) && cOp1.fp == 0)) {
415 cDest.fp = NAN;

--- 52 unchanged lines hidden (view full) ---

468 vabsDIop = InstObjParams("vabsd", "VabsD", "VfpRegRegOp",
469 { "code": vabsDCode,
470 "predicate_test": predicateTest }, [])
471 header_output += VfpRegRegOpDeclare.subst(vabsDIop);
472 decoder_output += VfpRegRegOpConstructor.subst(vabsDIop);
473 exec_output += PredOpExecute.subst(vabsDIop);
474
475 vaddSCode = '''
476 vfpFlushToZero(Fpscr, FpOp1, FpOp2);
474 VfpSavedState state = prepVfpFpscr(Fpscr);
475 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
476 FpDest = FpOp1 + FpOp2;
477 __asm__ __volatile__("" :: "m" (FpDest));
478 Fpscr = setVfpFpscr(Fpscr, state);
479 '''
480 vaddSIop = InstObjParams("vadds", "VaddS", "VfpRegRegRegOp",
481 { "code": vaddSCode,
482 "predicate_test": predicateTest }, [])
483 header_output += VfpRegRegRegOpDeclare.subst(vaddSIop);
484 decoder_output += VfpRegRegRegOpConstructor.subst(vaddSIop);
485 exec_output += PredOpExecute.subst(vaddSIop);
486
487 vaddDCode = '''
488 IntDoubleUnion cOp1, cOp2, cDest;
489 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
490 cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32));
477 VfpSavedState state = prepVfpFpscr(Fpscr);
478 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
479 FpDest = FpOp1 + FpOp2;
480 __asm__ __volatile__("" :: "m" (FpDest));
481 Fpscr = setVfpFpscr(Fpscr, state);
482 '''
483 vaddSIop = InstObjParams("vadds", "VaddS", "VfpRegRegRegOp",
484 { "code": vaddSCode,
485 "predicate_test": predicateTest }, [])
486 header_output += VfpRegRegRegOpDeclare.subst(vaddSIop);
487 decoder_output += VfpRegRegRegOpConstructor.subst(vaddSIop);
488 exec_output += PredOpExecute.subst(vaddSIop);
489
490 vaddDCode = '''
491 IntDoubleUnion cOp1, cOp2, cDest;
492 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
493 cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32));
494 vfpFlushToZero(Fpscr, cOp1.fp, cOp2.fp);
491 VfpSavedState state = prepVfpFpscr(Fpscr);
492 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp));
493 cDest.fp = cOp1.fp + cOp2.fp;
494 __asm__ __volatile__("" :: "m" (cDest.fp));
495 Fpscr = setVfpFpscr(Fpscr, state);
496 FpDestP0.uw = cDest.bits;
497 FpDestP1.uw = cDest.bits >> 32;
498 '''
499 vaddDIop = InstObjParams("vaddd", "VaddD", "VfpRegRegRegOp",
500 { "code": vaddDCode,
501 "predicate_test": predicateTest }, [])
502 header_output += VfpRegRegRegOpDeclare.subst(vaddDIop);
503 decoder_output += VfpRegRegRegOpConstructor.subst(vaddDIop);
504 exec_output += PredOpExecute.subst(vaddDIop);
505
506 vsubSCode = '''
495 VfpSavedState state = prepVfpFpscr(Fpscr);
496 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp));
497 cDest.fp = cOp1.fp + cOp2.fp;
498 __asm__ __volatile__("" :: "m" (cDest.fp));
499 Fpscr = setVfpFpscr(Fpscr, state);
500 FpDestP0.uw = cDest.bits;
501 FpDestP1.uw = cDest.bits >> 32;
502 '''
503 vaddDIop = InstObjParams("vaddd", "VaddD", "VfpRegRegRegOp",
504 { "code": vaddDCode,
505 "predicate_test": predicateTest }, [])
506 header_output += VfpRegRegRegOpDeclare.subst(vaddDIop);
507 decoder_output += VfpRegRegRegOpConstructor.subst(vaddDIop);
508 exec_output += PredOpExecute.subst(vaddDIop);
509
510 vsubSCode = '''
511 vfpFlushToZero(Fpscr, FpOp1, FpOp2);
507 VfpSavedState state = prepVfpFpscr(Fpscr);
508 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
509 FpDest = FpOp1 - FpOp2;
510 __asm__ __volatile__("" :: "m" (FpDest));
511 Fpscr = setVfpFpscr(Fpscr, state)
512 '''
513 vsubSIop = InstObjParams("vsubs", "VsubS", "VfpRegRegRegOp",
514 { "code": vsubSCode,
515 "predicate_test": predicateTest }, [])
516 header_output += VfpRegRegRegOpDeclare.subst(vsubSIop);
517 decoder_output += VfpRegRegRegOpConstructor.subst(vsubSIop);
518 exec_output += PredOpExecute.subst(vsubSIop);
519
520 vsubDCode = '''
521 IntDoubleUnion cOp1, cOp2, cDest;
522 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
523 cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32));
512 VfpSavedState state = prepVfpFpscr(Fpscr);
513 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
514 FpDest = FpOp1 - FpOp2;
515 __asm__ __volatile__("" :: "m" (FpDest));
516 Fpscr = setVfpFpscr(Fpscr, state)
517 '''
518 vsubSIop = InstObjParams("vsubs", "VsubS", "VfpRegRegRegOp",
519 { "code": vsubSCode,
520 "predicate_test": predicateTest }, [])
521 header_output += VfpRegRegRegOpDeclare.subst(vsubSIop);
522 decoder_output += VfpRegRegRegOpConstructor.subst(vsubSIop);
523 exec_output += PredOpExecute.subst(vsubSIop);
524
525 vsubDCode = '''
526 IntDoubleUnion cOp1, cOp2, cDest;
527 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
528 cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32));
529 vfpFlushToZero(Fpscr, cOp1.fp, cOp2.fp);
524 VfpSavedState state = prepVfpFpscr(Fpscr);
525 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp));
526 cDest.fp = cOp1.fp - cOp2.fp;
527 __asm__ __volatile__("" :: "m" (cDest.fp));
528 Fpscr = setVfpFpscr(Fpscr, state);
529 FpDestP0.uw = cDest.bits;
530 FpDestP1.uw = cDest.bits >> 32;
531 '''
532 vsubDIop = InstObjParams("vsubd", "VsubD", "VfpRegRegRegOp",
533 { "code": vsubDCode,
534 "predicate_test": predicateTest }, [])
535 header_output += VfpRegRegRegOpDeclare.subst(vsubDIop);
536 decoder_output += VfpRegRegRegOpConstructor.subst(vsubDIop);
537 exec_output += PredOpExecute.subst(vsubDIop);
538
539 vdivSCode = '''
530 VfpSavedState state = prepVfpFpscr(Fpscr);
531 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp));
532 cDest.fp = cOp1.fp - cOp2.fp;
533 __asm__ __volatile__("" :: "m" (cDest.fp));
534 Fpscr = setVfpFpscr(Fpscr, state);
535 FpDestP0.uw = cDest.bits;
536 FpDestP1.uw = cDest.bits >> 32;
537 '''
538 vsubDIop = InstObjParams("vsubd", "VsubD", "VfpRegRegRegOp",
539 { "code": vsubDCode,
540 "predicate_test": predicateTest }, [])
541 header_output += VfpRegRegRegOpDeclare.subst(vsubDIop);
542 decoder_output += VfpRegRegRegOpConstructor.subst(vsubDIop);
543 exec_output += PredOpExecute.subst(vsubDIop);
544
545 vdivSCode = '''
546 vfpFlushToZero(Fpscr, FpOp1, FpOp2);
540 VfpSavedState state = prepVfpFpscr(Fpscr);
541 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
542 FpDest = FpOp1 / FpOp2;
543 __asm__ __volatile__("" :: "m" (FpDest));
544 Fpscr = setVfpFpscr(Fpscr, state);
545 '''
546 vdivSIop = InstObjParams("vdivs", "VdivS", "VfpRegRegRegOp",
547 { "code": vdivSCode,
548 "predicate_test": predicateTest }, [])
549 header_output += VfpRegRegRegOpDeclare.subst(vdivSIop);
550 decoder_output += VfpRegRegRegOpConstructor.subst(vdivSIop);
551 exec_output += PredOpExecute.subst(vdivSIop);
552
553 vdivDCode = '''
554 IntDoubleUnion cOp1, cOp2, cDest;
555 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
556 cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32));
547 VfpSavedState state = prepVfpFpscr(Fpscr);
548 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
549 FpDest = FpOp1 / FpOp2;
550 __asm__ __volatile__("" :: "m" (FpDest));
551 Fpscr = setVfpFpscr(Fpscr, state);
552 '''
553 vdivSIop = InstObjParams("vdivs", "VdivS", "VfpRegRegRegOp",
554 { "code": vdivSCode,
555 "predicate_test": predicateTest }, [])
556 header_output += VfpRegRegRegOpDeclare.subst(vdivSIop);
557 decoder_output += VfpRegRegRegOpConstructor.subst(vdivSIop);
558 exec_output += PredOpExecute.subst(vdivSIop);
559
560 vdivDCode = '''
561 IntDoubleUnion cOp1, cOp2, cDest;
562 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
563 cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32));
564 vfpFlushToZero(Fpscr, cOp1.fp, cOp2.fp);
557 VfpSavedState state = prepVfpFpscr(Fpscr);
558 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cDest.fp));
559 cDest.fp = cOp1.fp / cOp2.fp;
560 __asm__ __volatile__("" :: "m" (cDest.fp));
561 Fpscr = setVfpFpscr(Fpscr, state);
562 FpDestP0.uw = cDest.bits;
563 FpDestP1.uw = cDest.bits >> 32;
564 '''
565 vdivDIop = InstObjParams("vdivd", "VdivD", "VfpRegRegRegOp",
566 { "code": vdivDCode,
567 "predicate_test": predicateTest }, [])
568 header_output += VfpRegRegRegOpDeclare.subst(vdivDIop);
569 decoder_output += VfpRegRegRegOpConstructor.subst(vdivDIop);
570 exec_output += PredOpExecute.subst(vdivDIop);
571
572 vsqrtSCode = '''
565 VfpSavedState state = prepVfpFpscr(Fpscr);
566 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cDest.fp));
567 cDest.fp = cOp1.fp / cOp2.fp;
568 __asm__ __volatile__("" :: "m" (cDest.fp));
569 Fpscr = setVfpFpscr(Fpscr, state);
570 FpDestP0.uw = cDest.bits;
571 FpDestP1.uw = cDest.bits >> 32;
572 '''
573 vdivDIop = InstObjParams("vdivd", "VdivD", "VfpRegRegRegOp",
574 { "code": vdivDCode,
575 "predicate_test": predicateTest }, [])
576 header_output += VfpRegRegRegOpDeclare.subst(vdivDIop);
577 decoder_output += VfpRegRegRegOpConstructor.subst(vdivDIop);
578 exec_output += PredOpExecute.subst(vdivDIop);
579
580 vsqrtSCode = '''
581 vfpFlushToZero(Fpscr, FpOp1);
573 VfpSavedState state = prepVfpFpscr(Fpscr);
574 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
575 FpDest = sqrtf(FpOp1);
576 __asm__ __volatile__("" :: "m" (FpDest));
577 Fpscr = setVfpFpscr(Fpscr, state);
578 if (FpOp1 < 0) {
579 FpDest = NAN;
580 }
581 '''
582 vsqrtSIop = InstObjParams("vsqrts", "VsqrtS", "VfpRegRegOp",
583 { "code": vsqrtSCode,
584 "predicate_test": predicateTest }, [])
585 header_output += VfpRegRegOpDeclare.subst(vsqrtSIop);
586 decoder_output += VfpRegRegOpConstructor.subst(vsqrtSIop);
587 exec_output += PredOpExecute.subst(vsqrtSIop);
588
589 vsqrtDCode = '''
590 IntDoubleUnion cOp1, cDest;
591 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
582 VfpSavedState state = prepVfpFpscr(Fpscr);
583 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
584 FpDest = sqrtf(FpOp1);
585 __asm__ __volatile__("" :: "m" (FpDest));
586 Fpscr = setVfpFpscr(Fpscr, state);
587 if (FpOp1 < 0) {
588 FpDest = NAN;
589 }
590 '''
591 vsqrtSIop = InstObjParams("vsqrts", "VsqrtS", "VfpRegRegOp",
592 { "code": vsqrtSCode,
593 "predicate_test": predicateTest }, [])
594 header_output += VfpRegRegOpDeclare.subst(vsqrtSIop);
595 decoder_output += VfpRegRegOpConstructor.subst(vsqrtSIop);
596 exec_output += PredOpExecute.subst(vsqrtSIop);
597
598 vsqrtDCode = '''
599 IntDoubleUnion cOp1, cDest;
600 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
601 vfpFlushToZero(Fpscr, cOp1.fp);
592 VfpSavedState state = prepVfpFpscr(Fpscr);
593 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cDest.fp));
594 cDest.fp = sqrt(cOp1.fp);
595 __asm__ __volatile__("" :: "m" (cDest.fp));
596 Fpscr = setVfpFpscr(Fpscr, state);
597 if (cOp1.fp < 0) {
598 cDest.fp = NAN;
599 }

--- 10 unchanged lines hidden (view full) ---

610
611let {{
612
613 header_output = ""
614 decoder_output = ""
615 exec_output = ""
616
617 vmlaSCode = '''
602 VfpSavedState state = prepVfpFpscr(Fpscr);
603 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cDest.fp));
604 cDest.fp = sqrt(cOp1.fp);
605 __asm__ __volatile__("" :: "m" (cDest.fp));
606 Fpscr = setVfpFpscr(Fpscr, state);
607 if (cOp1.fp < 0) {
608 cDest.fp = NAN;
609 }

--- 10 unchanged lines hidden (view full) ---

620
621let {{
622
623 header_output = ""
624 decoder_output = ""
625 exec_output = ""
626
627 vmlaSCode = '''
628 vfpFlushToZero(Fpscr, FpOp1, FpOp2);
618 VfpSavedState state = prepVfpFpscr(Fpscr);
619 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
620 float mid = FpOp1 * FpOp2;
621 if ((isinf(FpOp1) && FpOp2 == 0) || (isinf(FpOp2) && FpOp1 == 0)) {
622 mid = NAN;
623 }
629 VfpSavedState state = prepVfpFpscr(Fpscr);
630 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
631 float mid = FpOp1 * FpOp2;
632 if ((isinf(FpOp1) && FpOp2 == 0) || (isinf(FpOp2) && FpOp1 == 0)) {
633 mid = NAN;
634 }
635 vfpFlushToZero(Fpscr, FpDest, mid);
624 FpDest = FpDest + mid;
625 __asm__ __volatile__("" :: "m" (FpDest));
626 Fpscr = setVfpFpscr(Fpscr, state);
627 '''
628 vmlaSIop = InstObjParams("vmlas", "VmlaS", "VfpRegRegRegOp",
629 { "code": vmlaSCode,
630 "predicate_test": predicateTest }, [])
631 header_output += VfpRegRegRegOpDeclare.subst(vmlaSIop);
632 decoder_output += VfpRegRegRegOpConstructor.subst(vmlaSIop);
633 exec_output += PredOpExecute.subst(vmlaSIop);
634
635 vmlaDCode = '''
636 IntDoubleUnion cOp1, cOp2, cDest;
637 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
638 cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32));
639 cDest.bits = ((uint64_t)FpDestP0.uw | ((uint64_t)FpDestP1.uw << 32));
636 FpDest = FpDest + mid;
637 __asm__ __volatile__("" :: "m" (FpDest));
638 Fpscr = setVfpFpscr(Fpscr, state);
639 '''
640 vmlaSIop = InstObjParams("vmlas", "VmlaS", "VfpRegRegRegOp",
641 { "code": vmlaSCode,
642 "predicate_test": predicateTest }, [])
643 header_output += VfpRegRegRegOpDeclare.subst(vmlaSIop);
644 decoder_output += VfpRegRegRegOpConstructor.subst(vmlaSIop);
645 exec_output += PredOpExecute.subst(vmlaSIop);
646
647 vmlaDCode = '''
648 IntDoubleUnion cOp1, cOp2, cDest;
649 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
650 cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32));
651 cDest.bits = ((uint64_t)FpDestP0.uw | ((uint64_t)FpDestP1.uw << 32));
652 vfpFlushToZero(Fpscr, cOp1.fp, cOp2.fp);
640 VfpSavedState state = prepVfpFpscr(Fpscr);
641 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp));
642 double mid = cOp1.fp * cOp2.fp;
643 if ((isinf(cOp1.fp) && cOp2.fp == 0) ||
644 (isinf(cOp2.fp) && cOp1.fp == 0)) {
645 mid = NAN;
646 }
653 VfpSavedState state = prepVfpFpscr(Fpscr);
654 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp));
655 double mid = cOp1.fp * cOp2.fp;
656 if ((isinf(cOp1.fp) && cOp2.fp == 0) ||
657 (isinf(cOp2.fp) && cOp1.fp == 0)) {
658 mid = NAN;
659 }
660 vfpFlushToZero(Fpscr, cDest.fp, mid);
647 cDest.fp = cDest.fp + mid;
648 __asm__ __volatile__("" :: "m" (cDest.fp));
649 Fpscr = setVfpFpscr(Fpscr, state);
650 FpDestP0.uw = cDest.bits;
651 FpDestP1.uw = cDest.bits >> 32;
652 '''
653 vmlaDIop = InstObjParams("vmlad", "VmlaD", "VfpRegRegRegOp",
654 { "code": vmlaDCode,
655 "predicate_test": predicateTest }, [])
656 header_output += VfpRegRegRegOpDeclare.subst(vmlaDIop);
657 decoder_output += VfpRegRegRegOpConstructor.subst(vmlaDIop);
658 exec_output += PredOpExecute.subst(vmlaDIop);
659
660 vmlsSCode = '''
661 cDest.fp = cDest.fp + mid;
662 __asm__ __volatile__("" :: "m" (cDest.fp));
663 Fpscr = setVfpFpscr(Fpscr, state);
664 FpDestP0.uw = cDest.bits;
665 FpDestP1.uw = cDest.bits >> 32;
666 '''
667 vmlaDIop = InstObjParams("vmlad", "VmlaD", "VfpRegRegRegOp",
668 { "code": vmlaDCode,
669 "predicate_test": predicateTest }, [])
670 header_output += VfpRegRegRegOpDeclare.subst(vmlaDIop);
671 decoder_output += VfpRegRegRegOpConstructor.subst(vmlaDIop);
672 exec_output += PredOpExecute.subst(vmlaDIop);
673
674 vmlsSCode = '''
675 vfpFlushToZero(Fpscr, FpOp1, FpOp2);
661 VfpSavedState state = prepVfpFpscr(Fpscr);
662 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
663 float mid = FpOp1 * FpOp2;
664 if ((isinf(FpOp1) && FpOp2 == 0) || (isinf(FpOp2) && FpOp1 == 0)) {
665 mid = NAN;
666 }
676 VfpSavedState state = prepVfpFpscr(Fpscr);
677 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
678 float mid = FpOp1 * FpOp2;
679 if ((isinf(FpOp1) && FpOp2 == 0) || (isinf(FpOp2) && FpOp1 == 0)) {
680 mid = NAN;
681 }
682 vfpFlushToZero(Fpscr, FpDest, mid);
667 FpDest = FpDest - mid;
668 __asm__ __volatile__("" :: "m" (FpDest));
669 Fpscr = setVfpFpscr(Fpscr, state);
670 '''
671 vmlsSIop = InstObjParams("vmlss", "VmlsS", "VfpRegRegRegOp",
672 { "code": vmlsSCode,
673 "predicate_test": predicateTest }, [])
674 header_output += VfpRegRegRegOpDeclare.subst(vmlsSIop);
675 decoder_output += VfpRegRegRegOpConstructor.subst(vmlsSIop);
676 exec_output += PredOpExecute.subst(vmlsSIop);
677
678 vmlsDCode = '''
679 IntDoubleUnion cOp1, cOp2, cDest;
680 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
681 cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32));
682 cDest.bits = ((uint64_t)FpDestP0.uw | ((uint64_t)FpDestP1.uw << 32));
683 FpDest = FpDest - mid;
684 __asm__ __volatile__("" :: "m" (FpDest));
685 Fpscr = setVfpFpscr(Fpscr, state);
686 '''
687 vmlsSIop = InstObjParams("vmlss", "VmlsS", "VfpRegRegRegOp",
688 { "code": vmlsSCode,
689 "predicate_test": predicateTest }, [])
690 header_output += VfpRegRegRegOpDeclare.subst(vmlsSIop);
691 decoder_output += VfpRegRegRegOpConstructor.subst(vmlsSIop);
692 exec_output += PredOpExecute.subst(vmlsSIop);
693
694 vmlsDCode = '''
695 IntDoubleUnion cOp1, cOp2, cDest;
696 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
697 cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32));
698 cDest.bits = ((uint64_t)FpDestP0.uw | ((uint64_t)FpDestP1.uw << 32));
699 vfpFlushToZero(Fpscr, cOp1.fp, cOp2.fp);
683 VfpSavedState state = prepVfpFpscr(Fpscr);
684 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp));
685 double mid = cOp1.fp * cOp2.fp;
686 if ((isinf(cOp1.fp) && cOp2.fp == 0) ||
687 (isinf(cOp2.fp) && cOp1.fp == 0)) {
688 mid = NAN;
689 }
690 cDest.fp = cDest.fp - mid;
700 VfpSavedState state = prepVfpFpscr(Fpscr);
701 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp));
702 double mid = cOp1.fp * cOp2.fp;
703 if ((isinf(cOp1.fp) && cOp2.fp == 0) ||
704 (isinf(cOp2.fp) && cOp1.fp == 0)) {
705 mid = NAN;
706 }
707 cDest.fp = cDest.fp - mid;
708 vfpFlushToZero(Fpscr, cDest.fp, mid);
691 __asm__ __volatile__("" :: "m" (cDest.fp));
692 Fpscr = setVfpFpscr(Fpscr, state);
693 FpDestP0.uw = cDest.bits;
694 FpDestP1.uw = cDest.bits >> 32;
695 '''
696 vmlsDIop = InstObjParams("vmlsd", "VmlsD", "VfpRegRegRegOp",
697 { "code": vmlsDCode,
698 "predicate_test": predicateTest }, [])
699 header_output += VfpRegRegRegOpDeclare.subst(vmlsDIop);
700 decoder_output += VfpRegRegRegOpConstructor.subst(vmlsDIop);
701 exec_output += PredOpExecute.subst(vmlsDIop);
702
703 vnmlaSCode = '''
709 __asm__ __volatile__("" :: "m" (cDest.fp));
710 Fpscr = setVfpFpscr(Fpscr, state);
711 FpDestP0.uw = cDest.bits;
712 FpDestP1.uw = cDest.bits >> 32;
713 '''
714 vmlsDIop = InstObjParams("vmlsd", "VmlsD", "VfpRegRegRegOp",
715 { "code": vmlsDCode,
716 "predicate_test": predicateTest }, [])
717 header_output += VfpRegRegRegOpDeclare.subst(vmlsDIop);
718 decoder_output += VfpRegRegRegOpConstructor.subst(vmlsDIop);
719 exec_output += PredOpExecute.subst(vmlsDIop);
720
721 vnmlaSCode = '''
722 vfpFlushToZero(Fpscr, FpOp1, FpOp2);
704 VfpSavedState state = prepVfpFpscr(Fpscr);
705 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
706 float mid = FpOp1 * FpOp2;
707 if ((isinf(FpOp1) && FpOp2 == 0) || (isinf(FpOp2) && FpOp1 == 0)) {
708 mid = NAN;
709 }
723 VfpSavedState state = prepVfpFpscr(Fpscr);
724 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
725 float mid = FpOp1 * FpOp2;
726 if ((isinf(FpOp1) && FpOp2 == 0) || (isinf(FpOp2) && FpOp1 == 0)) {
727 mid = NAN;
728 }
729 vfpFlushToZero(Fpscr, FpDest, mid);
710 FpDest = -FpDest - mid;
711 __asm__ __volatile__("" :: "m" (FpDest));
712 Fpscr = setVfpFpscr(Fpscr, state);
713 '''
714 vnmlaSIop = InstObjParams("vnmlas", "VnmlaS", "VfpRegRegRegOp",
715 { "code": vnmlaSCode,
716 "predicate_test": predicateTest }, [])
717 header_output += VfpRegRegRegOpDeclare.subst(vnmlaSIop);
718 decoder_output += VfpRegRegRegOpConstructor.subst(vnmlaSIop);
719 exec_output += PredOpExecute.subst(vnmlaSIop);
720
721 vnmlaDCode = '''
722 IntDoubleUnion cOp1, cOp2, cDest;
723 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
724 cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32));
725 cDest.bits = ((uint64_t)FpDestP0.uw | ((uint64_t)FpDestP1.uw << 32));
730 FpDest = -FpDest - mid;
731 __asm__ __volatile__("" :: "m" (FpDest));
732 Fpscr = setVfpFpscr(Fpscr, state);
733 '''
734 vnmlaSIop = InstObjParams("vnmlas", "VnmlaS", "VfpRegRegRegOp",
735 { "code": vnmlaSCode,
736 "predicate_test": predicateTest }, [])
737 header_output += VfpRegRegRegOpDeclare.subst(vnmlaSIop);
738 decoder_output += VfpRegRegRegOpConstructor.subst(vnmlaSIop);
739 exec_output += PredOpExecute.subst(vnmlaSIop);
740
741 vnmlaDCode = '''
742 IntDoubleUnion cOp1, cOp2, cDest;
743 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
744 cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32));
745 cDest.bits = ((uint64_t)FpDestP0.uw | ((uint64_t)FpDestP1.uw << 32));
746 vfpFlushToZero(Fpscr, cOp1.fp, cOp2.fp);
726 VfpSavedState state = prepVfpFpscr(Fpscr);
727 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp));
728 double mid = cOp1.fp * cOp2.fp;
729 if ((isinf(cOp1.fp) && cOp2.fp == 0) ||
730 (isinf(cOp2.fp) && cOp1.fp == 0)) {
731 mid = NAN;
732 }
747 VfpSavedState state = prepVfpFpscr(Fpscr);
748 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp));
749 double mid = cOp1.fp * cOp2.fp;
750 if ((isinf(cOp1.fp) && cOp2.fp == 0) ||
751 (isinf(cOp2.fp) && cOp1.fp == 0)) {
752 mid = NAN;
753 }
754 vfpFlushToZero(Fpscr, cDest.fp, mid);
733 cDest.fp = -cDest.fp - mid;
734 __asm__ __volatile__("" :: "m" (cDest.fp));
735 Fpscr = setVfpFpscr(Fpscr, state);
736 FpDestP0.uw = cDest.bits;
737 FpDestP1.uw = cDest.bits >> 32;
738 '''
739 vnmlaDIop = InstObjParams("vnmlad", "VnmlaD", "VfpRegRegRegOp",
740 { "code": vnmlaDCode,
741 "predicate_test": predicateTest }, [])
742 header_output += VfpRegRegRegOpDeclare.subst(vnmlaDIop);
743 decoder_output += VfpRegRegRegOpConstructor.subst(vnmlaDIop);
744 exec_output += PredOpExecute.subst(vnmlaDIop);
745
746 vnmlsSCode = '''
755 cDest.fp = -cDest.fp - mid;
756 __asm__ __volatile__("" :: "m" (cDest.fp));
757 Fpscr = setVfpFpscr(Fpscr, state);
758 FpDestP0.uw = cDest.bits;
759 FpDestP1.uw = cDest.bits >> 32;
760 '''
761 vnmlaDIop = InstObjParams("vnmlad", "VnmlaD", "VfpRegRegRegOp",
762 { "code": vnmlaDCode,
763 "predicate_test": predicateTest }, [])
764 header_output += VfpRegRegRegOpDeclare.subst(vnmlaDIop);
765 decoder_output += VfpRegRegRegOpConstructor.subst(vnmlaDIop);
766 exec_output += PredOpExecute.subst(vnmlaDIop);
767
768 vnmlsSCode = '''
769 vfpFlushToZero(Fpscr, FpOp1, FpOp2);
747 VfpSavedState state = prepVfpFpscr(Fpscr);
748 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
749 float mid = FpOp1 * FpOp2;
750 if ((isinf(FpOp1) && FpOp2 == 0) || (isinf(FpOp2) && FpOp1 == 0)) {
751 mid = NAN;
752 }
770 VfpSavedState state = prepVfpFpscr(Fpscr);
771 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
772 float mid = FpOp1 * FpOp2;
773 if ((isinf(FpOp1) && FpOp2 == 0) || (isinf(FpOp2) && FpOp1 == 0)) {
774 mid = NAN;
775 }
776 vfpFlushToZero(Fpscr, FpDest, mid);
753 FpDest = -FpDest + mid;
754 __asm__ __volatile__("" :: "m" (FpDest));
755 Fpscr = setVfpFpscr(Fpscr, state);
756 '''
757 vnmlsSIop = InstObjParams("vnmlss", "VnmlsS", "VfpRegRegRegOp",
758 { "code": vnmlsSCode,
759 "predicate_test": predicateTest }, [])
760 header_output += VfpRegRegRegOpDeclare.subst(vnmlsSIop);
761 decoder_output += VfpRegRegRegOpConstructor.subst(vnmlsSIop);
762 exec_output += PredOpExecute.subst(vnmlsSIop);
763
764 vnmlsDCode = '''
765 IntDoubleUnion cOp1, cOp2, cDest;
766 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
767 cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32));
768 cDest.bits = ((uint64_t)FpDestP0.uw | ((uint64_t)FpDestP1.uw << 32));
777 FpDest = -FpDest + mid;
778 __asm__ __volatile__("" :: "m" (FpDest));
779 Fpscr = setVfpFpscr(Fpscr, state);
780 '''
781 vnmlsSIop = InstObjParams("vnmlss", "VnmlsS", "VfpRegRegRegOp",
782 { "code": vnmlsSCode,
783 "predicate_test": predicateTest }, [])
784 header_output += VfpRegRegRegOpDeclare.subst(vnmlsSIop);
785 decoder_output += VfpRegRegRegOpConstructor.subst(vnmlsSIop);
786 exec_output += PredOpExecute.subst(vnmlsSIop);
787
788 vnmlsDCode = '''
789 IntDoubleUnion cOp1, cOp2, cDest;
790 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
791 cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32));
792 cDest.bits = ((uint64_t)FpDestP0.uw | ((uint64_t)FpDestP1.uw << 32));
793 vfpFlushToZero(Fpscr, cOp1.fp, cOp2.fp);
769 VfpSavedState state = prepVfpFpscr(Fpscr);
770 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp));
771 double mid = cOp1.fp * cOp2.fp;
772 if ((isinf(cOp1.fp) && cOp2.fp == 0) ||
773 (isinf(cOp2.fp) && cOp1.fp == 0)) {
774 mid = NAN;
775 }
794 VfpSavedState state = prepVfpFpscr(Fpscr);
795 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp));
796 double mid = cOp1.fp * cOp2.fp;
797 if ((isinf(cOp1.fp) && cOp2.fp == 0) ||
798 (isinf(cOp2.fp) && cOp1.fp == 0)) {
799 mid = NAN;
800 }
801 vfpFlushToZero(Fpscr, cDest.fp, mid);
776 cDest.fp = -cDest.fp + mid;
777 __asm__ __volatile__("" :: "m" (cDest.fp));
778 Fpscr = setVfpFpscr(Fpscr, state);
779 FpDestP0.uw = cDest.bits;
780 FpDestP1.uw = cDest.bits >> 32;
781 '''
782 vnmlsDIop = InstObjParams("vnmlsd", "VnmlsD", "VfpRegRegRegOp",
783 { "code": vnmlsDCode,
784 "predicate_test": predicateTest }, [])
785 header_output += VfpRegRegRegOpDeclare.subst(vnmlsDIop);
786 decoder_output += VfpRegRegRegOpConstructor.subst(vnmlsDIop);
787 exec_output += PredOpExecute.subst(vnmlsDIop);
788
789 vnmulSCode = '''
802 cDest.fp = -cDest.fp + mid;
803 __asm__ __volatile__("" :: "m" (cDest.fp));
804 Fpscr = setVfpFpscr(Fpscr, state);
805 FpDestP0.uw = cDest.bits;
806 FpDestP1.uw = cDest.bits >> 32;
807 '''
808 vnmlsDIop = InstObjParams("vnmlsd", "VnmlsD", "VfpRegRegRegOp",
809 { "code": vnmlsDCode,
810 "predicate_test": predicateTest }, [])
811 header_output += VfpRegRegRegOpDeclare.subst(vnmlsDIop);
812 decoder_output += VfpRegRegRegOpConstructor.subst(vnmlsDIop);
813 exec_output += PredOpExecute.subst(vnmlsDIop);
814
815 vnmulSCode = '''
816 vfpFlushToZero(Fpscr, FpOp1, FpOp2);
790 VfpSavedState state = prepVfpFpscr(Fpscr);
791 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
792 float mid = FpOp1 * FpOp2;
793 if ((isinf(FpOp1) && FpOp2 == 0) || (isinf(FpOp2) && FpOp1 == 0)) {
794 mid = NAN;
795 }
796 FpDest = -mid;
797 __asm__ __volatile__("" :: "m" (FpDest));

--- 6 unchanged lines hidden (view full) ---

804 decoder_output += VfpRegRegRegOpConstructor.subst(vnmulSIop);
805 exec_output += PredOpExecute.subst(vnmulSIop);
806
807 vnmulDCode = '''
808 IntDoubleUnion cOp1, cOp2, cDest;
809 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
810 cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32));
811 cDest.bits = ((uint64_t)FpDestP0.uw | ((uint64_t)FpDestP1.uw << 32));
817 VfpSavedState state = prepVfpFpscr(Fpscr);
818 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
819 float mid = FpOp1 * FpOp2;
820 if ((isinf(FpOp1) && FpOp2 == 0) || (isinf(FpOp2) && FpOp1 == 0)) {
821 mid = NAN;
822 }
823 FpDest = -mid;
824 __asm__ __volatile__("" :: "m" (FpDest));

--- 6 unchanged lines hidden (view full) ---

831 decoder_output += VfpRegRegRegOpConstructor.subst(vnmulSIop);
832 exec_output += PredOpExecute.subst(vnmulSIop);
833
834 vnmulDCode = '''
835 IntDoubleUnion cOp1, cOp2, cDest;
836 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
837 cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32));
838 cDest.bits = ((uint64_t)FpDestP0.uw | ((uint64_t)FpDestP1.uw << 32));
839 vfpFlushToZero(Fpscr, cOp1.fp, cOp2.fp);
812 VfpSavedState state = prepVfpFpscr(Fpscr);
813 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp));
814 double mid = cOp1.fp * cOp2.fp;
815 if ((isinf(cOp1.fp) && cOp2.fp == 0) ||
816 (isinf(cOp2.fp) && cOp1.fp == 0)) {
817 mid = NAN;
818 }
819 cDest.fp = -mid;

--- 74 unchanged lines hidden (view full) ---

894 vcvtSIntFpDIop = InstObjParams("vcvt", "VcvtSIntFpD", "VfpRegRegOp",
895 { "code": vcvtSIntFpDCode,
896 "predicate_test": predicateTest }, [])
897 header_output += VfpRegRegOpDeclare.subst(vcvtSIntFpDIop);
898 decoder_output += VfpRegRegOpConstructor.subst(vcvtSIntFpDIop);
899 exec_output += PredOpExecute.subst(vcvtSIntFpDIop);
900
901 vcvtFpUIntSRCode = '''
840 VfpSavedState state = prepVfpFpscr(Fpscr);
841 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp));
842 double mid = cOp1.fp * cOp2.fp;
843 if ((isinf(cOp1.fp) && cOp2.fp == 0) ||
844 (isinf(cOp2.fp) && cOp1.fp == 0)) {
845 mid = NAN;
846 }
847 cDest.fp = -mid;

--- 74 unchanged lines hidden (view full) ---

922 vcvtSIntFpDIop = InstObjParams("vcvt", "VcvtSIntFpD", "VfpRegRegOp",
923 { "code": vcvtSIntFpDCode,
924 "predicate_test": predicateTest }, [])
925 header_output += VfpRegRegOpDeclare.subst(vcvtSIntFpDIop);
926 decoder_output += VfpRegRegOpConstructor.subst(vcvtSIntFpDIop);
927 exec_output += PredOpExecute.subst(vcvtSIntFpDIop);
928
929 vcvtFpUIntSRCode = '''
930 vfpFlushToZero(Fpscr, FpOp1);
902 VfpSavedState state = prepVfpFpscr(Fpscr);
903 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
904 FpDest.uw = FpOp1;
905 __asm__ __volatile__("" :: "m" (FpDest.uw));
906 Fpscr = setVfpFpscr(Fpscr, state);
907 '''
908 vcvtFpUIntSRIop = InstObjParams("vcvt", "VcvtFpUIntSR", "VfpRegRegOp",
909 { "code": vcvtFpUIntSRCode,
910 "predicate_test": predicateTest }, [])
911 header_output += VfpRegRegOpDeclare.subst(vcvtFpUIntSRIop);
912 decoder_output += VfpRegRegOpConstructor.subst(vcvtFpUIntSRIop);
913 exec_output += PredOpExecute.subst(vcvtFpUIntSRIop);
914
915 vcvtFpUIntDRCode = '''
916 IntDoubleUnion cOp1;
917 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
931 VfpSavedState state = prepVfpFpscr(Fpscr);
932 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
933 FpDest.uw = FpOp1;
934 __asm__ __volatile__("" :: "m" (FpDest.uw));
935 Fpscr = setVfpFpscr(Fpscr, state);
936 '''
937 vcvtFpUIntSRIop = InstObjParams("vcvt", "VcvtFpUIntSR", "VfpRegRegOp",
938 { "code": vcvtFpUIntSRCode,
939 "predicate_test": predicateTest }, [])
940 header_output += VfpRegRegOpDeclare.subst(vcvtFpUIntSRIop);
941 decoder_output += VfpRegRegOpConstructor.subst(vcvtFpUIntSRIop);
942 exec_output += PredOpExecute.subst(vcvtFpUIntSRIop);
943
944 vcvtFpUIntDRCode = '''
945 IntDoubleUnion cOp1;
946 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
947 vfpFlushToZero(Fpscr, cOp1.fp);
918 VfpSavedState state = prepVfpFpscr(Fpscr);
919 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp));
920 uint64_t result = cOp1.fp;
921 __asm__ __volatile__("" :: "m" (result));
922 Fpscr = setVfpFpscr(Fpscr, state);
923 FpDestP0.uw = result;
924 '''
925 vcvtFpUIntDRIop = InstObjParams("vcvtr", "VcvtFpUIntDR", "VfpRegRegOp",
926 { "code": vcvtFpUIntDRCode,
927 "predicate_test": predicateTest }, [])
928 header_output += VfpRegRegOpDeclare.subst(vcvtFpUIntDRIop);
929 decoder_output += VfpRegRegOpConstructor.subst(vcvtFpUIntDRIop);
930 exec_output += PredOpExecute.subst(vcvtFpUIntDRIop);
931
932 vcvtFpSIntSRCode = '''
948 VfpSavedState state = prepVfpFpscr(Fpscr);
949 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp));
950 uint64_t result = cOp1.fp;
951 __asm__ __volatile__("" :: "m" (result));
952 Fpscr = setVfpFpscr(Fpscr, state);
953 FpDestP0.uw = result;
954 '''
955 vcvtFpUIntDRIop = InstObjParams("vcvtr", "VcvtFpUIntDR", "VfpRegRegOp",
956 { "code": vcvtFpUIntDRCode,
957 "predicate_test": predicateTest }, [])
958 header_output += VfpRegRegOpDeclare.subst(vcvtFpUIntDRIop);
959 decoder_output += VfpRegRegOpConstructor.subst(vcvtFpUIntDRIop);
960 exec_output += PredOpExecute.subst(vcvtFpUIntDRIop);
961
962 vcvtFpSIntSRCode = '''
963 vfpFlushToZero(Fpscr, FpOp1);
933 VfpSavedState state = prepVfpFpscr(Fpscr);
934 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
935 FpDest.sw = FpOp1;
936 __asm__ __volatile__("" :: "m" (FpDest.sw));
937 Fpscr = setVfpFpscr(Fpscr, state);
938 '''
939 vcvtFpSIntSRIop = InstObjParams("vcvtr", "VcvtFpSIntSR", "VfpRegRegOp",
940 { "code": vcvtFpSIntSRCode,
941 "predicate_test": predicateTest }, [])
942 header_output += VfpRegRegOpDeclare.subst(vcvtFpSIntSRIop);
943 decoder_output += VfpRegRegOpConstructor.subst(vcvtFpSIntSRIop);
944 exec_output += PredOpExecute.subst(vcvtFpSIntSRIop);
945
946 vcvtFpSIntDRCode = '''
947 IntDoubleUnion cOp1;
948 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
964 VfpSavedState state = prepVfpFpscr(Fpscr);
965 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
966 FpDest.sw = FpOp1;
967 __asm__ __volatile__("" :: "m" (FpDest.sw));
968 Fpscr = setVfpFpscr(Fpscr, state);
969 '''
970 vcvtFpSIntSRIop = InstObjParams("vcvtr", "VcvtFpSIntSR", "VfpRegRegOp",
971 { "code": vcvtFpSIntSRCode,
972 "predicate_test": predicateTest }, [])
973 header_output += VfpRegRegOpDeclare.subst(vcvtFpSIntSRIop);
974 decoder_output += VfpRegRegOpConstructor.subst(vcvtFpSIntSRIop);
975 exec_output += PredOpExecute.subst(vcvtFpSIntSRIop);
976
977 vcvtFpSIntDRCode = '''
978 IntDoubleUnion cOp1;
979 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
980 vfpFlushToZero(Fpscr, cOp1.fp);
949 VfpSavedState state = prepVfpFpscr(Fpscr);
950 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp));
951 int64_t result = cOp1.fp;
952 __asm__ __volatile__("" :: "m" (result));
953 Fpscr = setVfpFpscr(Fpscr, state);
954 FpDestP0.uw = result;
955 '''
956 vcvtFpSIntDRIop = InstObjParams("vcvtr", "VcvtFpSIntDR", "VfpRegRegOp",
957 { "code": vcvtFpSIntDRCode,
958 "predicate_test": predicateTest }, [])
959 header_output += VfpRegRegOpDeclare.subst(vcvtFpSIntDRIop);
960 decoder_output += VfpRegRegOpConstructor.subst(vcvtFpSIntDRIop);
961 exec_output += PredOpExecute.subst(vcvtFpSIntDRIop);
962
963 vcvtFpUIntSCode = '''
981 VfpSavedState state = prepVfpFpscr(Fpscr);
982 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp));
983 int64_t result = cOp1.fp;
984 __asm__ __volatile__("" :: "m" (result));
985 Fpscr = setVfpFpscr(Fpscr, state);
986 FpDestP0.uw = result;
987 '''
988 vcvtFpSIntDRIop = InstObjParams("vcvtr", "VcvtFpSIntDR", "VfpRegRegOp",
989 { "code": vcvtFpSIntDRCode,
990 "predicate_test": predicateTest }, [])
991 header_output += VfpRegRegOpDeclare.subst(vcvtFpSIntDRIop);
992 decoder_output += VfpRegRegOpConstructor.subst(vcvtFpSIntDRIop);
993 exec_output += PredOpExecute.subst(vcvtFpSIntDRIop);
994
995 vcvtFpUIntSCode = '''
996 vfpFlushToZero(Fpscr, FpOp1);
964 VfpSavedState state = prepVfpFpscr(Fpscr);
965 fesetround(FeRoundZero);
966 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
967 FpDest.uw = FpOp1;
968 __asm__ __volatile__("" :: "m" (FpDest.uw));
969 Fpscr = setVfpFpscr(Fpscr, state);
970 '''
971 vcvtFpUIntSIop = InstObjParams("vcvt", "VcvtFpUIntS", "VfpRegRegOp",
972 { "code": vcvtFpUIntSCode,
973 "predicate_test": predicateTest }, [])
974 header_output += VfpRegRegOpDeclare.subst(vcvtFpUIntSIop);
975 decoder_output += VfpRegRegOpConstructor.subst(vcvtFpUIntSIop);
976 exec_output += PredOpExecute.subst(vcvtFpUIntSIop);
977
978 vcvtFpUIntDCode = '''
979 IntDoubleUnion cOp1;
980 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
997 VfpSavedState state = prepVfpFpscr(Fpscr);
998 fesetround(FeRoundZero);
999 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
1000 FpDest.uw = FpOp1;
1001 __asm__ __volatile__("" :: "m" (FpDest.uw));
1002 Fpscr = setVfpFpscr(Fpscr, state);
1003 '''
1004 vcvtFpUIntSIop = InstObjParams("vcvt", "VcvtFpUIntS", "VfpRegRegOp",
1005 { "code": vcvtFpUIntSCode,
1006 "predicate_test": predicateTest }, [])
1007 header_output += VfpRegRegOpDeclare.subst(vcvtFpUIntSIop);
1008 decoder_output += VfpRegRegOpConstructor.subst(vcvtFpUIntSIop);
1009 exec_output += PredOpExecute.subst(vcvtFpUIntSIop);
1010
1011 vcvtFpUIntDCode = '''
1012 IntDoubleUnion cOp1;
1013 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
1014 vfpFlushToZero(Fpscr, cOp1.fp);
981 VfpSavedState state = prepVfpFpscr(Fpscr);
982 fesetround(FeRoundZero);
983 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp));
984 uint64_t result = cOp1.fp;
985 __asm__ __volatile__("" :: "m" (result));
986 Fpscr = setVfpFpscr(Fpscr, state);
987 FpDestP0.uw = result;
988 '''
989 vcvtFpUIntDIop = InstObjParams("vcvt", "VcvtFpUIntD", "VfpRegRegOp",
990 { "code": vcvtFpUIntDCode,
991 "predicate_test": predicateTest }, [])
992 header_output += VfpRegRegOpDeclare.subst(vcvtFpUIntDIop);
993 decoder_output += VfpRegRegOpConstructor.subst(vcvtFpUIntDIop);
994 exec_output += PredOpExecute.subst(vcvtFpUIntDIop);
995
996 vcvtFpSIntSCode = '''
1015 VfpSavedState state = prepVfpFpscr(Fpscr);
1016 fesetround(FeRoundZero);
1017 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp));
1018 uint64_t result = cOp1.fp;
1019 __asm__ __volatile__("" :: "m" (result));
1020 Fpscr = setVfpFpscr(Fpscr, state);
1021 FpDestP0.uw = result;
1022 '''
1023 vcvtFpUIntDIop = InstObjParams("vcvt", "VcvtFpUIntD", "VfpRegRegOp",
1024 { "code": vcvtFpUIntDCode,
1025 "predicate_test": predicateTest }, [])
1026 header_output += VfpRegRegOpDeclare.subst(vcvtFpUIntDIop);
1027 decoder_output += VfpRegRegOpConstructor.subst(vcvtFpUIntDIop);
1028 exec_output += PredOpExecute.subst(vcvtFpUIntDIop);
1029
1030 vcvtFpSIntSCode = '''
1031 vfpFlushToZero(Fpscr, FpOp1);
997 VfpSavedState state = prepVfpFpscr(Fpscr);
998 fesetround(FeRoundZero);
999 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
1000 FpDest.sw = FpOp1;
1001 __asm__ __volatile__("" :: "m" (FpDest.sw));
1002 Fpscr = setVfpFpscr(Fpscr, state);
1003 '''
1004 vcvtFpSIntSIop = InstObjParams("vcvt", "VcvtFpSIntS", "VfpRegRegOp",
1005 { "code": vcvtFpSIntSCode,
1006 "predicate_test": predicateTest }, [])
1007 header_output += VfpRegRegOpDeclare.subst(vcvtFpSIntSIop);
1008 decoder_output += VfpRegRegOpConstructor.subst(vcvtFpSIntSIop);
1009 exec_output += PredOpExecute.subst(vcvtFpSIntSIop);
1010
1011 vcvtFpSIntDCode = '''
1012 IntDoubleUnion cOp1;
1013 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
1032 VfpSavedState state = prepVfpFpscr(Fpscr);
1033 fesetround(FeRoundZero);
1034 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
1035 FpDest.sw = FpOp1;
1036 __asm__ __volatile__("" :: "m" (FpDest.sw));
1037 Fpscr = setVfpFpscr(Fpscr, state);
1038 '''
1039 vcvtFpSIntSIop = InstObjParams("vcvt", "VcvtFpSIntS", "VfpRegRegOp",
1040 { "code": vcvtFpSIntSCode,
1041 "predicate_test": predicateTest }, [])
1042 header_output += VfpRegRegOpDeclare.subst(vcvtFpSIntSIop);
1043 decoder_output += VfpRegRegOpConstructor.subst(vcvtFpSIntSIop);
1044 exec_output += PredOpExecute.subst(vcvtFpSIntSIop);
1045
1046 vcvtFpSIntDCode = '''
1047 IntDoubleUnion cOp1;
1048 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
1049 vfpFlushToZero(Fpscr, cOp1.fp);
1014 VfpSavedState state = prepVfpFpscr(Fpscr);
1015 fesetround(FeRoundZero);
1016 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp));
1017 int64_t result = cOp1.fp;
1018 __asm__ __volatile__("" :: "m" (result));
1019 Fpscr = setVfpFpscr(Fpscr, state);
1020 FpDestP0.uw = result;
1021 '''
1022 vcvtFpSIntDIop = InstObjParams("vcvt", "VcvtFpSIntD", "VfpRegRegOp",
1023 { "code": vcvtFpSIntDCode,
1024 "predicate_test": predicateTest }, [])
1025 header_output += VfpRegRegOpDeclare.subst(vcvtFpSIntDIop);
1026 decoder_output += VfpRegRegOpConstructor.subst(vcvtFpSIntDIop);
1027 exec_output += PredOpExecute.subst(vcvtFpSIntDIop);
1028
1029 vcvtFpSFpDCode = '''
1030 IntDoubleUnion cDest;
1050 VfpSavedState state = prepVfpFpscr(Fpscr);
1051 fesetround(FeRoundZero);
1052 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp));
1053 int64_t result = cOp1.fp;
1054 __asm__ __volatile__("" :: "m" (result));
1055 Fpscr = setVfpFpscr(Fpscr, state);
1056 FpDestP0.uw = result;
1057 '''
1058 vcvtFpSIntDIop = InstObjParams("vcvt", "VcvtFpSIntD", "VfpRegRegOp",
1059 { "code": vcvtFpSIntDCode,
1060 "predicate_test": predicateTest }, [])
1061 header_output += VfpRegRegOpDeclare.subst(vcvtFpSIntDIop);
1062 decoder_output += VfpRegRegOpConstructor.subst(vcvtFpSIntDIop);
1063 exec_output += PredOpExecute.subst(vcvtFpSIntDIop);
1064
1065 vcvtFpSFpDCode = '''
1066 IntDoubleUnion cDest;
1067 vfpFlushToZero(Fpscr, FpOp1);
1031 VfpSavedState state = prepVfpFpscr(Fpscr);
1032 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
1033 cDest.fp = FpOp1;
1034 __asm__ __volatile__("" :: "m" (cDest.fp));
1035 Fpscr = setVfpFpscr(Fpscr, state);
1036 FpDestP0.uw = cDest.bits;
1037 FpDestP1.uw = cDest.bits >> 32;
1038 '''
1039 vcvtFpSFpDIop = InstObjParams("vcvt", "VcvtFpSFpD", "VfpRegRegOp",
1040 { "code": vcvtFpSFpDCode,
1041 "predicate_test": predicateTest }, [])
1042 header_output += VfpRegRegOpDeclare.subst(vcvtFpSFpDIop);
1043 decoder_output += VfpRegRegOpConstructor.subst(vcvtFpSFpDIop);
1044 exec_output += PredOpExecute.subst(vcvtFpSFpDIop);
1045
1046 vcvtFpDFpSCode = '''
1047 IntDoubleUnion cOp1;
1048 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
1068 VfpSavedState state = prepVfpFpscr(Fpscr);
1069 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
1070 cDest.fp = FpOp1;
1071 __asm__ __volatile__("" :: "m" (cDest.fp));
1072 Fpscr = setVfpFpscr(Fpscr, state);
1073 FpDestP0.uw = cDest.bits;
1074 FpDestP1.uw = cDest.bits >> 32;
1075 '''
1076 vcvtFpSFpDIop = InstObjParams("vcvt", "VcvtFpSFpD", "VfpRegRegOp",
1077 { "code": vcvtFpSFpDCode,
1078 "predicate_test": predicateTest }, [])
1079 header_output += VfpRegRegOpDeclare.subst(vcvtFpSFpDIop);
1080 decoder_output += VfpRegRegOpConstructor.subst(vcvtFpSFpDIop);
1081 exec_output += PredOpExecute.subst(vcvtFpSFpDIop);
1082
1083 vcvtFpDFpSCode = '''
1084 IntDoubleUnion cOp1;
1085 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
1086 vfpFlushToZero(Fpscr, cOp1.fp);
1049 VfpSavedState state = prepVfpFpscr(Fpscr);
1050 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp));
1051 FpDest = cOp1.fp;
1052 __asm__ __volatile__("" :: "m" (FpDest));
1053 Fpscr = setVfpFpscr(Fpscr, state);
1054 '''
1055 vcvtFpDFpSIop = InstObjParams("vcvt", "VcvtFpDFpS", "VfpRegRegOp",
1056 { "code": vcvtFpDFpSCode,
1057 "predicate_test": predicateTest }, [])
1058 header_output += VfpRegRegOpDeclare.subst(vcvtFpDFpSIop);
1059 decoder_output += VfpRegRegOpConstructor.subst(vcvtFpDFpSIop);
1060 exec_output += PredOpExecute.subst(vcvtFpDFpSIop);
1061
1062 vcmpSCode = '''
1063 FPSCR fpscr = Fpscr;
1087 VfpSavedState state = prepVfpFpscr(Fpscr);
1088 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp));
1089 FpDest = cOp1.fp;
1090 __asm__ __volatile__("" :: "m" (FpDest));
1091 Fpscr = setVfpFpscr(Fpscr, state);
1092 '''
1093 vcvtFpDFpSIop = InstObjParams("vcvt", "VcvtFpDFpS", "VfpRegRegOp",
1094 { "code": vcvtFpDFpSCode,
1095 "predicate_test": predicateTest }, [])
1096 header_output += VfpRegRegOpDeclare.subst(vcvtFpDFpSIop);
1097 decoder_output += VfpRegRegOpConstructor.subst(vcvtFpDFpSIop);
1098 exec_output += PredOpExecute.subst(vcvtFpDFpSIop);
1099
1100 vcmpSCode = '''
1101 FPSCR fpscr = Fpscr;
1102 vfpFlushToZero(Fpscr, FpDest, FpOp1);
1064 if (FpDest == FpOp1) {
1065 fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0;
1066 } else if (FpDest < FpOp1) {
1067 fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0;
1068 } else if (FpDest > FpOp1) {
1069 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0;
1070 } else {
1071 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1;

--- 6 unchanged lines hidden (view full) ---

1078 header_output += VfpRegRegOpDeclare.subst(vcmpSIop);
1079 decoder_output += VfpRegRegOpConstructor.subst(vcmpSIop);
1080 exec_output += PredOpExecute.subst(vcmpSIop);
1081
1082 vcmpDCode = '''
1083 IntDoubleUnion cOp1, cDest;
1084 cDest.bits = ((uint64_t)FpDestP0.uw | ((uint64_t)FpDestP1.uw << 32));
1085 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
1103 if (FpDest == FpOp1) {
1104 fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0;
1105 } else if (FpDest < FpOp1) {
1106 fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0;
1107 } else if (FpDest > FpOp1) {
1108 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0;
1109 } else {
1110 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1;

--- 6 unchanged lines hidden (view full) ---

1117 header_output += VfpRegRegOpDeclare.subst(vcmpSIop);
1118 decoder_output += VfpRegRegOpConstructor.subst(vcmpSIop);
1119 exec_output += PredOpExecute.subst(vcmpSIop);
1120
1121 vcmpDCode = '''
1122 IntDoubleUnion cOp1, cDest;
1123 cDest.bits = ((uint64_t)FpDestP0.uw | ((uint64_t)FpDestP1.uw << 32));
1124 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
1125 vfpFlushToZero(Fpscr, cDest.fp, cOp1.fp);
1086 FPSCR fpscr = Fpscr;
1087 if (cDest.fp == cOp1.fp) {
1088 fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0;
1089 } else if (cDest.fp < cOp1.fp) {
1090 fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0;
1091 } else if (cDest.fp > cOp1.fp) {
1092 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0;
1093 } else {

--- 5 unchanged lines hidden (view full) ---

1099 { "code": vcmpDCode,
1100 "predicate_test": predicateTest }, [])
1101 header_output += VfpRegRegOpDeclare.subst(vcmpDIop);
1102 decoder_output += VfpRegRegOpConstructor.subst(vcmpDIop);
1103 exec_output += PredOpExecute.subst(vcmpDIop);
1104
1105 vcmpZeroSCode = '''
1106 FPSCR fpscr = Fpscr;
1126 FPSCR fpscr = Fpscr;
1127 if (cDest.fp == cOp1.fp) {
1128 fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0;
1129 } else if (cDest.fp < cOp1.fp) {
1130 fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0;
1131 } else if (cDest.fp > cOp1.fp) {
1132 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0;
1133 } else {

--- 5 unchanged lines hidden (view full) ---

1139 { "code": vcmpDCode,
1140 "predicate_test": predicateTest }, [])
1141 header_output += VfpRegRegOpDeclare.subst(vcmpDIop);
1142 decoder_output += VfpRegRegOpConstructor.subst(vcmpDIop);
1143 exec_output += PredOpExecute.subst(vcmpDIop);
1144
1145 vcmpZeroSCode = '''
1146 FPSCR fpscr = Fpscr;
1147 vfpFlushToZero(Fpscr, FpDest);
1107 if (FpDest == imm) {
1108 fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0;
1109 } else if (FpDest < imm) {
1110 fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0;
1111 } else if (FpDest > imm) {
1112 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0;
1113 } else {
1114 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1;

--- 5 unchanged lines hidden (view full) ---

1120 "predicate_test": predicateTest }, [])
1121 header_output += VfpRegImmOpDeclare.subst(vcmpZeroSIop);
1122 decoder_output += VfpRegImmOpConstructor.subst(vcmpZeroSIop);
1123 exec_output += PredOpExecute.subst(vcmpZeroSIop);
1124
1125 vcmpZeroDCode = '''
1126 IntDoubleUnion cDest;
1127 cDest.bits = ((uint64_t)FpDestP0.uw | ((uint64_t)FpDestP1.uw << 32));
1148 if (FpDest == imm) {
1149 fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0;
1150 } else if (FpDest < imm) {
1151 fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0;
1152 } else if (FpDest > imm) {
1153 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0;
1154 } else {
1155 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1;

--- 5 unchanged lines hidden (view full) ---

1161 "predicate_test": predicateTest }, [])
1162 header_output += VfpRegImmOpDeclare.subst(vcmpZeroSIop);
1163 decoder_output += VfpRegImmOpConstructor.subst(vcmpZeroSIop);
1164 exec_output += PredOpExecute.subst(vcmpZeroSIop);
1165
1166 vcmpZeroDCode = '''
1167 IntDoubleUnion cDest;
1168 cDest.bits = ((uint64_t)FpDestP0.uw | ((uint64_t)FpDestP1.uw << 32));
1169 vfpFlushToZero(Fpscr, cDest.fp);
1128 FPSCR fpscr = Fpscr;
1129 if (cDest.fp == imm) {
1130 fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0;
1131 } else if (cDest.fp < imm) {
1132 fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0;
1133 } else if (cDest.fp > imm) {
1134 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0;
1135 } else {

--- 11 unchanged lines hidden (view full) ---

1147
1148let {{
1149
1150 header_output = ""
1151 decoder_output = ""
1152 exec_output = ""
1153
1154 vcvtFpSFixedSCode = '''
1170 FPSCR fpscr = Fpscr;
1171 if (cDest.fp == imm) {
1172 fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0;
1173 } else if (cDest.fp < imm) {
1174 fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0;
1175 } else if (cDest.fp > imm) {
1176 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0;
1177 } else {

--- 11 unchanged lines hidden (view full) ---

1189
1190let {{
1191
1192 header_output = ""
1193 decoder_output = ""
1194 exec_output = ""
1195
1196 vcvtFpSFixedSCode = '''
1197 vfpFlushToZero(Fpscr, FpOp1);
1155 VfpSavedState state = prepVfpFpscr(Fpscr);
1156 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
1157 FpDest.sw = vfpFpSToFixed(FpOp1, true, false, imm);
1158 __asm__ __volatile__("" :: "m" (FpDest.sw));
1159 Fpscr = setVfpFpscr(Fpscr, state);
1160 '''
1161 vcvtFpSFixedSIop = InstObjParams("vcvt", "VcvtFpSFixedS", "VfpRegRegImmOp",
1162 { "code": vcvtFpSFixedSCode,
1163 "predicate_test": predicateTest }, [])
1164 header_output += VfpRegRegImmOpDeclare.subst(vcvtFpSFixedSIop);
1165 decoder_output += VfpRegRegImmOpConstructor.subst(vcvtFpSFixedSIop);
1166 exec_output += PredOpExecute.subst(vcvtFpSFixedSIop);
1167
1168 vcvtFpSFixedDCode = '''
1169 IntDoubleUnion cOp1;
1170 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
1198 VfpSavedState state = prepVfpFpscr(Fpscr);
1199 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
1200 FpDest.sw = vfpFpSToFixed(FpOp1, true, false, imm);
1201 __asm__ __volatile__("" :: "m" (FpDest.sw));
1202 Fpscr = setVfpFpscr(Fpscr, state);
1203 '''
1204 vcvtFpSFixedSIop = InstObjParams("vcvt", "VcvtFpSFixedS", "VfpRegRegImmOp",
1205 { "code": vcvtFpSFixedSCode,
1206 "predicate_test": predicateTest }, [])
1207 header_output += VfpRegRegImmOpDeclare.subst(vcvtFpSFixedSIop);
1208 decoder_output += VfpRegRegImmOpConstructor.subst(vcvtFpSFixedSIop);
1209 exec_output += PredOpExecute.subst(vcvtFpSFixedSIop);
1210
1211 vcvtFpSFixedDCode = '''
1212 IntDoubleUnion cOp1;
1213 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
1214 vfpFlushToZero(Fpscr, cOp1.fp);
1171 VfpSavedState state = prepVfpFpscr(Fpscr);
1172 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp));
1173 uint64_t mid = vfpFpDToFixed(cOp1.fp, true, false, imm);
1174 __asm__ __volatile__("" :: "m" (mid));
1175 Fpscr = setVfpFpscr(Fpscr, state);
1176 FpDestP0.uw = mid;
1177 FpDestP1.uw = mid >> 32;
1178 '''
1179 vcvtFpSFixedDIop = InstObjParams("vcvt", "VcvtFpSFixedD", "VfpRegRegImmOp",
1180 { "code": vcvtFpSFixedDCode,
1181 "predicate_test": predicateTest }, [])
1182 header_output += VfpRegRegImmOpDeclare.subst(vcvtFpSFixedDIop);
1183 decoder_output += VfpRegRegImmOpConstructor.subst(vcvtFpSFixedDIop);
1184 exec_output += PredOpExecute.subst(vcvtFpSFixedDIop);
1185
1186 vcvtFpUFixedSCode = '''
1215 VfpSavedState state = prepVfpFpscr(Fpscr);
1216 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp));
1217 uint64_t mid = vfpFpDToFixed(cOp1.fp, true, false, imm);
1218 __asm__ __volatile__("" :: "m" (mid));
1219 Fpscr = setVfpFpscr(Fpscr, state);
1220 FpDestP0.uw = mid;
1221 FpDestP1.uw = mid >> 32;
1222 '''
1223 vcvtFpSFixedDIop = InstObjParams("vcvt", "VcvtFpSFixedD", "VfpRegRegImmOp",
1224 { "code": vcvtFpSFixedDCode,
1225 "predicate_test": predicateTest }, [])
1226 header_output += VfpRegRegImmOpDeclare.subst(vcvtFpSFixedDIop);
1227 decoder_output += VfpRegRegImmOpConstructor.subst(vcvtFpSFixedDIop);
1228 exec_output += PredOpExecute.subst(vcvtFpSFixedDIop);
1229
1230 vcvtFpUFixedSCode = '''
1231 vfpFlushToZero(Fpscr, FpOp1);
1187 VfpSavedState state = prepVfpFpscr(Fpscr);
1188 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
1189 FpDest.uw = vfpFpSToFixed(FpOp1, false, false, imm);
1190 __asm__ __volatile__("" :: "m" (FpDest.uw));
1191 Fpscr = setVfpFpscr(Fpscr, state);
1192 '''
1193 vcvtFpUFixedSIop = InstObjParams("vcvt", "VcvtFpUFixedS", "VfpRegRegImmOp",
1194 { "code": vcvtFpUFixedSCode,
1195 "predicate_test": predicateTest }, [])
1196 header_output += VfpRegRegImmOpDeclare.subst(vcvtFpUFixedSIop);
1197 decoder_output += VfpRegRegImmOpConstructor.subst(vcvtFpUFixedSIop);
1198 exec_output += PredOpExecute.subst(vcvtFpUFixedSIop);
1199
1200 vcvtFpUFixedDCode = '''
1201 IntDoubleUnion cOp1;
1202 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
1232 VfpSavedState state = prepVfpFpscr(Fpscr);
1233 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
1234 FpDest.uw = vfpFpSToFixed(FpOp1, false, false, imm);
1235 __asm__ __volatile__("" :: "m" (FpDest.uw));
1236 Fpscr = setVfpFpscr(Fpscr, state);
1237 '''
1238 vcvtFpUFixedSIop = InstObjParams("vcvt", "VcvtFpUFixedS", "VfpRegRegImmOp",
1239 { "code": vcvtFpUFixedSCode,
1240 "predicate_test": predicateTest }, [])
1241 header_output += VfpRegRegImmOpDeclare.subst(vcvtFpUFixedSIop);
1242 decoder_output += VfpRegRegImmOpConstructor.subst(vcvtFpUFixedSIop);
1243 exec_output += PredOpExecute.subst(vcvtFpUFixedSIop);
1244
1245 vcvtFpUFixedDCode = '''
1246 IntDoubleUnion cOp1;
1247 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
1248 vfpFlushToZero(Fpscr, cOp1.fp);
1203 VfpSavedState state = prepVfpFpscr(Fpscr);
1204 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp));
1205 uint64_t mid = vfpFpDToFixed(cOp1.fp, false, false, imm);
1206 __asm__ __volatile__("" :: "m" (mid));
1207 Fpscr = setVfpFpscr(Fpscr, state);
1208 FpDestP0.uw = mid;
1209 FpDestP1.uw = mid >> 32;
1210 '''

--- 64 unchanged lines hidden (view full) ---

1275 vcvtUFixedFpDIop = InstObjParams("vcvt", "VcvtUFixedFpD", "VfpRegRegImmOp",
1276 { "code": vcvtUFixedFpDCode,
1277 "predicate_test": predicateTest }, [])
1278 header_output += VfpRegRegImmOpDeclare.subst(vcvtUFixedFpDIop);
1279 decoder_output += VfpRegRegImmOpConstructor.subst(vcvtUFixedFpDIop);
1280 exec_output += PredOpExecute.subst(vcvtUFixedFpDIop);
1281
1282 vcvtFpSHFixedSCode = '''
1249 VfpSavedState state = prepVfpFpscr(Fpscr);
1250 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp));
1251 uint64_t mid = vfpFpDToFixed(cOp1.fp, false, false, imm);
1252 __asm__ __volatile__("" :: "m" (mid));
1253 Fpscr = setVfpFpscr(Fpscr, state);
1254 FpDestP0.uw = mid;
1255 FpDestP1.uw = mid >> 32;
1256 '''

--- 64 unchanged lines hidden (view full) ---

1321 vcvtUFixedFpDIop = InstObjParams("vcvt", "VcvtUFixedFpD", "VfpRegRegImmOp",
1322 { "code": vcvtUFixedFpDCode,
1323 "predicate_test": predicateTest }, [])
1324 header_output += VfpRegRegImmOpDeclare.subst(vcvtUFixedFpDIop);
1325 decoder_output += VfpRegRegImmOpConstructor.subst(vcvtUFixedFpDIop);
1326 exec_output += PredOpExecute.subst(vcvtUFixedFpDIop);
1327
1328 vcvtFpSHFixedSCode = '''
1329 vfpFlushToZero(Fpscr, FpOp1);
1283 VfpSavedState state = prepVfpFpscr(Fpscr);
1284 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
1285 FpDest.sh = vfpFpSToFixed(FpOp1, true, true, imm);
1286 __asm__ __volatile__("" :: "m" (FpDest.sh));
1287 Fpscr = setVfpFpscr(Fpscr, state);
1288 '''
1289 vcvtFpSHFixedSIop = InstObjParams("vcvt", "VcvtFpSHFixedS",
1290 "VfpRegRegImmOp",
1291 { "code": vcvtFpSHFixedSCode,
1292 "predicate_test": predicateTest }, [])
1293 header_output += VfpRegRegImmOpDeclare.subst(vcvtFpSHFixedSIop);
1294 decoder_output += VfpRegRegImmOpConstructor.subst(vcvtFpSHFixedSIop);
1295 exec_output += PredOpExecute.subst(vcvtFpSHFixedSIop);
1296
1297 vcvtFpSHFixedDCode = '''
1298 IntDoubleUnion cOp1;
1299 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
1330 VfpSavedState state = prepVfpFpscr(Fpscr);
1331 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
1332 FpDest.sh = vfpFpSToFixed(FpOp1, true, true, imm);
1333 __asm__ __volatile__("" :: "m" (FpDest.sh));
1334 Fpscr = setVfpFpscr(Fpscr, state);
1335 '''
1336 vcvtFpSHFixedSIop = InstObjParams("vcvt", "VcvtFpSHFixedS",
1337 "VfpRegRegImmOp",
1338 { "code": vcvtFpSHFixedSCode,
1339 "predicate_test": predicateTest }, [])
1340 header_output += VfpRegRegImmOpDeclare.subst(vcvtFpSHFixedSIop);
1341 decoder_output += VfpRegRegImmOpConstructor.subst(vcvtFpSHFixedSIop);
1342 exec_output += PredOpExecute.subst(vcvtFpSHFixedSIop);
1343
1344 vcvtFpSHFixedDCode = '''
1345 IntDoubleUnion cOp1;
1346 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
1347 vfpFlushToZero(Fpscr, cOp1.fp);
1300 VfpSavedState state = prepVfpFpscr(Fpscr);
1301 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp));
1302 uint64_t result = vfpFpDToFixed(cOp1.fp, true, true, imm);
1303 __asm__ __volatile__("" :: "m" (result));
1304 Fpscr = setVfpFpscr(Fpscr, state);
1305 FpDestP0.uw = result;
1306 FpDestP1.uw = result >> 32;
1307 '''
1308 vcvtFpSHFixedDIop = InstObjParams("vcvt", "VcvtFpSHFixedD",
1309 "VfpRegRegImmOp",
1310 { "code": vcvtFpSHFixedDCode,
1311 "predicate_test": predicateTest }, [])
1312 header_output += VfpRegRegImmOpDeclare.subst(vcvtFpSHFixedDIop);
1313 decoder_output += VfpRegRegImmOpConstructor.subst(vcvtFpSHFixedDIop);
1314 exec_output += PredOpExecute.subst(vcvtFpSHFixedDIop);
1315
1316 vcvtFpUHFixedSCode = '''
1348 VfpSavedState state = prepVfpFpscr(Fpscr);
1349 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp));
1350 uint64_t result = vfpFpDToFixed(cOp1.fp, true, true, imm);
1351 __asm__ __volatile__("" :: "m" (result));
1352 Fpscr = setVfpFpscr(Fpscr, state);
1353 FpDestP0.uw = result;
1354 FpDestP1.uw = result >> 32;
1355 '''
1356 vcvtFpSHFixedDIop = InstObjParams("vcvt", "VcvtFpSHFixedD",
1357 "VfpRegRegImmOp",
1358 { "code": vcvtFpSHFixedDCode,
1359 "predicate_test": predicateTest }, [])
1360 header_output += VfpRegRegImmOpDeclare.subst(vcvtFpSHFixedDIop);
1361 decoder_output += VfpRegRegImmOpConstructor.subst(vcvtFpSHFixedDIop);
1362 exec_output += PredOpExecute.subst(vcvtFpSHFixedDIop);
1363
1364 vcvtFpUHFixedSCode = '''
1365 vfpFlushToZero(Fpscr, FpOp1);
1317 VfpSavedState state = prepVfpFpscr(Fpscr);
1318 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
1319 FpDest.uh = vfpFpSToFixed(FpOp1, false, true, imm);
1320 __asm__ __volatile__("" :: "m" (FpDest.uh));
1321 Fpscr = setVfpFpscr(Fpscr, state);
1322 '''
1323 vcvtFpUHFixedSIop = InstObjParams("vcvt", "VcvtFpUHFixedS",
1324 "VfpRegRegImmOp",
1325 { "code": vcvtFpUHFixedSCode,
1326 "predicate_test": predicateTest }, [])
1327 header_output += VfpRegRegImmOpDeclare.subst(vcvtFpUHFixedSIop);
1328 decoder_output += VfpRegRegImmOpConstructor.subst(vcvtFpUHFixedSIop);
1329 exec_output += PredOpExecute.subst(vcvtFpUHFixedSIop);
1330
1331 vcvtFpUHFixedDCode = '''
1332 IntDoubleUnion cOp1;
1333 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
1366 VfpSavedState state = prepVfpFpscr(Fpscr);
1367 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
1368 FpDest.uh = vfpFpSToFixed(FpOp1, false, true, imm);
1369 __asm__ __volatile__("" :: "m" (FpDest.uh));
1370 Fpscr = setVfpFpscr(Fpscr, state);
1371 '''
1372 vcvtFpUHFixedSIop = InstObjParams("vcvt", "VcvtFpUHFixedS",
1373 "VfpRegRegImmOp",
1374 { "code": vcvtFpUHFixedSCode,
1375 "predicate_test": predicateTest }, [])
1376 header_output += VfpRegRegImmOpDeclare.subst(vcvtFpUHFixedSIop);
1377 decoder_output += VfpRegRegImmOpConstructor.subst(vcvtFpUHFixedSIop);
1378 exec_output += PredOpExecute.subst(vcvtFpUHFixedSIop);
1379
1380 vcvtFpUHFixedDCode = '''
1381 IntDoubleUnion cOp1;
1382 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
1383 vfpFlushToZero(Fpscr, cOp1.fp);
1334 VfpSavedState state = prepVfpFpscr(Fpscr);
1335 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp));
1336 uint64_t mid = vfpFpDToFixed(cOp1.fp, false, true, imm);
1337 __asm__ __volatile__("" :: "m" (mid));
1338 Fpscr = setVfpFpscr(Fpscr, state);
1339 FpDestP0.uw = mid;
1340 FpDestP1.uw = mid >> 32;
1341 '''

--- 76 unchanged lines hidden --- 		1384 VfpSavedState state = prepVfpFpscr(Fpscr);
1385 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp));
1386 uint64_t mid = vfpFpDToFixed(cOp1.fp, false, true, imm);
1387 __asm__ __volatile__("" :: "m" (mid));
1388 Fpscr = setVfpFpscr(Fpscr, state);
1389 FpDestP0.uw = mid;
1390 FpDestP1.uw = mid >> 32;
1391 '''

--- 76 unchanged lines hidden ---