fp.isa (7379:92ef7238d230) fp.isa (7380:baee640ca6a4)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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824 '''
825 vcvtSIntFpDIop = InstObjParams("vcvt", "VcvtSIntFpD", "VfpRegRegOp",
826 { "code": vcvtSIntFpDCode,
827 "predicate_test": predicateTest }, [])
828 header_output += VfpRegRegOpDeclare.subst(vcvtSIntFpDIop);
829 decoder_output += VfpRegRegOpConstructor.subst(vcvtSIntFpDIop);
830 exec_output += PredOpExecute.subst(vcvtSIntFpDIop);
831
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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824 '''
825 vcvtSIntFpDIop = InstObjParams("vcvt", "VcvtSIntFpD", "VfpRegRegOp",
826 { "code": vcvtSIntFpDCode,
827 "predicate_test": predicateTest }, [])
828 header_output += VfpRegRegOpDeclare.subst(vcvtSIntFpDIop);
829 decoder_output += VfpRegRegOpConstructor.subst(vcvtSIntFpDIop);
830 exec_output += PredOpExecute.subst(vcvtSIntFpDIop);
831
832 vcvtFpUIntSRCode = '''
833 VfpSavedState state = prepVfpFpscr(Fpscr);
834 FpDest.uw = FpOp1;
835 Fpscr = setVfpFpscr(Fpscr, state);
836 '''
837 vcvtFpUIntSRIop = InstObjParams("vcvt", "VcvtFpUIntSR", "VfpRegRegOp",
838 { "code": vcvtFpUIntSRCode,
839 "predicate_test": predicateTest }, [])
840 header_output += VfpRegRegOpDeclare.subst(vcvtFpUIntSRIop);
841 decoder_output += VfpRegRegOpConstructor.subst(vcvtFpUIntSRIop);
842 exec_output += PredOpExecute.subst(vcvtFpUIntSRIop);
843
844 vcvtFpUIntDRCode = '''
845 IntDoubleUnion cOp1;
846 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
847 VfpSavedState state = prepVfpFpscr(Fpscr);
848 uint64_t result = cOp1.fp;
849 Fpscr = setVfpFpscr(Fpscr, state);
850 FpDestP0.uw = result;
851 '''
852 vcvtFpUIntDRIop = InstObjParams("vcvtr", "VcvtFpUIntDR", "VfpRegRegOp",
853 { "code": vcvtFpUIntDRCode,
854 "predicate_test": predicateTest }, [])
855 header_output += VfpRegRegOpDeclare.subst(vcvtFpUIntDRIop);
856 decoder_output += VfpRegRegOpConstructor.subst(vcvtFpUIntDRIop);
857 exec_output += PredOpExecute.subst(vcvtFpUIntDRIop);
858
859 vcvtFpSIntSRCode = '''
860 VfpSavedState state = prepVfpFpscr(Fpscr);
861 FpDest.sw = FpOp1;
862 Fpscr = setVfpFpscr(Fpscr, state);
863 '''
864 vcvtFpSIntSRIop = InstObjParams("vcvtr", "VcvtFpSIntSR", "VfpRegRegOp",
865 { "code": vcvtFpSIntSRCode,
866 "predicate_test": predicateTest }, [])
867 header_output += VfpRegRegOpDeclare.subst(vcvtFpSIntSRIop);
868 decoder_output += VfpRegRegOpConstructor.subst(vcvtFpSIntSRIop);
869 exec_output += PredOpExecute.subst(vcvtFpSIntSRIop);
870
871 vcvtFpSIntDRCode = '''
872 IntDoubleUnion cOp1;
873 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
874 VfpSavedState state = prepVfpFpscr(Fpscr);
875 int64_t result = cOp1.fp;
876 Fpscr = setVfpFpscr(Fpscr, state);
877 FpDestP0.uw = result;
878 '''
879 vcvtFpSIntDRIop = InstObjParams("vcvtr", "VcvtFpSIntDR", "VfpRegRegOp",
880 { "code": vcvtFpSIntDRCode,
881 "predicate_test": predicateTest }, [])
882 header_output += VfpRegRegOpDeclare.subst(vcvtFpSIntDRIop);
883 decoder_output += VfpRegRegOpConstructor.subst(vcvtFpSIntDRIop);
884 exec_output += PredOpExecute.subst(vcvtFpSIntDRIop);
885
832 vcvtFpUIntSCode = '''
833 VfpSavedState state = prepVfpFpscr(Fpscr);
886 vcvtFpUIntSCode = '''
887 VfpSavedState state = prepVfpFpscr(Fpscr);
888 fesetround(FeRoundZero);
834 FpDest.uw = FpOp1;
835 Fpscr = setVfpFpscr(Fpscr, state);
836 '''
837 vcvtFpUIntSIop = InstObjParams("vcvt", "VcvtFpUIntS", "VfpRegRegOp",
838 { "code": vcvtFpUIntSCode,
839 "predicate_test": predicateTest }, [])
840 header_output += VfpRegRegOpDeclare.subst(vcvtFpUIntSIop);
841 decoder_output += VfpRegRegOpConstructor.subst(vcvtFpUIntSIop);
842 exec_output += PredOpExecute.subst(vcvtFpUIntSIop);
843
844 vcvtFpUIntDCode = '''
845 IntDoubleUnion cOp1;
846 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
847 VfpSavedState state = prepVfpFpscr(Fpscr);
889 FpDest.uw = FpOp1;
890 Fpscr = setVfpFpscr(Fpscr, state);
891 '''
892 vcvtFpUIntSIop = InstObjParams("vcvt", "VcvtFpUIntS", "VfpRegRegOp",
893 { "code": vcvtFpUIntSCode,
894 "predicate_test": predicateTest }, [])
895 header_output += VfpRegRegOpDeclare.subst(vcvtFpUIntSIop);
896 decoder_output += VfpRegRegOpConstructor.subst(vcvtFpUIntSIop);
897 exec_output += PredOpExecute.subst(vcvtFpUIntSIop);
898
899 vcvtFpUIntDCode = '''
900 IntDoubleUnion cOp1;
901 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
902 VfpSavedState state = prepVfpFpscr(Fpscr);
903 fesetround(FeRoundZero);
848 uint64_t result = cOp1.fp;
849 Fpscr = setVfpFpscr(Fpscr, state);
850 FpDestP0.uw = result;
851 '''
852 vcvtFpUIntDIop = InstObjParams("vcvt", "VcvtFpUIntD", "VfpRegRegOp",
853 { "code": vcvtFpUIntDCode,
854 "predicate_test": predicateTest }, [])
855 header_output += VfpRegRegOpDeclare.subst(vcvtFpUIntDIop);
856 decoder_output += VfpRegRegOpConstructor.subst(vcvtFpUIntDIop);
857 exec_output += PredOpExecute.subst(vcvtFpUIntDIop);
858
859 vcvtFpSIntSCode = '''
860 VfpSavedState state = prepVfpFpscr(Fpscr);
904 uint64_t result = cOp1.fp;
905 Fpscr = setVfpFpscr(Fpscr, state);
906 FpDestP0.uw = result;
907 '''
908 vcvtFpUIntDIop = InstObjParams("vcvt", "VcvtFpUIntD", "VfpRegRegOp",
909 { "code": vcvtFpUIntDCode,
910 "predicate_test": predicateTest }, [])
911 header_output += VfpRegRegOpDeclare.subst(vcvtFpUIntDIop);
912 decoder_output += VfpRegRegOpConstructor.subst(vcvtFpUIntDIop);
913 exec_output += PredOpExecute.subst(vcvtFpUIntDIop);
914
915 vcvtFpSIntSCode = '''
916 VfpSavedState state = prepVfpFpscr(Fpscr);
917 fesetround(FeRoundZero);
861 FpDest.sw = FpOp1;
862 Fpscr = setVfpFpscr(Fpscr, state);
863 '''
864 vcvtFpSIntSIop = InstObjParams("vcvt", "VcvtFpSIntS", "VfpRegRegOp",
865 { "code": vcvtFpSIntSCode,
866 "predicate_test": predicateTest }, [])
867 header_output += VfpRegRegOpDeclare.subst(vcvtFpSIntSIop);
868 decoder_output += VfpRegRegOpConstructor.subst(vcvtFpSIntSIop);
869 exec_output += PredOpExecute.subst(vcvtFpSIntSIop);
870
871 vcvtFpSIntDCode = '''
872 IntDoubleUnion cOp1;
873 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
874 VfpSavedState state = prepVfpFpscr(Fpscr);
918 FpDest.sw = FpOp1;
919 Fpscr = setVfpFpscr(Fpscr, state);
920 '''
921 vcvtFpSIntSIop = InstObjParams("vcvt", "VcvtFpSIntS", "VfpRegRegOp",
922 { "code": vcvtFpSIntSCode,
923 "predicate_test": predicateTest }, [])
924 header_output += VfpRegRegOpDeclare.subst(vcvtFpSIntSIop);
925 decoder_output += VfpRegRegOpConstructor.subst(vcvtFpSIntSIop);
926 exec_output += PredOpExecute.subst(vcvtFpSIntSIop);
927
928 vcvtFpSIntDCode = '''
929 IntDoubleUnion cOp1;
930 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
931 VfpSavedState state = prepVfpFpscr(Fpscr);
932 fesetround(FeRoundZero);
875 int64_t result = cOp1.fp;
876 Fpscr = setVfpFpscr(Fpscr, state);
877 FpDestP0.uw = result;
878 '''
879 vcvtFpSIntDIop = InstObjParams("vcvt", "VcvtFpSIntD", "VfpRegRegOp",
880 { "code": vcvtFpSIntDCode,
881 "predicate_test": predicateTest }, [])
882 header_output += VfpRegRegOpDeclare.subst(vcvtFpSIntDIop);

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1057 { "code": vcvtFpUFixedDCode,
1058 "predicate_test": predicateTest }, [])
1059 header_output += VfpRegRegImmOpDeclare.subst(vcvtFpUFixedDIop);
1060 decoder_output += VfpRegRegImmOpConstructor.subst(vcvtFpUFixedDIop);
1061 exec_output += PredOpExecute.subst(vcvtFpUFixedDIop);
1062
1063 vcvtSFixedFpSCode = '''
1064 VfpSavedState state = prepVfpFpscr(Fpscr);
933 int64_t result = cOp1.fp;
934 Fpscr = setVfpFpscr(Fpscr, state);
935 FpDestP0.uw = result;
936 '''
937 vcvtFpSIntDIop = InstObjParams("vcvt", "VcvtFpSIntD", "VfpRegRegOp",
938 { "code": vcvtFpSIntDCode,
939 "predicate_test": predicateTest }, [])
940 header_output += VfpRegRegOpDeclare.subst(vcvtFpSIntDIop);

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1115 { "code": vcvtFpUFixedDCode,
1116 "predicate_test": predicateTest }, [])
1117 header_output += VfpRegRegImmOpDeclare.subst(vcvtFpUFixedDIop);
1118 decoder_output += VfpRegRegImmOpConstructor.subst(vcvtFpUFixedDIop);
1119 exec_output += PredOpExecute.subst(vcvtFpUFixedDIop);
1120
1121 vcvtSFixedFpSCode = '''
1122 VfpSavedState state = prepVfpFpscr(Fpscr);
1065 FpDest = vfpSFixedToFpS(FpOp1.sw, true, imm);
1123 FpDest = vfpSFixedToFpS(FpOp1.sw, false, imm);
1066 Fpscr = setVfpFpscr(Fpscr, state);
1067 '''
1068 vcvtSFixedFpSIop = InstObjParams("vcvt", "VcvtSFixedFpS", "VfpRegRegImmOp",
1069 { "code": vcvtSFixedFpSCode,
1070 "predicate_test": predicateTest }, [])
1071 header_output += VfpRegRegImmOpDeclare.subst(vcvtSFixedFpSIop);
1072 decoder_output += VfpRegRegImmOpConstructor.subst(vcvtSFixedFpSIop);
1073 exec_output += PredOpExecute.subst(vcvtSFixedFpSIop);
1074
1075 vcvtSFixedFpDCode = '''
1076 IntDoubleUnion cDest;
1077 uint64_t mid = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
1078 VfpSavedState state = prepVfpFpscr(Fpscr);
1124 Fpscr = setVfpFpscr(Fpscr, state);
1125 '''
1126 vcvtSFixedFpSIop = InstObjParams("vcvt", "VcvtSFixedFpS", "VfpRegRegImmOp",
1127 { "code": vcvtSFixedFpSCode,
1128 "predicate_test": predicateTest }, [])
1129 header_output += VfpRegRegImmOpDeclare.subst(vcvtSFixedFpSIop);
1130 decoder_output += VfpRegRegImmOpConstructor.subst(vcvtSFixedFpSIop);
1131 exec_output += PredOpExecute.subst(vcvtSFixedFpSIop);
1132
1133 vcvtSFixedFpDCode = '''
1134 IntDoubleUnion cDest;
1135 uint64_t mid = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
1136 VfpSavedState state = prepVfpFpscr(Fpscr);
1079 cDest.fp = vfpSFixedToFpD(mid, true, imm);
1137 cDest.fp = vfpSFixedToFpD(mid, false, imm);
1080 Fpscr = setVfpFpscr(Fpscr, state);
1081 FpDestP0.uw = cDest.bits;
1082 FpDestP1.uw = cDest.bits >> 32;
1083 '''
1084 vcvtSFixedFpDIop = InstObjParams("vcvt", "VcvtSFixedFpD", "VfpRegRegImmOp",
1085 { "code": vcvtSFixedFpDCode,
1086 "predicate_test": predicateTest }, [])
1087 header_output += VfpRegRegImmOpDeclare.subst(vcvtSFixedFpDIop);

--- 151 unchanged lines hidden --- 		1138 Fpscr = setVfpFpscr(Fpscr, state);
1139 FpDestP0.uw = cDest.bits;
1140 FpDestP1.uw = cDest.bits >> 32;
1141 '''
1142 vcvtSFixedFpDIop = InstObjParams("vcvt", "VcvtSFixedFpD", "VfpRegRegImmOp",
1143 { "code": vcvtSFixedFpDCode,
1144 "predicate_test": predicateTest }, [])
1145 header_output += VfpRegRegImmOpDeclare.subst(vcvtSFixedFpDIop);

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