fp.isa (7378:de704acd042f) | fp.isa (7379:92ef7238d230) |
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1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating --- 983 unchanged lines hidden (view full) --- 992 ''' 993 vcmpZeroDIop = InstObjParams("vcmpZerod", "VcmpZeroD", "VfpRegImmOp", 994 { "code": vcmpZeroDCode, 995 "predicate_test": predicateTest }, []) 996 header_output += VfpRegImmOpDeclare.subst(vcmpZeroDIop); 997 decoder_output += VfpRegImmOpConstructor.subst(vcmpZeroDIop); 998 exec_output += PredOpExecute.subst(vcmpZeroDIop); 999}}; | 1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating --- 983 unchanged lines hidden (view full) --- 992 ''' 993 vcmpZeroDIop = InstObjParams("vcmpZerod", "VcmpZeroD", "VfpRegImmOp", 994 { "code": vcmpZeroDCode, 995 "predicate_test": predicateTest }, []) 996 header_output += VfpRegImmOpDeclare.subst(vcmpZeroDIop); 997 decoder_output += VfpRegImmOpConstructor.subst(vcmpZeroDIop); 998 exec_output += PredOpExecute.subst(vcmpZeroDIop); 999}}; |
1000 1001let {{ 1002 1003 header_output = "" 1004 decoder_output = "" 1005 exec_output = "" 1006 1007 vcvtFpSFixedSCode = ''' 1008 VfpSavedState state = prepVfpFpscr(Fpscr); 1009 FpDest.sw = vfpFpSToFixed(FpOp1, true, false, imm); 1010 Fpscr = setVfpFpscr(Fpscr, state); 1011 ''' 1012 vcvtFpSFixedSIop = InstObjParams("vcvt", "VcvtFpSFixedS", "VfpRegRegImmOp", 1013 { "code": vcvtFpSFixedSCode, 1014 "predicate_test": predicateTest }, []) 1015 header_output += VfpRegRegImmOpDeclare.subst(vcvtFpSFixedSIop); 1016 decoder_output += VfpRegRegImmOpConstructor.subst(vcvtFpSFixedSIop); 1017 exec_output += PredOpExecute.subst(vcvtFpSFixedSIop); 1018 1019 vcvtFpSFixedDCode = ''' 1020 IntDoubleUnion cOp1; 1021 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 1022 VfpSavedState state = prepVfpFpscr(Fpscr); 1023 uint64_t mid = vfpFpDToFixed(cOp1.fp, true, false, imm); 1024 Fpscr = setVfpFpscr(Fpscr, state); 1025 FpDestP0.uw = mid; 1026 FpDestP1.uw = mid >> 32; 1027 ''' 1028 vcvtFpSFixedDIop = InstObjParams("vcvt", "VcvtFpSFixedD", "VfpRegRegImmOp", 1029 { "code": vcvtFpSFixedDCode, 1030 "predicate_test": predicateTest }, []) 1031 header_output += VfpRegRegImmOpDeclare.subst(vcvtFpSFixedDIop); 1032 decoder_output += VfpRegRegImmOpConstructor.subst(vcvtFpSFixedDIop); 1033 exec_output += PredOpExecute.subst(vcvtFpSFixedDIop); 1034 1035 vcvtFpUFixedSCode = ''' 1036 VfpSavedState state = prepVfpFpscr(Fpscr); 1037 FpDest.uw = vfpFpSToFixed(FpOp1, false, false, imm); 1038 Fpscr = setVfpFpscr(Fpscr, state); 1039 ''' 1040 vcvtFpUFixedSIop = InstObjParams("vcvt", "VcvtFpUFixedS", "VfpRegRegImmOp", 1041 { "code": vcvtFpUFixedSCode, 1042 "predicate_test": predicateTest }, []) 1043 header_output += VfpRegRegImmOpDeclare.subst(vcvtFpUFixedSIop); 1044 decoder_output += VfpRegRegImmOpConstructor.subst(vcvtFpUFixedSIop); 1045 exec_output += PredOpExecute.subst(vcvtFpUFixedSIop); 1046 1047 vcvtFpUFixedDCode = ''' 1048 IntDoubleUnion cOp1; 1049 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 1050 VfpSavedState state = prepVfpFpscr(Fpscr); 1051 uint64_t mid = vfpFpDToFixed(cOp1.fp, false, false, imm); 1052 Fpscr = setVfpFpscr(Fpscr, state); 1053 FpDestP0.uw = mid; 1054 FpDestP1.uw = mid >> 32; 1055 ''' 1056 vcvtFpUFixedDIop = InstObjParams("vcvt", "VcvtFpUFixedD", "VfpRegRegImmOp", 1057 { "code": vcvtFpUFixedDCode, 1058 "predicate_test": predicateTest }, []) 1059 header_output += VfpRegRegImmOpDeclare.subst(vcvtFpUFixedDIop); 1060 decoder_output += VfpRegRegImmOpConstructor.subst(vcvtFpUFixedDIop); 1061 exec_output += PredOpExecute.subst(vcvtFpUFixedDIop); 1062 1063 vcvtSFixedFpSCode = ''' 1064 VfpSavedState state = prepVfpFpscr(Fpscr); 1065 FpDest = vfpSFixedToFpS(FpOp1.sw, true, imm); 1066 Fpscr = setVfpFpscr(Fpscr, state); 1067 ''' 1068 vcvtSFixedFpSIop = InstObjParams("vcvt", "VcvtSFixedFpS", "VfpRegRegImmOp", 1069 { "code": vcvtSFixedFpSCode, 1070 "predicate_test": predicateTest }, []) 1071 header_output += VfpRegRegImmOpDeclare.subst(vcvtSFixedFpSIop); 1072 decoder_output += VfpRegRegImmOpConstructor.subst(vcvtSFixedFpSIop); 1073 exec_output += PredOpExecute.subst(vcvtSFixedFpSIop); 1074 1075 vcvtSFixedFpDCode = ''' 1076 IntDoubleUnion cDest; 1077 uint64_t mid = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 1078 VfpSavedState state = prepVfpFpscr(Fpscr); 1079 cDest.fp = vfpSFixedToFpD(mid, true, imm); 1080 Fpscr = setVfpFpscr(Fpscr, state); 1081 FpDestP0.uw = cDest.bits; 1082 FpDestP1.uw = cDest.bits >> 32; 1083 ''' 1084 vcvtSFixedFpDIop = InstObjParams("vcvt", "VcvtSFixedFpD", "VfpRegRegImmOp", 1085 { "code": vcvtSFixedFpDCode, 1086 "predicate_test": predicateTest }, []) 1087 header_output += VfpRegRegImmOpDeclare.subst(vcvtSFixedFpDIop); 1088 decoder_output += VfpRegRegImmOpConstructor.subst(vcvtSFixedFpDIop); 1089 exec_output += PredOpExecute.subst(vcvtSFixedFpDIop); 1090 1091 vcvtUFixedFpSCode = ''' 1092 VfpSavedState state = prepVfpFpscr(Fpscr); 1093 FpDest = vfpUFixedToFpS(FpOp1.uw, false, imm); 1094 Fpscr = setVfpFpscr(Fpscr, state); 1095 ''' 1096 vcvtUFixedFpSIop = InstObjParams("vcvt", "VcvtUFixedFpS", "VfpRegRegImmOp", 1097 { "code": vcvtUFixedFpSCode, 1098 "predicate_test": predicateTest }, []) 1099 header_output += VfpRegRegImmOpDeclare.subst(vcvtUFixedFpSIop); 1100 decoder_output += VfpRegRegImmOpConstructor.subst(vcvtUFixedFpSIop); 1101 exec_output += PredOpExecute.subst(vcvtUFixedFpSIop); 1102 1103 vcvtUFixedFpDCode = ''' 1104 IntDoubleUnion cDest; 1105 uint64_t mid = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 1106 VfpSavedState state = prepVfpFpscr(Fpscr); 1107 cDest.fp = vfpUFixedToFpD(mid, false, imm); 1108 Fpscr = setVfpFpscr(Fpscr, state); 1109 FpDestP0.uw = cDest.bits; 1110 FpDestP1.uw = cDest.bits >> 32; 1111 ''' 1112 vcvtUFixedFpDIop = InstObjParams("vcvt", "VcvtUFixedFpD", "VfpRegRegImmOp", 1113 { "code": vcvtUFixedFpDCode, 1114 "predicate_test": predicateTest }, []) 1115 header_output += VfpRegRegImmOpDeclare.subst(vcvtUFixedFpDIop); 1116 decoder_output += VfpRegRegImmOpConstructor.subst(vcvtUFixedFpDIop); 1117 exec_output += PredOpExecute.subst(vcvtUFixedFpDIop); 1118 1119 vcvtFpSHFixedSCode = ''' 1120 VfpSavedState state = prepVfpFpscr(Fpscr); 1121 FpDest.sh = vfpFpSToFixed(FpOp1, true, true, imm); 1122 Fpscr = setVfpFpscr(Fpscr, state); 1123 ''' 1124 vcvtFpSHFixedSIop = InstObjParams("vcvt", "VcvtFpSHFixedS", 1125 "VfpRegRegImmOp", 1126 { "code": vcvtFpSHFixedSCode, 1127 "predicate_test": predicateTest }, []) 1128 header_output += VfpRegRegImmOpDeclare.subst(vcvtFpSHFixedSIop); 1129 decoder_output += VfpRegRegImmOpConstructor.subst(vcvtFpSHFixedSIop); 1130 exec_output += PredOpExecute.subst(vcvtFpSHFixedSIop); 1131 1132 vcvtFpSHFixedDCode = ''' 1133 IntDoubleUnion cOp1; 1134 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 1135 VfpSavedState state = prepVfpFpscr(Fpscr); 1136 uint64_t result = vfpFpDToFixed(cOp1.fp, true, true, imm); 1137 Fpscr = setVfpFpscr(Fpscr, state); 1138 FpDestP0.uw = result; 1139 FpDestP1.uw = result >> 32; 1140 ''' 1141 vcvtFpSHFixedDIop = InstObjParams("vcvt", "VcvtFpSHFixedD", 1142 "VfpRegRegImmOp", 1143 { "code": vcvtFpSHFixedDCode, 1144 "predicate_test": predicateTest }, []) 1145 header_output += VfpRegRegImmOpDeclare.subst(vcvtFpSHFixedDIop); 1146 decoder_output += VfpRegRegImmOpConstructor.subst(vcvtFpSHFixedDIop); 1147 exec_output += PredOpExecute.subst(vcvtFpSHFixedDIop); 1148 1149 vcvtFpUHFixedSCode = ''' 1150 VfpSavedState state = prepVfpFpscr(Fpscr); 1151 FpDest.uh = vfpFpSToFixed(FpOp1, false, true, imm); 1152 Fpscr = setVfpFpscr(Fpscr, state); 1153 ''' 1154 vcvtFpUHFixedSIop = InstObjParams("vcvt", "VcvtFpUHFixedS", 1155 "VfpRegRegImmOp", 1156 { "code": vcvtFpUHFixedSCode, 1157 "predicate_test": predicateTest }, []) 1158 header_output += VfpRegRegImmOpDeclare.subst(vcvtFpUHFixedSIop); 1159 decoder_output += VfpRegRegImmOpConstructor.subst(vcvtFpUHFixedSIop); 1160 exec_output += PredOpExecute.subst(vcvtFpUHFixedSIop); 1161 1162 vcvtFpUHFixedDCode = ''' 1163 IntDoubleUnion cOp1; 1164 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 1165 VfpSavedState state = prepVfpFpscr(Fpscr); 1166 uint64_t mid = vfpFpDToFixed(cOp1.fp, false, true, imm); 1167 Fpscr = setVfpFpscr(Fpscr, state); 1168 FpDestP0.uw = mid; 1169 FpDestP1.uw = mid >> 32; 1170 ''' 1171 vcvtFpUHFixedDIop = InstObjParams("vcvt", "VcvtFpUHFixedD", 1172 "VfpRegRegImmOp", 1173 { "code": vcvtFpUHFixedDCode, 1174 "predicate_test": predicateTest }, []) 1175 header_output += VfpRegRegImmOpDeclare.subst(vcvtFpUHFixedDIop); 1176 decoder_output += VfpRegRegImmOpConstructor.subst(vcvtFpUHFixedDIop); 1177 exec_output += PredOpExecute.subst(vcvtFpUHFixedDIop); 1178 1179 vcvtSHFixedFpSCode = ''' 1180 VfpSavedState state = prepVfpFpscr(Fpscr); 1181 FpDest = vfpSFixedToFpS(FpOp1.sh, true, imm); 1182 Fpscr = setVfpFpscr(Fpscr, state); 1183 ''' 1184 vcvtSHFixedFpSIop = InstObjParams("vcvt", "VcvtSHFixedFpS", 1185 "VfpRegRegImmOp", 1186 { "code": vcvtSHFixedFpSCode, 1187 "predicate_test": predicateTest }, []) 1188 header_output += VfpRegRegImmOpDeclare.subst(vcvtSHFixedFpSIop); 1189 decoder_output += VfpRegRegImmOpConstructor.subst(vcvtSHFixedFpSIop); 1190 exec_output += PredOpExecute.subst(vcvtSHFixedFpSIop); 1191 1192 vcvtSHFixedFpDCode = ''' 1193 IntDoubleUnion cDest; 1194 uint64_t mid = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 1195 VfpSavedState state = prepVfpFpscr(Fpscr); 1196 cDest.fp = vfpSFixedToFpD(mid, true, imm); 1197 Fpscr = setVfpFpscr(Fpscr, state); 1198 FpDestP0.uw = cDest.bits; 1199 FpDestP1.uw = cDest.bits >> 32; 1200 ''' 1201 vcvtSHFixedFpDIop = InstObjParams("vcvt", "VcvtSHFixedFpD", 1202 "VfpRegRegImmOp", 1203 { "code": vcvtSHFixedFpDCode, 1204 "predicate_test": predicateTest }, []) 1205 header_output += VfpRegRegImmOpDeclare.subst(vcvtSHFixedFpDIop); 1206 decoder_output += VfpRegRegImmOpConstructor.subst(vcvtSHFixedFpDIop); 1207 exec_output += PredOpExecute.subst(vcvtSHFixedFpDIop); 1208 1209 vcvtUHFixedFpSCode = ''' 1210 VfpSavedState state = prepVfpFpscr(Fpscr); 1211 FpDest = vfpUFixedToFpS(FpOp1.uh, true, imm); 1212 Fpscr = setVfpFpscr(Fpscr, state); 1213 ''' 1214 vcvtUHFixedFpSIop = InstObjParams("vcvt", "VcvtUHFixedFpS", 1215 "VfpRegRegImmOp", 1216 { "code": vcvtUHFixedFpSCode, 1217 "predicate_test": predicateTest }, []) 1218 header_output += VfpRegRegImmOpDeclare.subst(vcvtUHFixedFpSIop); 1219 decoder_output += VfpRegRegImmOpConstructor.subst(vcvtUHFixedFpSIop); 1220 exec_output += PredOpExecute.subst(vcvtUHFixedFpSIop); 1221 1222 vcvtUHFixedFpDCode = ''' 1223 IntDoubleUnion cDest; 1224 uint64_t mid = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 1225 VfpSavedState state = prepVfpFpscr(Fpscr); 1226 cDest.fp = vfpUFixedToFpD(mid, true, imm); 1227 Fpscr = setVfpFpscr(Fpscr, state); 1228 FpDestP0.uw = cDest.bits; 1229 FpDestP1.uw = cDest.bits >> 32; 1230 ''' 1231 vcvtUHFixedFpDIop = InstObjParams("vcvt", "VcvtUHFixedFpD", 1232 "VfpRegRegImmOp", 1233 { "code": vcvtUHFixedFpDCode, 1234 "predicate_test": predicateTest }, []) 1235 header_output += VfpRegRegImmOpDeclare.subst(vcvtUHFixedFpDIop); 1236 decoder_output += VfpRegRegImmOpConstructor.subst(vcvtUHFixedFpDIop); 1237 exec_output += PredOpExecute.subst(vcvtUHFixedFpDIop); 1238}}; |
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