fp.isa (7377:ce388054b481) fp.isa (7378:de704acd042f)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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371 vmov2Core2RegIop = InstObjParams("vmov", "Vmov2Core2Reg", "VfpRegRegRegOp",
372 { "code": vmov2Core2RegCode,
373 "predicate_test": predicateTest }, [])
374 header_output += VfpRegRegRegOpDeclare.subst(vmov2Core2RegIop);
375 decoder_output += VfpRegRegRegOpConstructor.subst(vmov2Core2RegIop);
376 exec_output += PredOpExecute.subst(vmov2Core2RegIop);
377
378 vmulSCode = '''
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 362 unchanged lines hidden (view full) ---

371 vmov2Core2RegIop = InstObjParams("vmov", "Vmov2Core2Reg", "VfpRegRegRegOp",
372 { "code": vmov2Core2RegCode,
373 "predicate_test": predicateTest }, [])
374 header_output += VfpRegRegRegOpDeclare.subst(vmov2Core2RegIop);
375 decoder_output += VfpRegRegRegOpConstructor.subst(vmov2Core2RegIop);
376 exec_output += PredOpExecute.subst(vmov2Core2RegIop);
377
378 vmulSCode = '''
379 VfpSavedState state = prepVfpFpscr(Fpscr);
379 FpDest = FpOp1 * FpOp2;
380 FpDest = FpOp1 * FpOp2;
381 Fpscr = setVfpFpscr(Fpscr, state);
380 if ((isinf(FpOp1) && FpOp2 == 0) || (isinf(FpOp2) && FpOp1 == 0)) {
381 FpDest = NAN;
382 }
383 '''
384 vmulSIop = InstObjParams("vmuls", "VmulS", "VfpRegRegRegOp",
385 { "code": vmulSCode,
386 "predicate_test": predicateTest }, [])
387 header_output += VfpRegRegRegOpDeclare.subst(vmulSIop);
388 decoder_output += VfpRegRegRegOpConstructor.subst(vmulSIop);
389 exec_output += PredOpExecute.subst(vmulSIop);
390
391 vmulDCode = '''
392 IntDoubleUnion cOp1, cOp2, cDest;
393 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
394 cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32));
382 if ((isinf(FpOp1) && FpOp2 == 0) || (isinf(FpOp2) && FpOp1 == 0)) {
383 FpDest = NAN;
384 }
385 '''
386 vmulSIop = InstObjParams("vmuls", "VmulS", "VfpRegRegRegOp",
387 { "code": vmulSCode,
388 "predicate_test": predicateTest }, [])
389 header_output += VfpRegRegRegOpDeclare.subst(vmulSIop);
390 decoder_output += VfpRegRegRegOpConstructor.subst(vmulSIop);
391 exec_output += PredOpExecute.subst(vmulSIop);
392
393 vmulDCode = '''
394 IntDoubleUnion cOp1, cOp2, cDest;
395 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
396 cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32));
397 VfpSavedState state = prepVfpFpscr(Fpscr);
395 cDest.fp = cOp1.fp * cOp2.fp;
398 cDest.fp = cOp1.fp * cOp2.fp;
399 Fpscr = setVfpFpscr(Fpscr, state);
396 if ((isinf(cOp1.fp) && cOp2.fp == 0) ||
397 (isinf(cOp2.fp) && cOp1.fp == 0)) {
398 cDest.fp = NAN;
399 }
400 FpDestP0.uw = cDest.bits;
401 FpDestP1.uw = cDest.bits >> 32;
402 '''
403 vmulDIop = InstObjParams("vmuld", "VmulD", "VfpRegRegRegOp",

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451 vabsDIop = InstObjParams("vabsd", "VabsD", "VfpRegRegOp",
452 { "code": vabsDCode,
453 "predicate_test": predicateTest }, [])
454 header_output += VfpRegRegOpDeclare.subst(vabsDIop);
455 decoder_output += VfpRegRegOpConstructor.subst(vabsDIop);
456 exec_output += PredOpExecute.subst(vabsDIop);
457
458 vaddSCode = '''
400 if ((isinf(cOp1.fp) && cOp2.fp == 0) ||
401 (isinf(cOp2.fp) && cOp1.fp == 0)) {
402 cDest.fp = NAN;
403 }
404 FpDestP0.uw = cDest.bits;
405 FpDestP1.uw = cDest.bits >> 32;
406 '''
407 vmulDIop = InstObjParams("vmuld", "VmulD", "VfpRegRegRegOp",

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455 vabsDIop = InstObjParams("vabsd", "VabsD", "VfpRegRegOp",
456 { "code": vabsDCode,
457 "predicate_test": predicateTest }, [])
458 header_output += VfpRegRegOpDeclare.subst(vabsDIop);
459 decoder_output += VfpRegRegOpConstructor.subst(vabsDIop);
460 exec_output += PredOpExecute.subst(vabsDIop);
461
462 vaddSCode = '''
463 VfpSavedState state = prepVfpFpscr(Fpscr);
459 FpDest = FpOp1 + FpOp2;
464 FpDest = FpOp1 + FpOp2;
465 Fpscr = setVfpFpscr(Fpscr, state);
460 '''
461 vaddSIop = InstObjParams("vadds", "VaddS", "VfpRegRegRegOp",
462 { "code": vaddSCode,
463 "predicate_test": predicateTest }, [])
464 header_output += VfpRegRegRegOpDeclare.subst(vaddSIop);
465 decoder_output += VfpRegRegRegOpConstructor.subst(vaddSIop);
466 exec_output += PredOpExecute.subst(vaddSIop);
467
468 vaddDCode = '''
469 IntDoubleUnion cOp1, cOp2, cDest;
470 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
471 cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32));
466 '''
467 vaddSIop = InstObjParams("vadds", "VaddS", "VfpRegRegRegOp",
468 { "code": vaddSCode,
469 "predicate_test": predicateTest }, [])
470 header_output += VfpRegRegRegOpDeclare.subst(vaddSIop);
471 decoder_output += VfpRegRegRegOpConstructor.subst(vaddSIop);
472 exec_output += PredOpExecute.subst(vaddSIop);
473
474 vaddDCode = '''
475 IntDoubleUnion cOp1, cOp2, cDest;
476 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
477 cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32));
478 VfpSavedState state = prepVfpFpscr(Fpscr);
472 cDest.fp = cOp1.fp + cOp2.fp;
479 cDest.fp = cOp1.fp + cOp2.fp;
480 Fpscr = setVfpFpscr(Fpscr, state);
473 FpDestP0.uw = cDest.bits;
474 FpDestP1.uw = cDest.bits >> 32;
475 '''
476 vaddDIop = InstObjParams("vaddd", "VaddD", "VfpRegRegRegOp",
477 { "code": vaddDCode,
478 "predicate_test": predicateTest }, [])
479 header_output += VfpRegRegRegOpDeclare.subst(vaddDIop);
480 decoder_output += VfpRegRegRegOpConstructor.subst(vaddDIop);
481 exec_output += PredOpExecute.subst(vaddDIop);
482
483 vsubSCode = '''
481 FpDestP0.uw = cDest.bits;
482 FpDestP1.uw = cDest.bits >> 32;
483 '''
484 vaddDIop = InstObjParams("vaddd", "VaddD", "VfpRegRegRegOp",
485 { "code": vaddDCode,
486 "predicate_test": predicateTest }, [])
487 header_output += VfpRegRegRegOpDeclare.subst(vaddDIop);
488 decoder_output += VfpRegRegRegOpConstructor.subst(vaddDIop);
489 exec_output += PredOpExecute.subst(vaddDIop);
490
491 vsubSCode = '''
492 VfpSavedState state = prepVfpFpscr(Fpscr);
484 FpDest = FpOp1 - FpOp2;
493 FpDest = FpOp1 - FpOp2;
494 Fpscr = setVfpFpscr(Fpscr, state)
485 '''
486 vsubSIop = InstObjParams("vsubs", "VsubS", "VfpRegRegRegOp",
487 { "code": vsubSCode,
488 "predicate_test": predicateTest }, [])
489 header_output += VfpRegRegRegOpDeclare.subst(vsubSIop);
490 decoder_output += VfpRegRegRegOpConstructor.subst(vsubSIop);
491 exec_output += PredOpExecute.subst(vsubSIop);
492
493 vsubDCode = '''
494 IntDoubleUnion cOp1, cOp2, cDest;
495 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
496 cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32));
495 '''
496 vsubSIop = InstObjParams("vsubs", "VsubS", "VfpRegRegRegOp",
497 { "code": vsubSCode,
498 "predicate_test": predicateTest }, [])
499 header_output += VfpRegRegRegOpDeclare.subst(vsubSIop);
500 decoder_output += VfpRegRegRegOpConstructor.subst(vsubSIop);
501 exec_output += PredOpExecute.subst(vsubSIop);
502
503 vsubDCode = '''
504 IntDoubleUnion cOp1, cOp2, cDest;
505 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
506 cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32));
507 VfpSavedState state = prepVfpFpscr(Fpscr);
497 cDest.fp = cOp1.fp - cOp2.fp;
508 cDest.fp = cOp1.fp - cOp2.fp;
509 Fpscr = setVfpFpscr(Fpscr, state);
498 FpDestP0.uw = cDest.bits;
499 FpDestP1.uw = cDest.bits >> 32;
500 '''
501 vsubDIop = InstObjParams("vsubd", "VsubD", "VfpRegRegRegOp",
502 { "code": vsubDCode,
503 "predicate_test": predicateTest }, [])
504 header_output += VfpRegRegRegOpDeclare.subst(vsubDIop);
505 decoder_output += VfpRegRegRegOpConstructor.subst(vsubDIop);
506 exec_output += PredOpExecute.subst(vsubDIop);
507
508 vdivSCode = '''
510 FpDestP0.uw = cDest.bits;
511 FpDestP1.uw = cDest.bits >> 32;
512 '''
513 vsubDIop = InstObjParams("vsubd", "VsubD", "VfpRegRegRegOp",
514 { "code": vsubDCode,
515 "predicate_test": predicateTest }, [])
516 header_output += VfpRegRegRegOpDeclare.subst(vsubDIop);
517 decoder_output += VfpRegRegRegOpConstructor.subst(vsubDIop);
518 exec_output += PredOpExecute.subst(vsubDIop);
519
520 vdivSCode = '''
521 VfpSavedState state = prepVfpFpscr(Fpscr);
509 FpDest = FpOp1 / FpOp2;
522 FpDest = FpOp1 / FpOp2;
523 Fpscr = setVfpFpscr(Fpscr, state);
510 '''
511 vdivSIop = InstObjParams("vdivs", "VdivS", "VfpRegRegRegOp",
512 { "code": vdivSCode,
513 "predicate_test": predicateTest }, [])
514 header_output += VfpRegRegRegOpDeclare.subst(vdivSIop);
515 decoder_output += VfpRegRegRegOpConstructor.subst(vdivSIop);
516 exec_output += PredOpExecute.subst(vdivSIop);
517
518 vdivDCode = '''
519 IntDoubleUnion cOp1, cOp2, cDest;
520 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
521 cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32));
524 '''
525 vdivSIop = InstObjParams("vdivs", "VdivS", "VfpRegRegRegOp",
526 { "code": vdivSCode,
527 "predicate_test": predicateTest }, [])
528 header_output += VfpRegRegRegOpDeclare.subst(vdivSIop);
529 decoder_output += VfpRegRegRegOpConstructor.subst(vdivSIop);
530 exec_output += PredOpExecute.subst(vdivSIop);
531
532 vdivDCode = '''
533 IntDoubleUnion cOp1, cOp2, cDest;
534 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
535 cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32));
536 VfpSavedState state = prepVfpFpscr(Fpscr);
522 cDest.fp = cOp1.fp / cOp2.fp;
537 cDest.fp = cOp1.fp / cOp2.fp;
538 Fpscr = setVfpFpscr(Fpscr, state);
523 FpDestP0.uw = cDest.bits;
524 FpDestP1.uw = cDest.bits >> 32;
525 '''
526 vdivDIop = InstObjParams("vdivd", "VdivD", "VfpRegRegRegOp",
527 { "code": vdivDCode,
528 "predicate_test": predicateTest }, [])
529 header_output += VfpRegRegRegOpDeclare.subst(vdivDIop);
530 decoder_output += VfpRegRegRegOpConstructor.subst(vdivDIop);
531 exec_output += PredOpExecute.subst(vdivDIop);
532
533 vsqrtSCode = '''
539 FpDestP0.uw = cDest.bits;
540 FpDestP1.uw = cDest.bits >> 32;
541 '''
542 vdivDIop = InstObjParams("vdivd", "VdivD", "VfpRegRegRegOp",
543 { "code": vdivDCode,
544 "predicate_test": predicateTest }, [])
545 header_output += VfpRegRegRegOpDeclare.subst(vdivDIop);
546 decoder_output += VfpRegRegRegOpConstructor.subst(vdivDIop);
547 exec_output += PredOpExecute.subst(vdivDIop);
548
549 vsqrtSCode = '''
550 VfpSavedState state = prepVfpFpscr(Fpscr);
534 FpDest = sqrtf(FpOp1);
551 FpDest = sqrtf(FpOp1);
552 Fpscr = setVfpFpscr(Fpscr, state);
535 if (FpOp1 < 0) {
536 FpDest = NAN;
537 }
538 '''
539 vsqrtSIop = InstObjParams("vsqrts", "VsqrtS", "VfpRegRegOp",
540 { "code": vsqrtSCode,
541 "predicate_test": predicateTest }, [])
542 header_output += VfpRegRegOpDeclare.subst(vsqrtSIop);
543 decoder_output += VfpRegRegOpConstructor.subst(vsqrtSIop);
544 exec_output += PredOpExecute.subst(vsqrtSIop);
545
546 vsqrtDCode = '''
547 IntDoubleUnion cOp1, cDest;
548 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
553 if (FpOp1 < 0) {
554 FpDest = NAN;
555 }
556 '''
557 vsqrtSIop = InstObjParams("vsqrts", "VsqrtS", "VfpRegRegOp",
558 { "code": vsqrtSCode,
559 "predicate_test": predicateTest }, [])
560 header_output += VfpRegRegOpDeclare.subst(vsqrtSIop);
561 decoder_output += VfpRegRegOpConstructor.subst(vsqrtSIop);
562 exec_output += PredOpExecute.subst(vsqrtSIop);
563
564 vsqrtDCode = '''
565 IntDoubleUnion cOp1, cDest;
566 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
567 VfpSavedState state = prepVfpFpscr(Fpscr);
549 cDest.fp = sqrt(cOp1.fp);
568 cDest.fp = sqrt(cOp1.fp);
569 Fpscr = setVfpFpscr(Fpscr, state);
550 if (cOp1.fp < 0) {
551 cDest.fp = NAN;
552 }
553 FpDestP0.uw = cDest.bits;
554 FpDestP1.uw = cDest.bits >> 32;
555 '''
556 vsqrtDIop = InstObjParams("vsqrtd", "VsqrtD", "VfpRegRegOp",
557 { "code": vsqrtDCode,
558 "predicate_test": predicateTest }, [])
559 header_output += VfpRegRegOpDeclare.subst(vsqrtDIop);
560 decoder_output += VfpRegRegOpConstructor.subst(vsqrtDIop);
561 exec_output += PredOpExecute.subst(vsqrtDIop);
562
563 vmlaSCode = '''
570 if (cOp1.fp < 0) {
571 cDest.fp = NAN;
572 }
573 FpDestP0.uw = cDest.bits;
574 FpDestP1.uw = cDest.bits >> 32;
575 '''
576 vsqrtDIop = InstObjParams("vsqrtd", "VsqrtD", "VfpRegRegOp",
577 { "code": vsqrtDCode,
578 "predicate_test": predicateTest }, [])
579 header_output += VfpRegRegOpDeclare.subst(vsqrtDIop);
580 decoder_output += VfpRegRegOpConstructor.subst(vsqrtDIop);
581 exec_output += PredOpExecute.subst(vsqrtDIop);
582
583 vmlaSCode = '''
584 VfpSavedState state = prepVfpFpscr(Fpscr);
564 float mid = FpOp1 * FpOp2;
565 if ((isinf(FpOp1) && FpOp2 == 0) || (isinf(FpOp2) && FpOp1 == 0)) {
566 mid = NAN;
567 }
568 FpDest = FpDest + mid;
585 float mid = FpOp1 * FpOp2;
586 if ((isinf(FpOp1) && FpOp2 == 0) || (isinf(FpOp2) && FpOp1 == 0)) {
587 mid = NAN;
588 }
589 FpDest = FpDest + mid;
590 Fpscr = setVfpFpscr(Fpscr, state);
569 '''
570 vmlaSIop = InstObjParams("vmlas", "VmlaS", "VfpRegRegRegOp",
571 { "code": vmlaSCode,
572 "predicate_test": predicateTest }, [])
573 header_output += VfpRegRegRegOpDeclare.subst(vmlaSIop);
574 decoder_output += VfpRegRegRegOpConstructor.subst(vmlaSIop);
575 exec_output += PredOpExecute.subst(vmlaSIop);
576
577 vmlaDCode = '''
578 IntDoubleUnion cOp1, cOp2, cDest;
579 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
580 cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32));
581 cDest.bits = ((uint64_t)FpDestP0.uw | ((uint64_t)FpDestP1.uw << 32));
591 '''
592 vmlaSIop = InstObjParams("vmlas", "VmlaS", "VfpRegRegRegOp",
593 { "code": vmlaSCode,
594 "predicate_test": predicateTest }, [])
595 header_output += VfpRegRegRegOpDeclare.subst(vmlaSIop);
596 decoder_output += VfpRegRegRegOpConstructor.subst(vmlaSIop);
597 exec_output += PredOpExecute.subst(vmlaSIop);
598
599 vmlaDCode = '''
600 IntDoubleUnion cOp1, cOp2, cDest;
601 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
602 cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32));
603 cDest.bits = ((uint64_t)FpDestP0.uw | ((uint64_t)FpDestP1.uw << 32));
604 VfpSavedState state = prepVfpFpscr(Fpscr);
582 double mid = cOp1.fp * cOp2.fp;
583 if ((isinf(cOp1.fp) && cOp2.fp == 0) ||
584 (isinf(cOp2.fp) && cOp1.fp == 0)) {
585 mid = NAN;
586 }
587 cDest.fp = cDest.fp + mid;
605 double mid = cOp1.fp * cOp2.fp;
606 if ((isinf(cOp1.fp) && cOp2.fp == 0) ||
607 (isinf(cOp2.fp) && cOp1.fp == 0)) {
608 mid = NAN;
609 }
610 cDest.fp = cDest.fp + mid;
611 Fpscr = setVfpFpscr(Fpscr, state);
588 FpDestP0.uw = cDest.bits;
589 FpDestP1.uw = cDest.bits >> 32;
590 '''
591 vmlaDIop = InstObjParams("vmlad", "VmlaD", "VfpRegRegRegOp",
592 { "code": vmlaDCode,
593 "predicate_test": predicateTest }, [])
594 header_output += VfpRegRegRegOpDeclare.subst(vmlaDIop);
595 decoder_output += VfpRegRegRegOpConstructor.subst(vmlaDIop);
596 exec_output += PredOpExecute.subst(vmlaDIop);
597
598 vmlsSCode = '''
612 FpDestP0.uw = cDest.bits;
613 FpDestP1.uw = cDest.bits >> 32;
614 '''
615 vmlaDIop = InstObjParams("vmlad", "VmlaD", "VfpRegRegRegOp",
616 { "code": vmlaDCode,
617 "predicate_test": predicateTest }, [])
618 header_output += VfpRegRegRegOpDeclare.subst(vmlaDIop);
619 decoder_output += VfpRegRegRegOpConstructor.subst(vmlaDIop);
620 exec_output += PredOpExecute.subst(vmlaDIop);
621
622 vmlsSCode = '''
623 VfpSavedState state = prepVfpFpscr(Fpscr);
599 float mid = FpOp1 * FpOp2;
600 if ((isinf(FpOp1) && FpOp2 == 0) || (isinf(FpOp2) && FpOp1 == 0)) {
601 mid = NAN;
602 }
603 FpDest = FpDest - mid;
624 float mid = FpOp1 * FpOp2;
625 if ((isinf(FpOp1) && FpOp2 == 0) || (isinf(FpOp2) && FpOp1 == 0)) {
626 mid = NAN;
627 }
628 FpDest = FpDest - mid;
629 Fpscr = setVfpFpscr(Fpscr, state);
604 '''
605 vmlsSIop = InstObjParams("vmlss", "VmlsS", "VfpRegRegRegOp",
606 { "code": vmlsSCode,
607 "predicate_test": predicateTest }, [])
608 header_output += VfpRegRegRegOpDeclare.subst(vmlsSIop);
609 decoder_output += VfpRegRegRegOpConstructor.subst(vmlsSIop);
610 exec_output += PredOpExecute.subst(vmlsSIop);
611
612 vmlsDCode = '''
613 IntDoubleUnion cOp1, cOp2, cDest;
614 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
615 cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32));
616 cDest.bits = ((uint64_t)FpDestP0.uw | ((uint64_t)FpDestP1.uw << 32));
630 '''
631 vmlsSIop = InstObjParams("vmlss", "VmlsS", "VfpRegRegRegOp",
632 { "code": vmlsSCode,
633 "predicate_test": predicateTest }, [])
634 header_output += VfpRegRegRegOpDeclare.subst(vmlsSIop);
635 decoder_output += VfpRegRegRegOpConstructor.subst(vmlsSIop);
636 exec_output += PredOpExecute.subst(vmlsSIop);
637
638 vmlsDCode = '''
639 IntDoubleUnion cOp1, cOp2, cDest;
640 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
641 cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32));
642 cDest.bits = ((uint64_t)FpDestP0.uw | ((uint64_t)FpDestP1.uw << 32));
643 VfpSavedState state = prepVfpFpscr(Fpscr);
617 double mid = cOp1.fp * cOp2.fp;
618 if ((isinf(cOp1.fp) && cOp2.fp == 0) ||
619 (isinf(cOp2.fp) && cOp1.fp == 0)) {
620 mid = NAN;
621 }
622 cDest.fp = cDest.fp - mid;
644 double mid = cOp1.fp * cOp2.fp;
645 if ((isinf(cOp1.fp) && cOp2.fp == 0) ||
646 (isinf(cOp2.fp) && cOp1.fp == 0)) {
647 mid = NAN;
648 }
649 cDest.fp = cDest.fp - mid;
650 Fpscr = setVfpFpscr(Fpscr, state);
623 FpDestP0.uw = cDest.bits;
624 FpDestP1.uw = cDest.bits >> 32;
625 '''
626 vmlsDIop = InstObjParams("vmlsd", "VmlsD", "VfpRegRegRegOp",
627 { "code": vmlsDCode,
628 "predicate_test": predicateTest }, [])
629 header_output += VfpRegRegRegOpDeclare.subst(vmlsDIop);
630 decoder_output += VfpRegRegRegOpConstructor.subst(vmlsDIop);
631 exec_output += PredOpExecute.subst(vmlsDIop);
632
633 vnmlaSCode = '''
651 FpDestP0.uw = cDest.bits;
652 FpDestP1.uw = cDest.bits >> 32;
653 '''
654 vmlsDIop = InstObjParams("vmlsd", "VmlsD", "VfpRegRegRegOp",
655 { "code": vmlsDCode,
656 "predicate_test": predicateTest }, [])
657 header_output += VfpRegRegRegOpDeclare.subst(vmlsDIop);
658 decoder_output += VfpRegRegRegOpConstructor.subst(vmlsDIop);
659 exec_output += PredOpExecute.subst(vmlsDIop);
660
661 vnmlaSCode = '''
662 VfpSavedState state = prepVfpFpscr(Fpscr);
634 float mid = FpOp1 * FpOp2;
635 if ((isinf(FpOp1) && FpOp2 == 0) || (isinf(FpOp2) && FpOp1 == 0)) {
636 mid = NAN;
637 }
638 FpDest = -FpDest - mid;
663 float mid = FpOp1 * FpOp2;
664 if ((isinf(FpOp1) && FpOp2 == 0) || (isinf(FpOp2) && FpOp1 == 0)) {
665 mid = NAN;
666 }
667 FpDest = -FpDest - mid;
668 Fpscr = setVfpFpscr(Fpscr, state);
639 '''
640 vnmlaSIop = InstObjParams("vnmlas", "VnmlaS", "VfpRegRegRegOp",
641 { "code": vnmlaSCode,
642 "predicate_test": predicateTest }, [])
643 header_output += VfpRegRegRegOpDeclare.subst(vnmlaSIop);
644 decoder_output += VfpRegRegRegOpConstructor.subst(vnmlaSIop);
645 exec_output += PredOpExecute.subst(vnmlaSIop);
646
647 vnmlaDCode = '''
648 IntDoubleUnion cOp1, cOp2, cDest;
649 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
650 cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32));
651 cDest.bits = ((uint64_t)FpDestP0.uw | ((uint64_t)FpDestP1.uw << 32));
669 '''
670 vnmlaSIop = InstObjParams("vnmlas", "VnmlaS", "VfpRegRegRegOp",
671 { "code": vnmlaSCode,
672 "predicate_test": predicateTest }, [])
673 header_output += VfpRegRegRegOpDeclare.subst(vnmlaSIop);
674 decoder_output += VfpRegRegRegOpConstructor.subst(vnmlaSIop);
675 exec_output += PredOpExecute.subst(vnmlaSIop);
676
677 vnmlaDCode = '''
678 IntDoubleUnion cOp1, cOp2, cDest;
679 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
680 cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32));
681 cDest.bits = ((uint64_t)FpDestP0.uw | ((uint64_t)FpDestP1.uw << 32));
682 VfpSavedState state = prepVfpFpscr(Fpscr);
652 double mid = cOp1.fp * cOp2.fp;
653 if ((isinf(cOp1.fp) && cOp2.fp == 0) ||
654 (isinf(cOp2.fp) && cOp1.fp == 0)) {
655 mid = NAN;
656 }
657 cDest.fp = -cDest.fp - mid;
683 double mid = cOp1.fp * cOp2.fp;
684 if ((isinf(cOp1.fp) && cOp2.fp == 0) ||
685 (isinf(cOp2.fp) && cOp1.fp == 0)) {
686 mid = NAN;
687 }
688 cDest.fp = -cDest.fp - mid;
689 Fpscr = setVfpFpscr(Fpscr, state);
658 FpDestP0.uw = cDest.bits;
659 FpDestP1.uw = cDest.bits >> 32;
660 '''
661 vnmlaDIop = InstObjParams("vnmlad", "VnmlaD", "VfpRegRegRegOp",
662 { "code": vnmlaDCode,
663 "predicate_test": predicateTest }, [])
664 header_output += VfpRegRegRegOpDeclare.subst(vnmlaDIop);
665 decoder_output += VfpRegRegRegOpConstructor.subst(vnmlaDIop);
666 exec_output += PredOpExecute.subst(vnmlaDIop);
667
668 vnmlsSCode = '''
690 FpDestP0.uw = cDest.bits;
691 FpDestP1.uw = cDest.bits >> 32;
692 '''
693 vnmlaDIop = InstObjParams("vnmlad", "VnmlaD", "VfpRegRegRegOp",
694 { "code": vnmlaDCode,
695 "predicate_test": predicateTest }, [])
696 header_output += VfpRegRegRegOpDeclare.subst(vnmlaDIop);
697 decoder_output += VfpRegRegRegOpConstructor.subst(vnmlaDIop);
698 exec_output += PredOpExecute.subst(vnmlaDIop);
699
700 vnmlsSCode = '''
701 VfpSavedState state = prepVfpFpscr(Fpscr);
669 float mid = FpOp1 * FpOp2;
670 if ((isinf(FpOp1) && FpOp2 == 0) || (isinf(FpOp2) && FpOp1 == 0)) {
671 mid = NAN;
672 }
673 FpDest = -FpDest + mid;
702 float mid = FpOp1 * FpOp2;
703 if ((isinf(FpOp1) && FpOp2 == 0) || (isinf(FpOp2) && FpOp1 == 0)) {
704 mid = NAN;
705 }
706 FpDest = -FpDest + mid;
707 Fpscr = setVfpFpscr(Fpscr, state);
674 '''
675 vnmlsSIop = InstObjParams("vnmlss", "VnmlsS", "VfpRegRegRegOp",
676 { "code": vnmlsSCode,
677 "predicate_test": predicateTest }, [])
678 header_output += VfpRegRegRegOpDeclare.subst(vnmlsSIop);
679 decoder_output += VfpRegRegRegOpConstructor.subst(vnmlsSIop);
680 exec_output += PredOpExecute.subst(vnmlsSIop);
681
682 vnmlsDCode = '''
683 IntDoubleUnion cOp1, cOp2, cDest;
684 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
685 cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32));
686 cDest.bits = ((uint64_t)FpDestP0.uw | ((uint64_t)FpDestP1.uw << 32));
708 '''
709 vnmlsSIop = InstObjParams("vnmlss", "VnmlsS", "VfpRegRegRegOp",
710 { "code": vnmlsSCode,
711 "predicate_test": predicateTest }, [])
712 header_output += VfpRegRegRegOpDeclare.subst(vnmlsSIop);
713 decoder_output += VfpRegRegRegOpConstructor.subst(vnmlsSIop);
714 exec_output += PredOpExecute.subst(vnmlsSIop);
715
716 vnmlsDCode = '''
717 IntDoubleUnion cOp1, cOp2, cDest;
718 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
719 cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32));
720 cDest.bits = ((uint64_t)FpDestP0.uw | ((uint64_t)FpDestP1.uw << 32));
721 VfpSavedState state = prepVfpFpscr(Fpscr);
687 double mid = cOp1.fp * cOp2.fp;
688 if ((isinf(cOp1.fp) && cOp2.fp == 0) ||
689 (isinf(cOp2.fp) && cOp1.fp == 0)) {
690 mid = NAN;
691 }
692 cDest.fp = -cDest.fp + mid;
722 double mid = cOp1.fp * cOp2.fp;
723 if ((isinf(cOp1.fp) && cOp2.fp == 0) ||
724 (isinf(cOp2.fp) && cOp1.fp == 0)) {
725 mid = NAN;
726 }
727 cDest.fp = -cDest.fp + mid;
728 Fpscr = setVfpFpscr(Fpscr, state);
693 FpDestP0.uw = cDest.bits;
694 FpDestP1.uw = cDest.bits >> 32;
695 '''
696 vnmlsDIop = InstObjParams("vnmlsd", "VnmlsD", "VfpRegRegRegOp",
697 { "code": vnmlsDCode,
698 "predicate_test": predicateTest }, [])
699 header_output += VfpRegRegRegOpDeclare.subst(vnmlsDIop);
700 decoder_output += VfpRegRegRegOpConstructor.subst(vnmlsDIop);
701 exec_output += PredOpExecute.subst(vnmlsDIop);
702
703 vnmulSCode = '''
729 FpDestP0.uw = cDest.bits;
730 FpDestP1.uw = cDest.bits >> 32;
731 '''
732 vnmlsDIop = InstObjParams("vnmlsd", "VnmlsD", "VfpRegRegRegOp",
733 { "code": vnmlsDCode,
734 "predicate_test": predicateTest }, [])
735 header_output += VfpRegRegRegOpDeclare.subst(vnmlsDIop);
736 decoder_output += VfpRegRegRegOpConstructor.subst(vnmlsDIop);
737 exec_output += PredOpExecute.subst(vnmlsDIop);
738
739 vnmulSCode = '''
740 VfpSavedState state = prepVfpFpscr(Fpscr);
704 float mid = FpOp1 * FpOp2;
705 if ((isinf(FpOp1) && FpOp2 == 0) || (isinf(FpOp2) && FpOp1 == 0)) {
706 mid = NAN;
707 }
708 FpDest = -mid;
741 float mid = FpOp1 * FpOp2;
742 if ((isinf(FpOp1) && FpOp2 == 0) || (isinf(FpOp2) && FpOp1 == 0)) {
743 mid = NAN;
744 }
745 FpDest = -mid;
746 Fpscr = setVfpFpscr(Fpscr, state);
709 '''
710 vnmulSIop = InstObjParams("vnmuls", "VnmulS", "VfpRegRegRegOp",
711 { "code": vnmulSCode,
712 "predicate_test": predicateTest }, [])
713 header_output += VfpRegRegRegOpDeclare.subst(vnmulSIop);
714 decoder_output += VfpRegRegRegOpConstructor.subst(vnmulSIop);
715 exec_output += PredOpExecute.subst(vnmulSIop);
716
717 vnmulDCode = '''
718 IntDoubleUnion cOp1, cOp2, cDest;
719 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
720 cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32));
721 cDest.bits = ((uint64_t)FpDestP0.uw | ((uint64_t)FpDestP1.uw << 32));
747 '''
748 vnmulSIop = InstObjParams("vnmuls", "VnmulS", "VfpRegRegRegOp",
749 { "code": vnmulSCode,
750 "predicate_test": predicateTest }, [])
751 header_output += VfpRegRegRegOpDeclare.subst(vnmulSIop);
752 decoder_output += VfpRegRegRegOpConstructor.subst(vnmulSIop);
753 exec_output += PredOpExecute.subst(vnmulSIop);
754
755 vnmulDCode = '''
756 IntDoubleUnion cOp1, cOp2, cDest;
757 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
758 cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32));
759 cDest.bits = ((uint64_t)FpDestP0.uw | ((uint64_t)FpDestP1.uw << 32));
760 VfpSavedState state = prepVfpFpscr(Fpscr);
722 double mid = cOp1.fp * cOp2.fp;
723 if ((isinf(cOp1.fp) && cOp2.fp == 0) ||
724 (isinf(cOp2.fp) && cOp1.fp == 0)) {
725 mid = NAN;
726 }
727 cDest.fp = -mid;
761 double mid = cOp1.fp * cOp2.fp;
762 if ((isinf(cOp1.fp) && cOp2.fp == 0) ||
763 (isinf(cOp2.fp) && cOp1.fp == 0)) {
764 mid = NAN;
765 }
766 cDest.fp = -mid;
767 Fpscr = setVfpFpscr(Fpscr, state);
728 FpDestP0.uw = cDest.bits;
729 FpDestP1.uw = cDest.bits >> 32;
730 '''
731 vnmulDIop = InstObjParams("vnmuld", "VnmulD", "VfpRegRegRegOp",
732 { "code": vnmulDCode,
733 "predicate_test": predicateTest }, [])
734 header_output += VfpRegRegRegOpDeclare.subst(vnmulDIop);
735 decoder_output += VfpRegRegRegOpConstructor.subst(vnmulDIop);
736 exec_output += PredOpExecute.subst(vnmulDIop);
737
738 vcvtUIntFpSCode = '''
768 FpDestP0.uw = cDest.bits;
769 FpDestP1.uw = cDest.bits >> 32;
770 '''
771 vnmulDIop = InstObjParams("vnmuld", "VnmulD", "VfpRegRegRegOp",
772 { "code": vnmulDCode,
773 "predicate_test": predicateTest }, [])
774 header_output += VfpRegRegRegOpDeclare.subst(vnmulDIop);
775 decoder_output += VfpRegRegRegOpConstructor.subst(vnmulDIop);
776 exec_output += PredOpExecute.subst(vnmulDIop);
777
778 vcvtUIntFpSCode = '''
779 VfpSavedState state = prepVfpFpscr(Fpscr);
739 FpDest = FpOp1.uw;
780 FpDest = FpOp1.uw;
781 Fpscr = setVfpFpscr(Fpscr, state);
740 '''
741 vcvtUIntFpSIop = InstObjParams("vcvt", "VcvtUIntFpS", "VfpRegRegOp",
742 { "code": vcvtUIntFpSCode,
743 "predicate_test": predicateTest }, [])
744 header_output += VfpRegRegOpDeclare.subst(vcvtUIntFpSIop);
745 decoder_output += VfpRegRegOpConstructor.subst(vcvtUIntFpSIop);
746 exec_output += PredOpExecute.subst(vcvtUIntFpSIop);
747
748 vcvtUIntFpDCode = '''
749 IntDoubleUnion cDest;
782 '''
783 vcvtUIntFpSIop = InstObjParams("vcvt", "VcvtUIntFpS", "VfpRegRegOp",
784 { "code": vcvtUIntFpSCode,
785 "predicate_test": predicateTest }, [])
786 header_output += VfpRegRegOpDeclare.subst(vcvtUIntFpSIop);
787 decoder_output += VfpRegRegOpConstructor.subst(vcvtUIntFpSIop);
788 exec_output += PredOpExecute.subst(vcvtUIntFpSIop);
789
790 vcvtUIntFpDCode = '''
791 IntDoubleUnion cDest;
792 VfpSavedState state = prepVfpFpscr(Fpscr);
750 cDest.fp = (uint64_t)FpOp1P0.uw;
793 cDest.fp = (uint64_t)FpOp1P0.uw;
794 Fpscr = setVfpFpscr(Fpscr, state);
751 FpDestP0.uw = cDest.bits;
752 FpDestP1.uw = cDest.bits >> 32;
753 '''
754 vcvtUIntFpDIop = InstObjParams("vcvt", "VcvtUIntFpD", "VfpRegRegOp",
755 { "code": vcvtUIntFpDCode,
756 "predicate_test": predicateTest }, [])
757 header_output += VfpRegRegOpDeclare.subst(vcvtUIntFpDIop);
758 decoder_output += VfpRegRegOpConstructor.subst(vcvtUIntFpDIop);
759 exec_output += PredOpExecute.subst(vcvtUIntFpDIop);
760
761 vcvtSIntFpSCode = '''
795 FpDestP0.uw = cDest.bits;
796 FpDestP1.uw = cDest.bits >> 32;
797 '''
798 vcvtUIntFpDIop = InstObjParams("vcvt", "VcvtUIntFpD", "VfpRegRegOp",
799 { "code": vcvtUIntFpDCode,
800 "predicate_test": predicateTest }, [])
801 header_output += VfpRegRegOpDeclare.subst(vcvtUIntFpDIop);
802 decoder_output += VfpRegRegOpConstructor.subst(vcvtUIntFpDIop);
803 exec_output += PredOpExecute.subst(vcvtUIntFpDIop);
804
805 vcvtSIntFpSCode = '''
806 VfpSavedState state = prepVfpFpscr(Fpscr);
762 FpDest = FpOp1.sw;
807 FpDest = FpOp1.sw;
808 Fpscr = setVfpFpscr(Fpscr, state);
763 '''
764 vcvtSIntFpSIop = InstObjParams("vcvt", "VcvtSIntFpS", "VfpRegRegOp",
765 { "code": vcvtSIntFpSCode,
766 "predicate_test": predicateTest }, [])
767 header_output += VfpRegRegOpDeclare.subst(vcvtSIntFpSIop);
768 decoder_output += VfpRegRegOpConstructor.subst(vcvtSIntFpSIop);
769 exec_output += PredOpExecute.subst(vcvtSIntFpSIop);
770
771 vcvtSIntFpDCode = '''
772 IntDoubleUnion cDest;
809 '''
810 vcvtSIntFpSIop = InstObjParams("vcvt", "VcvtSIntFpS", "VfpRegRegOp",
811 { "code": vcvtSIntFpSCode,
812 "predicate_test": predicateTest }, [])
813 header_output += VfpRegRegOpDeclare.subst(vcvtSIntFpSIop);
814 decoder_output += VfpRegRegOpConstructor.subst(vcvtSIntFpSIop);
815 exec_output += PredOpExecute.subst(vcvtSIntFpSIop);
816
817 vcvtSIntFpDCode = '''
818 IntDoubleUnion cDest;
819 VfpSavedState state = prepVfpFpscr(Fpscr);
773 cDest.fp = FpOp1P0.sw;
820 cDest.fp = FpOp1P0.sw;
821 Fpscr = setVfpFpscr(Fpscr, state);
774 FpDestP0.uw = cDest.bits;
775 FpDestP1.uw = cDest.bits >> 32;
776 '''
777 vcvtSIntFpDIop = InstObjParams("vcvt", "VcvtSIntFpD", "VfpRegRegOp",
778 { "code": vcvtSIntFpDCode,
779 "predicate_test": predicateTest }, [])
780 header_output += VfpRegRegOpDeclare.subst(vcvtSIntFpDIop);
781 decoder_output += VfpRegRegOpConstructor.subst(vcvtSIntFpDIop);
782 exec_output += PredOpExecute.subst(vcvtSIntFpDIop);
783
784 vcvtFpUIntSCode = '''
822 FpDestP0.uw = cDest.bits;
823 FpDestP1.uw = cDest.bits >> 32;
824 '''
825 vcvtSIntFpDIop = InstObjParams("vcvt", "VcvtSIntFpD", "VfpRegRegOp",
826 { "code": vcvtSIntFpDCode,
827 "predicate_test": predicateTest }, [])
828 header_output += VfpRegRegOpDeclare.subst(vcvtSIntFpDIop);
829 decoder_output += VfpRegRegOpConstructor.subst(vcvtSIntFpDIop);
830 exec_output += PredOpExecute.subst(vcvtSIntFpDIop);
831
832 vcvtFpUIntSCode = '''
833 VfpSavedState state = prepVfpFpscr(Fpscr);
785 FpDest.uw = FpOp1;
834 FpDest.uw = FpOp1;
835 Fpscr = setVfpFpscr(Fpscr, state);
786 '''
787 vcvtFpUIntSIop = InstObjParams("vcvt", "VcvtFpUIntS", "VfpRegRegOp",
788 { "code": vcvtFpUIntSCode,
789 "predicate_test": predicateTest }, [])
790 header_output += VfpRegRegOpDeclare.subst(vcvtFpUIntSIop);
791 decoder_output += VfpRegRegOpConstructor.subst(vcvtFpUIntSIop);
792 exec_output += PredOpExecute.subst(vcvtFpUIntSIop);
793
794 vcvtFpUIntDCode = '''
795 IntDoubleUnion cOp1;
796 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
836 '''
837 vcvtFpUIntSIop = InstObjParams("vcvt", "VcvtFpUIntS", "VfpRegRegOp",
838 { "code": vcvtFpUIntSCode,
839 "predicate_test": predicateTest }, [])
840 header_output += VfpRegRegOpDeclare.subst(vcvtFpUIntSIop);
841 decoder_output += VfpRegRegOpConstructor.subst(vcvtFpUIntSIop);
842 exec_output += PredOpExecute.subst(vcvtFpUIntSIop);
843
844 vcvtFpUIntDCode = '''
845 IntDoubleUnion cOp1;
846 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
847 VfpSavedState state = prepVfpFpscr(Fpscr);
797 uint64_t result = cOp1.fp;
848 uint64_t result = cOp1.fp;
849 Fpscr = setVfpFpscr(Fpscr, state);
798 FpDestP0.uw = result;
799 '''
800 vcvtFpUIntDIop = InstObjParams("vcvt", "VcvtFpUIntD", "VfpRegRegOp",
801 { "code": vcvtFpUIntDCode,
802 "predicate_test": predicateTest }, [])
803 header_output += VfpRegRegOpDeclare.subst(vcvtFpUIntDIop);
804 decoder_output += VfpRegRegOpConstructor.subst(vcvtFpUIntDIop);
805 exec_output += PredOpExecute.subst(vcvtFpUIntDIop);
806
807 vcvtFpSIntSCode = '''
850 FpDestP0.uw = result;
851 '''
852 vcvtFpUIntDIop = InstObjParams("vcvt", "VcvtFpUIntD", "VfpRegRegOp",
853 { "code": vcvtFpUIntDCode,
854 "predicate_test": predicateTest }, [])
855 header_output += VfpRegRegOpDeclare.subst(vcvtFpUIntDIop);
856 decoder_output += VfpRegRegOpConstructor.subst(vcvtFpUIntDIop);
857 exec_output += PredOpExecute.subst(vcvtFpUIntDIop);
858
859 vcvtFpSIntSCode = '''
860 VfpSavedState state = prepVfpFpscr(Fpscr);
808 FpDest.sw = FpOp1;
861 FpDest.sw = FpOp1;
862 Fpscr = setVfpFpscr(Fpscr, state);
809 '''
810 vcvtFpSIntSIop = InstObjParams("vcvt", "VcvtFpSIntS", "VfpRegRegOp",
811 { "code": vcvtFpSIntSCode,
812 "predicate_test": predicateTest }, [])
813 header_output += VfpRegRegOpDeclare.subst(vcvtFpSIntSIop);
814 decoder_output += VfpRegRegOpConstructor.subst(vcvtFpSIntSIop);
815 exec_output += PredOpExecute.subst(vcvtFpSIntSIop);
816
817 vcvtFpSIntDCode = '''
818 IntDoubleUnion cOp1;
819 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
863 '''
864 vcvtFpSIntSIop = InstObjParams("vcvt", "VcvtFpSIntS", "VfpRegRegOp",
865 { "code": vcvtFpSIntSCode,
866 "predicate_test": predicateTest }, [])
867 header_output += VfpRegRegOpDeclare.subst(vcvtFpSIntSIop);
868 decoder_output += VfpRegRegOpConstructor.subst(vcvtFpSIntSIop);
869 exec_output += PredOpExecute.subst(vcvtFpSIntSIop);
870
871 vcvtFpSIntDCode = '''
872 IntDoubleUnion cOp1;
873 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
874 VfpSavedState state = prepVfpFpscr(Fpscr);
820 int64_t result = cOp1.fp;
875 int64_t result = cOp1.fp;
876 Fpscr = setVfpFpscr(Fpscr, state);
821 FpDestP0.uw = result;
822 '''
823 vcvtFpSIntDIop = InstObjParams("vcvt", "VcvtFpSIntD", "VfpRegRegOp",
824 { "code": vcvtFpSIntDCode,
825 "predicate_test": predicateTest }, [])
826 header_output += VfpRegRegOpDeclare.subst(vcvtFpSIntDIop);
827 decoder_output += VfpRegRegOpConstructor.subst(vcvtFpSIntDIop);
828 exec_output += PredOpExecute.subst(vcvtFpSIntDIop);
829
830 vcvtFpSFpDCode = '''
831 IntDoubleUnion cDest;
877 FpDestP0.uw = result;
878 '''
879 vcvtFpSIntDIop = InstObjParams("vcvt", "VcvtFpSIntD", "VfpRegRegOp",
880 { "code": vcvtFpSIntDCode,
881 "predicate_test": predicateTest }, [])
882 header_output += VfpRegRegOpDeclare.subst(vcvtFpSIntDIop);
883 decoder_output += VfpRegRegOpConstructor.subst(vcvtFpSIntDIop);
884 exec_output += PredOpExecute.subst(vcvtFpSIntDIop);
885
886 vcvtFpSFpDCode = '''
887 IntDoubleUnion cDest;
888 VfpSavedState state = prepVfpFpscr(Fpscr);
832 cDest.fp = FpOp1;
889 cDest.fp = FpOp1;
890 Fpscr = setVfpFpscr(Fpscr, state);
833 FpDestP0.uw = cDest.bits;
834 FpDestP1.uw = cDest.bits >> 32;
835 '''
836 vcvtFpSFpDIop = InstObjParams("vcvt", "VcvtFpSFpD", "VfpRegRegOp",
837 { "code": vcvtFpSFpDCode,
838 "predicate_test": predicateTest }, [])
839 header_output += VfpRegRegOpDeclare.subst(vcvtFpSFpDIop);
840 decoder_output += VfpRegRegOpConstructor.subst(vcvtFpSFpDIop);
841 exec_output += PredOpExecute.subst(vcvtFpSFpDIop);
842
843 vcvtFpDFpSCode = '''
844 IntDoubleUnion cOp1;
845 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
891 FpDestP0.uw = cDest.bits;
892 FpDestP1.uw = cDest.bits >> 32;
893 '''
894 vcvtFpSFpDIop = InstObjParams("vcvt", "VcvtFpSFpD", "VfpRegRegOp",
895 { "code": vcvtFpSFpDCode,
896 "predicate_test": predicateTest }, [])
897 header_output += VfpRegRegOpDeclare.subst(vcvtFpSFpDIop);
898 decoder_output += VfpRegRegOpConstructor.subst(vcvtFpSFpDIop);
899 exec_output += PredOpExecute.subst(vcvtFpSFpDIop);
900
901 vcvtFpDFpSCode = '''
902 IntDoubleUnion cOp1;
903 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
904 VfpSavedState state = prepVfpFpscr(Fpscr);
846 FpDest = cOp1.fp;
905 FpDest = cOp1.fp;
906 Fpscr = setVfpFpscr(Fpscr, state);
847 '''
848 vcvtFpDFpSIop = InstObjParams("vcvt", "VcvtFpDFpS", "VfpRegRegOp",
849 { "code": vcvtFpDFpSCode,
850 "predicate_test": predicateTest }, [])
851 header_output += VfpRegRegOpDeclare.subst(vcvtFpDFpSIop);
852 decoder_output += VfpRegRegOpConstructor.subst(vcvtFpDFpSIop);
853 exec_output += PredOpExecute.subst(vcvtFpDFpSIop);
854

--- 85 unchanged lines hidden --- 		907 '''
908 vcvtFpDFpSIop = InstObjParams("vcvt", "VcvtFpDFpS", "VfpRegRegOp",
909 { "code": vcvtFpDFpSCode,
910 "predicate_test": predicateTest }, [])
911 header_output += VfpRegRegOpDeclare.subst(vcvtFpDFpSIop);
912 decoder_output += VfpRegRegOpConstructor.subst(vcvtFpDFpSIop);
913 exec_output += PredOpExecute.subst(vcvtFpDFpSIop);
914

--- 85 unchanged lines hidden ---