fp.isa (7376:3b781776b2d9) fp.isa (7377:ce388054b481)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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846 FpDest = cOp1.fp;
847 '''
848 vcvtFpDFpSIop = InstObjParams("vcvt", "VcvtFpDFpS", "VfpRegRegOp",
849 { "code": vcvtFpDFpSCode,
850 "predicate_test": predicateTest }, [])
851 header_output += VfpRegRegOpDeclare.subst(vcvtFpDFpSIop);
852 decoder_output += VfpRegRegOpConstructor.subst(vcvtFpDFpSIop);
853 exec_output += PredOpExecute.subst(vcvtFpDFpSIop);
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 837 unchanged lines hidden (view full) ---

846 FpDest = cOp1.fp;
847 '''
848 vcvtFpDFpSIop = InstObjParams("vcvt", "VcvtFpDFpS", "VfpRegRegOp",
849 { "code": vcvtFpDFpSCode,
850 "predicate_test": predicateTest }, [])
851 header_output += VfpRegRegOpDeclare.subst(vcvtFpDFpSIop);
852 decoder_output += VfpRegRegOpConstructor.subst(vcvtFpDFpSIop);
853 exec_output += PredOpExecute.subst(vcvtFpDFpSIop);
854
855 vcmpSCode = '''
856 FPSCR fpscr = Fpscr;
857 if (FpDest == FpOp1) {
858 fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0;
859 } else if (FpDest < FpOp1) {
860 fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0;
861 } else if (FpDest > FpOp1) {
862 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0;
863 } else {
864 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1;
865 }
866 Fpscr = fpscr;
867 '''
868 vcmpSIop = InstObjParams("vcmps", "VcmpS", "VfpRegRegOp",
869 { "code": vcmpSCode,
870 "predicate_test": predicateTest }, [])
871 header_output += VfpRegRegOpDeclare.subst(vcmpSIop);
872 decoder_output += VfpRegRegOpConstructor.subst(vcmpSIop);
873 exec_output += PredOpExecute.subst(vcmpSIop);
874
875 vcmpDCode = '''
876 IntDoubleUnion cOp1, cDest;
877 cDest.bits = ((uint64_t)FpDestP0.uw | ((uint64_t)FpDestP1.uw << 32));
878 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
879 FPSCR fpscr = Fpscr;
880 if (cDest.fp == cOp1.fp) {
881 fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0;
882 } else if (cDest.fp < cOp1.fp) {
883 fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0;
884 } else if (cDest.fp > cOp1.fp) {
885 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0;
886 } else {
887 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1;
888 }
889 Fpscr = fpscr;
890 '''
891 vcmpDIop = InstObjParams("vcmpd", "VcmpD", "VfpRegRegOp",
892 { "code": vcmpDCode,
893 "predicate_test": predicateTest }, [])
894 header_output += VfpRegRegOpDeclare.subst(vcmpDIop);
895 decoder_output += VfpRegRegOpConstructor.subst(vcmpDIop);
896 exec_output += PredOpExecute.subst(vcmpDIop);
897
898 vcmpZeroSCode = '''
899 FPSCR fpscr = Fpscr;
900 if (FpDest == imm) {
901 fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0;
902 } else if (FpDest < imm) {
903 fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0;
904 } else if (FpDest > imm) {
905 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0;
906 } else {
907 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1;
908 }
909 Fpscr = fpscr;
910 '''
911 vcmpZeroSIop = InstObjParams("vcmpZeros", "VcmpZeroS", "VfpRegImmOp",
912 { "code": vcmpZeroSCode,
913 "predicate_test": predicateTest }, [])
914 header_output += VfpRegImmOpDeclare.subst(vcmpZeroSIop);
915 decoder_output += VfpRegImmOpConstructor.subst(vcmpZeroSIop);
916 exec_output += PredOpExecute.subst(vcmpZeroSIop);
917
918 vcmpZeroDCode = '''
919 IntDoubleUnion cDest;
920 cDest.bits = ((uint64_t)FpDestP0.uw | ((uint64_t)FpDestP1.uw << 32));
921 FPSCR fpscr = Fpscr;
922 if (cDest.fp == imm) {
923 fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0;
924 } else if (cDest.fp < imm) {
925 fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0;
926 } else if (cDest.fp > imm) {
927 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0;
928 } else {
929 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1;
930 }
931 Fpscr = fpscr;
932 '''
933 vcmpZeroDIop = InstObjParams("vcmpZerod", "VcmpZeroD", "VfpRegImmOp",
934 { "code": vcmpZeroDCode,
935 "predicate_test": predicateTest }, [])
936 header_output += VfpRegImmOpDeclare.subst(vcmpZeroDIop);
937 decoder_output += VfpRegImmOpConstructor.subst(vcmpZeroDIop);
938 exec_output += PredOpExecute.subst(vcmpZeroDIop);
854}};
939}};