fp.isa (7373:65786254fdd1) fp.isa (7374:9a80d013b955)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 664 unchanged lines hidden (view full) ---

673 FpDestP0.uw = result;
674 '''
675 vcvtFpSIntDIop = InstObjParams("vcvt", "VcvtFpSIntD", "RegRegOp",
676 { "code": vcvtFpSIntDCode,
677 "predicate_test": predicateTest }, [])
678 header_output += RegRegOpDeclare.subst(vcvtFpSIntDIop);
679 decoder_output += RegRegOpConstructor.subst(vcvtFpSIntDIop);
680 exec_output += PredOpExecute.subst(vcvtFpSIntDIop);
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 664 unchanged lines hidden (view full) ---

673 FpDestP0.uw = result;
674 '''
675 vcvtFpSIntDIop = InstObjParams("vcvt", "VcvtFpSIntD", "RegRegOp",
676 { "code": vcvtFpSIntDCode,
677 "predicate_test": predicateTest }, [])
678 header_output += RegRegOpDeclare.subst(vcvtFpSIntDIop);
679 decoder_output += RegRegOpConstructor.subst(vcvtFpSIntDIop);
680 exec_output += PredOpExecute.subst(vcvtFpSIntDIop);
681
682 vcvtFpSFpDCode = '''
683 IntDoubleUnion cDest;
684 cDest.fp = FpOp1;
685 FpDestP0.uw = cDest.bits;
686 FpDestP1.uw = cDest.bits >> 32;
687 '''
688 vcvtFpSFpDIop = InstObjParams("vcvt", "VcvtFpSFpD", "RegRegOp",
689 { "code": vcvtFpSFpDCode,
690 "predicate_test": predicateTest }, [])
691 header_output += RegRegOpDeclare.subst(vcvtFpSFpDIop);
692 decoder_output += RegRegOpConstructor.subst(vcvtFpSFpDIop);
693 exec_output += PredOpExecute.subst(vcvtFpSFpDIop);
694
695 vcvtFpDFpSCode = '''
696 IntDoubleUnion cOp1;
697 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
698 FpDest = cOp1.fp;
699 '''
700 vcvtFpDFpSIop = InstObjParams("vcvt", "VcvtFpDFpS", "RegRegOp",
701 { "code": vcvtFpDFpSCode,
702 "predicate_test": predicateTest }, [])
703 header_output += RegRegOpDeclare.subst(vcvtFpDFpSIop);
704 decoder_output += RegRegOpConstructor.subst(vcvtFpDFpSIop);
705 exec_output += PredOpExecute.subst(vcvtFpDFpSIop);
681}};
706}};