fp.isa (7371:83612101a826) fp.isa (7373:65786254fdd1)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 572 unchanged lines hidden (view full) ---

581 FpDestP1.uw = cDest.bits >> 32;
582 '''
583 vnmulDIop = InstObjParams("vnmuld", "VnmulD", "RegRegRegOp",
584 { "code": vnmulDCode,
585 "predicate_test": predicateTest }, [])
586 header_output += RegRegRegOpDeclare.subst(vnmulDIop);
587 decoder_output += RegRegRegOpConstructor.subst(vnmulDIop);
588 exec_output += PredOpExecute.subst(vnmulDIop);
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 572 unchanged lines hidden (view full) ---

581 FpDestP1.uw = cDest.bits >> 32;
582 '''
583 vnmulDIop = InstObjParams("vnmuld", "VnmulD", "RegRegRegOp",
584 { "code": vnmulDCode,
585 "predicate_test": predicateTest }, [])
586 header_output += RegRegRegOpDeclare.subst(vnmulDIop);
587 decoder_output += RegRegRegOpConstructor.subst(vnmulDIop);
588 exec_output += PredOpExecute.subst(vnmulDIop);
589
590 vcvtUIntFpSCode = '''
591 FpDest = FpOp1.uw;
592 '''
593 vcvtUIntFpSIop = InstObjParams("vcvt", "VcvtUIntFpS", "RegRegOp",
594 { "code": vcvtUIntFpSCode,
595 "predicate_test": predicateTest }, [])
596 header_output += RegRegOpDeclare.subst(vcvtUIntFpSIop);
597 decoder_output += RegRegOpConstructor.subst(vcvtUIntFpSIop);
598 exec_output += PredOpExecute.subst(vcvtUIntFpSIop);
599
600 vcvtUIntFpDCode = '''
601 IntDoubleUnion cDest;
602 cDest.fp = (uint64_t)FpOp1P0.uw;
603 FpDestP0.uw = cDest.bits;
604 FpDestP1.uw = cDest.bits >> 32;
605 '''
606 vcvtUIntFpDIop = InstObjParams("vcvt", "VcvtUIntFpD", "RegRegOp",
607 { "code": vcvtUIntFpDCode,
608 "predicate_test": predicateTest }, [])
609 header_output += RegRegOpDeclare.subst(vcvtUIntFpDIop);
610 decoder_output += RegRegOpConstructor.subst(vcvtUIntFpDIop);
611 exec_output += PredOpExecute.subst(vcvtUIntFpDIop);
612
613 vcvtSIntFpSCode = '''
614 FpDest = FpOp1.sw;
615 '''
616 vcvtSIntFpSIop = InstObjParams("vcvt", "VcvtSIntFpS", "RegRegOp",
617 { "code": vcvtSIntFpSCode,
618 "predicate_test": predicateTest }, [])
619 header_output += RegRegOpDeclare.subst(vcvtSIntFpSIop);
620 decoder_output += RegRegOpConstructor.subst(vcvtSIntFpSIop);
621 exec_output += PredOpExecute.subst(vcvtSIntFpSIop);
622
623 vcvtSIntFpDCode = '''
624 IntDoubleUnion cDest;
625 cDest.fp = FpOp1P0.sw;
626 FpDestP0.uw = cDest.bits;
627 FpDestP1.uw = cDest.bits >> 32;
628 '''
629 vcvtSIntFpDIop = InstObjParams("vcvt", "VcvtSIntFpD", "RegRegOp",
630 { "code": vcvtSIntFpDCode,
631 "predicate_test": predicateTest }, [])
632 header_output += RegRegOpDeclare.subst(vcvtSIntFpDIop);
633 decoder_output += RegRegOpConstructor.subst(vcvtSIntFpDIop);
634 exec_output += PredOpExecute.subst(vcvtSIntFpDIop);
635
636 vcvtFpUIntSCode = '''
637 FpDest.uw = FpOp1;
638 '''
639 vcvtFpUIntSIop = InstObjParams("vcvt", "VcvtFpUIntS", "RegRegOp",
640 { "code": vcvtFpUIntSCode,
641 "predicate_test": predicateTest }, [])
642 header_output += RegRegOpDeclare.subst(vcvtFpUIntSIop);
643 decoder_output += RegRegOpConstructor.subst(vcvtFpUIntSIop);
644 exec_output += PredOpExecute.subst(vcvtFpUIntSIop);
645
646 vcvtFpUIntDCode = '''
647 IntDoubleUnion cOp1;
648 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
649 uint64_t result = cOp1.fp;
650 FpDestP0.uw = result;
651 '''
652 vcvtFpUIntDIop = InstObjParams("vcvt", "VcvtFpUIntD", "RegRegOp",
653 { "code": vcvtFpUIntDCode,
654 "predicate_test": predicateTest }, [])
655 header_output += RegRegOpDeclare.subst(vcvtFpUIntDIop);
656 decoder_output += RegRegOpConstructor.subst(vcvtFpUIntDIop);
657 exec_output += PredOpExecute.subst(vcvtFpUIntDIop);
658
659 vcvtFpSIntSCode = '''
660 FpDest.sw = FpOp1;
661 '''
662 vcvtFpSIntSIop = InstObjParams("vcvt", "VcvtFpSIntS", "RegRegOp",
663 { "code": vcvtFpSIntSCode,
664 "predicate_test": predicateTest }, [])
665 header_output += RegRegOpDeclare.subst(vcvtFpSIntSIop);
666 decoder_output += RegRegOpConstructor.subst(vcvtFpSIntSIop);
667 exec_output += PredOpExecute.subst(vcvtFpSIntSIop);
668
669 vcvtFpSIntDCode = '''
670 IntDoubleUnion cOp1;
671 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
672 int64_t result = cOp1.fp;
673 FpDestP0.uw = result;
674 '''
675 vcvtFpSIntDIop = InstObjParams("vcvt", "VcvtFpSIntD", "RegRegOp",
676 { "code": vcvtFpSIntDCode,
677 "predicate_test": predicateTest }, [])
678 header_output += RegRegOpDeclare.subst(vcvtFpSIntDIop);
679 decoder_output += RegRegOpConstructor.subst(vcvtFpSIntDIop);
680 exec_output += PredOpExecute.subst(vcvtFpSIntDIop);
589}};
681}};