fp.isa (7369:f71b906540cf) fp.isa (7370:6fa1e296585d)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 397 unchanged lines hidden (view full) ---

406 FpDestP1.uw = cDest.bits >> 32;
407 '''
408 vsqrtDIop = InstObjParams("vsqrtd", "VsqrtD", "RegRegOp",
409 { "code": vsqrtDCode,
410 "predicate_test": predicateTest }, [])
411 header_output += RegRegOpDeclare.subst(vsqrtDIop);
412 decoder_output += RegRegOpConstructor.subst(vsqrtDIop);
413 exec_output += PredOpExecute.subst(vsqrtDIop);
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 397 unchanged lines hidden (view full) ---

406 FpDestP1.uw = cDest.bits >> 32;
407 '''
408 vsqrtDIop = InstObjParams("vsqrtd", "VsqrtD", "RegRegOp",
409 { "code": vsqrtDCode,
410 "predicate_test": predicateTest }, [])
411 header_output += RegRegOpDeclare.subst(vsqrtDIop);
412 decoder_output += RegRegOpConstructor.subst(vsqrtDIop);
413 exec_output += PredOpExecute.subst(vsqrtDIop);
414
415 vmlaSCode = '''
416 float mid = FpOp1 * FpOp2;
417 if ((isinf(FpOp1) && FpOp2 == 0) || (isinf(FpOp2) && FpOp1 == 0)) {
418 mid = NAN;
419 }
420 FpDest = FpDest + mid;
421 '''
422 vmlaSIop = InstObjParams("vmlas", "VmlaS", "RegRegRegOp",
423 { "code": vmlaSCode,
424 "predicate_test": predicateTest }, [])
425 header_output += RegRegRegOpDeclare.subst(vmlaSIop);
426 decoder_output += RegRegRegOpConstructor.subst(vmlaSIop);
427 exec_output += PredOpExecute.subst(vmlaSIop);
428
429 vmlaDCode = '''
430 IntDoubleUnion cOp1, cOp2, cDest;
431 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
432 cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32));
433 cDest.bits = ((uint64_t)FpDestP0.uw | ((uint64_t)FpDestP1.uw << 32));
434 double mid = cOp1.fp * cOp2.fp;
435 if ((isinf(cOp1.fp) && cOp2.fp == 0) ||
436 (isinf(cOp2.fp) && cOp1.fp == 0)) {
437 mid = NAN;
438 }
439 cDest.fp = cDest.fp + mid;
440 FpDestP0.uw = cDest.bits;
441 FpDestP1.uw = cDest.bits >> 32;
442 '''
443 vmlaDIop = InstObjParams("vmlad", "VmlaD", "RegRegRegOp",
444 { "code": vmlaDCode,
445 "predicate_test": predicateTest }, [])
446 header_output += RegRegRegOpDeclare.subst(vmlaDIop);
447 decoder_output += RegRegRegOpConstructor.subst(vmlaDIop);
448 exec_output += PredOpExecute.subst(vmlaDIop);
449
450 vmlsSCode = '''
451 float mid = FpOp1 * FpOp2;
452 if ((isinf(FpOp1) && FpOp2 == 0) || (isinf(FpOp2) && FpOp1 == 0)) {
453 mid = NAN;
454 }
455 FpDest = FpDest - mid;
456 '''
457 vmlsSIop = InstObjParams("vmlss", "VmlsS", "RegRegRegOp",
458 { "code": vmlsSCode,
459 "predicate_test": predicateTest }, [])
460 header_output += RegRegRegOpDeclare.subst(vmlsSIop);
461 decoder_output += RegRegRegOpConstructor.subst(vmlsSIop);
462 exec_output += PredOpExecute.subst(vmlsSIop);
463
464 vmlsDCode = '''
465 IntDoubleUnion cOp1, cOp2, cDest;
466 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
467 cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32));
468 cDest.bits = ((uint64_t)FpDestP0.uw | ((uint64_t)FpDestP1.uw << 32));
469 double mid = cOp1.fp * cOp2.fp;
470 if ((isinf(cOp1.fp) && cOp2.fp == 0) ||
471 (isinf(cOp2.fp) && cOp1.fp == 0)) {
472 mid = NAN;
473 }
474 cDest.fp = cDest.fp - mid;
475 FpDestP0.uw = cDest.bits;
476 FpDestP1.uw = cDest.bits >> 32;
477 '''
478 vmlsDIop = InstObjParams("vmlsd", "VmlsD", "RegRegRegOp",
479 { "code": vmlsDCode,
480 "predicate_test": predicateTest }, [])
481 header_output += RegRegRegOpDeclare.subst(vmlsDIop);
482 decoder_output += RegRegRegOpConstructor.subst(vmlsDIop);
483 exec_output += PredOpExecute.subst(vmlsDIop);
414}};
484}};