fp.isa (7368:3053e3587124) | fp.isa (7369:f71b906540cf) |
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1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating --- 342 unchanged lines hidden (view full) --- 351 FpDestP1.uw = cDest.bits >> 32; 352 ''' 353 vsubDIop = InstObjParams("vsubd", "VsubD", "RegRegRegOp", 354 { "code": vsubDCode, 355 "predicate_test": predicateTest }, []) 356 header_output += RegRegRegOpDeclare.subst(vsubDIop); 357 decoder_output += RegRegRegOpConstructor.subst(vsubDIop); 358 exec_output += PredOpExecute.subst(vsubDIop); | 1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating --- 342 unchanged lines hidden (view full) --- 351 FpDestP1.uw = cDest.bits >> 32; 352 ''' 353 vsubDIop = InstObjParams("vsubd", "VsubD", "RegRegRegOp", 354 { "code": vsubDCode, 355 "predicate_test": predicateTest }, []) 356 header_output += RegRegRegOpDeclare.subst(vsubDIop); 357 decoder_output += RegRegRegOpConstructor.subst(vsubDIop); 358 exec_output += PredOpExecute.subst(vsubDIop); |
359 360 vdivSCode = ''' 361 FpDest = FpOp1 / FpOp2; 362 ''' 363 vdivSIop = InstObjParams("vdivs", "VdivS", "RegRegRegOp", 364 { "code": vdivSCode, 365 "predicate_test": predicateTest }, []) 366 header_output += RegRegRegOpDeclare.subst(vdivSIop); 367 decoder_output += RegRegRegOpConstructor.subst(vdivSIop); 368 exec_output += PredOpExecute.subst(vdivSIop); 369 370 vdivDCode = ''' 371 IntDoubleUnion cOp1, cOp2, cDest; 372 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 373 cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32)); 374 cDest.fp = cOp1.fp / cOp2.fp; 375 FpDestP0.uw = cDest.bits; 376 FpDestP1.uw = cDest.bits >> 32; 377 ''' 378 vdivDIop = InstObjParams("vdivd", "VdivD", "RegRegRegOp", 379 { "code": vdivDCode, 380 "predicate_test": predicateTest }, []) 381 header_output += RegRegRegOpDeclare.subst(vdivDIop); 382 decoder_output += RegRegRegOpConstructor.subst(vdivDIop); 383 exec_output += PredOpExecute.subst(vdivDIop); 384 385 vsqrtSCode = ''' 386 FpDest = sqrtf(FpOp1); 387 if (FpOp1 < 0) { 388 FpDest = NAN; 389 } 390 ''' 391 vsqrtSIop = InstObjParams("vsqrts", "VsqrtS", "RegRegOp", 392 { "code": vsqrtSCode, 393 "predicate_test": predicateTest }, []) 394 header_output += RegRegOpDeclare.subst(vsqrtSIop); 395 decoder_output += RegRegOpConstructor.subst(vsqrtSIop); 396 exec_output += PredOpExecute.subst(vsqrtSIop); 397 398 vsqrtDCode = ''' 399 IntDoubleUnion cOp1, cDest; 400 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 401 cDest.fp = sqrt(cOp1.fp); 402 if (cOp1.fp < 0) { 403 cDest.fp = NAN; 404 } 405 FpDestP0.uw = cDest.bits; 406 FpDestP1.uw = cDest.bits >> 32; 407 ''' 408 vsqrtDIop = InstObjParams("vsqrtd", "VsqrtD", "RegRegOp", 409 { "code": vsqrtDCode, 410 "predicate_test": predicateTest }, []) 411 header_output += RegRegOpDeclare.subst(vsqrtDIop); 412 decoder_output += RegRegOpConstructor.subst(vsqrtDIop); 413 exec_output += PredOpExecute.subst(vsqrtDIop); |
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359}}; | 414}}; |