fp.isa (7367:8c3ec534f022) fp.isa (7368:3053e3587124)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 317 unchanged lines hidden (view full) ---

326 FpDestP1.uw = cDest.bits >> 32;
327 '''
328 vaddDIop = InstObjParams("vaddd", "VaddD", "RegRegRegOp",
329 { "code": vaddDCode,
330 "predicate_test": predicateTest }, [])
331 header_output += RegRegRegOpDeclare.subst(vaddDIop);
332 decoder_output += RegRegRegOpConstructor.subst(vaddDIop);
333 exec_output += PredOpExecute.subst(vaddDIop);
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 317 unchanged lines hidden (view full) ---

326 FpDestP1.uw = cDest.bits >> 32;
327 '''
328 vaddDIop = InstObjParams("vaddd", "VaddD", "RegRegRegOp",
329 { "code": vaddDCode,
330 "predicate_test": predicateTest }, [])
331 header_output += RegRegRegOpDeclare.subst(vaddDIop);
332 decoder_output += RegRegRegOpConstructor.subst(vaddDIop);
333 exec_output += PredOpExecute.subst(vaddDIop);
334
335 vsubSCode = '''
336 FpDest = FpOp1 - FpOp2;
337 '''
338 vsubSIop = InstObjParams("vsubs", "VsubS", "RegRegRegOp",
339 { "code": vsubSCode,
340 "predicate_test": predicateTest }, [])
341 header_output += RegRegRegOpDeclare.subst(vsubSIop);
342 decoder_output += RegRegRegOpConstructor.subst(vsubSIop);
343 exec_output += PredOpExecute.subst(vsubSIop);
344
345 vsubDCode = '''
346 IntDoubleUnion cOp1, cOp2, cDest;
347 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
348 cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32));
349 cDest.fp = cOp1.fp - cOp2.fp;
350 FpDestP0.uw = cDest.bits;
351 FpDestP1.uw = cDest.bits >> 32;
352 '''
353 vsubDIop = InstObjParams("vsubd", "VsubD", "RegRegRegOp",
354 { "code": vsubDCode,
355 "predicate_test": predicateTest }, [])
356 header_output += RegRegRegOpDeclare.subst(vsubDIop);
357 decoder_output += RegRegRegOpConstructor.subst(vsubDIop);
358 exec_output += PredOpExecute.subst(vsubDIop);
334}};
359}};