fp.isa (7365:a7a6cc5f6a89) fp.isa (7366:4efa4733e66e)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 268 unchanged lines hidden (view full) ---

277 FpDestP1.uw = cDest.bits >> 32;
278 '''
279 vnegDIop = InstObjParams("vnegd", "VnegD", "RegRegOp",
280 { "code": vnegDCode,
281 "predicate_test": predicateTest }, [])
282 header_output += RegRegOpDeclare.subst(vnegDIop);
283 decoder_output += RegRegOpConstructor.subst(vnegDIop);
284 exec_output += PredOpExecute.subst(vnegDIop);
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 268 unchanged lines hidden (view full) ---

277 FpDestP1.uw = cDest.bits >> 32;
278 '''
279 vnegDIop = InstObjParams("vnegd", "VnegD", "RegRegOp",
280 { "code": vnegDCode,
281 "predicate_test": predicateTest }, [])
282 header_output += RegRegOpDeclare.subst(vnegDIop);
283 decoder_output += RegRegOpConstructor.subst(vnegDIop);
284 exec_output += PredOpExecute.subst(vnegDIop);
285
286 vabsSCode = '''
287 FpDest = fabsf(FpOp1);
288 '''
289 vabsSIop = InstObjParams("vabss", "VabsS", "RegRegOp",
290 { "code": vabsSCode,
291 "predicate_test": predicateTest }, [])
292 header_output += RegRegOpDeclare.subst(vabsSIop);
293 decoder_output += RegRegOpConstructor.subst(vabsSIop);
294 exec_output += PredOpExecute.subst(vabsSIop);
295
296 vabsDCode = '''
297 IntDoubleUnion cOp1, cDest;
298 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
299 cDest.fp = fabs(cOp1.fp);
300 FpDestP0.uw = cDest.bits;
301 FpDestP1.uw = cDest.bits >> 32;
302 '''
303 vabsDIop = InstObjParams("vabsd", "VabsD", "RegRegOp",
304 { "code": vabsDCode,
305 "predicate_test": predicateTest }, [])
306 header_output += RegRegOpDeclare.subst(vabsDIop);
307 decoder_output += RegRegOpConstructor.subst(vabsDIop);
308 exec_output += PredOpExecute.subst(vabsDIop);
285}};
309}};