fp.isa (7364:9d34477e6adb) fp.isa (7365:a7a6cc5f6a89)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 244 unchanged lines hidden (view full) ---

253 FpDestP1.uw = cDest.bits >> 32;
254 '''
255 vmulDIop = InstObjParams("vmuld", "VmulD", "RegRegRegOp",
256 { "code": vmulDCode,
257 "predicate_test": predicateTest }, [])
258 header_output += RegRegRegOpDeclare.subst(vmulDIop);
259 decoder_output += RegRegRegOpConstructor.subst(vmulDIop);
260 exec_output += PredOpExecute.subst(vmulDIop);
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 244 unchanged lines hidden (view full) ---

253 FpDestP1.uw = cDest.bits >> 32;
254 '''
255 vmulDIop = InstObjParams("vmuld", "VmulD", "RegRegRegOp",
256 { "code": vmulDCode,
257 "predicate_test": predicateTest }, [])
258 header_output += RegRegRegOpDeclare.subst(vmulDIop);
259 decoder_output += RegRegRegOpConstructor.subst(vmulDIop);
260 exec_output += PredOpExecute.subst(vmulDIop);
261
262 vnegSCode = '''
263 FpDest = -FpOp1;
264 '''
265 vnegSIop = InstObjParams("vnegs", "VnegS", "RegRegOp",
266 { "code": vnegSCode,
267 "predicate_test": predicateTest }, [])
268 header_output += RegRegOpDeclare.subst(vnegSIop);
269 decoder_output += RegRegOpConstructor.subst(vnegSIop);
270 exec_output += PredOpExecute.subst(vnegSIop);
271
272 vnegDCode = '''
273 IntDoubleUnion cOp1, cDest;
274 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
275 cDest.fp = -cOp1.fp;
276 FpDestP0.uw = cDest.bits;
277 FpDestP1.uw = cDest.bits >> 32;
278 '''
279 vnegDIop = InstObjParams("vnegd", "VnegD", "RegRegOp",
280 { "code": vnegDCode,
281 "predicate_test": predicateTest }, [])
282 header_output += RegRegOpDeclare.subst(vnegDIop);
283 decoder_output += RegRegOpConstructor.subst(vnegDIop);
284 exec_output += PredOpExecute.subst(vnegDIop);
261}};
285}};