fp.isa (7333:63e4f48e59d4) fp.isa (7364:9d34477e6adb)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 212 unchanged lines hidden (view full) ---

221 Op1.uw = FpOp2P1.uw;
222 '''
223 vmov2Core2RegIop = InstObjParams("vmov", "Vmov2Core2Reg", "RegRegRegOp",
224 { "code": vmov2Core2RegCode,
225 "predicate_test": predicateTest }, [])
226 header_output += RegRegRegOpDeclare.subst(vmov2Core2RegIop);
227 decoder_output += RegRegRegOpConstructor.subst(vmov2Core2RegIop);
228 exec_output += PredOpExecute.subst(vmov2Core2RegIop);
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 212 unchanged lines hidden (view full) ---

221 Op1.uw = FpOp2P1.uw;
222 '''
223 vmov2Core2RegIop = InstObjParams("vmov", "Vmov2Core2Reg", "RegRegRegOp",
224 { "code": vmov2Core2RegCode,
225 "predicate_test": predicateTest }, [])
226 header_output += RegRegRegOpDeclare.subst(vmov2Core2RegIop);
227 decoder_output += RegRegRegOpConstructor.subst(vmov2Core2RegIop);
228 exec_output += PredOpExecute.subst(vmov2Core2RegIop);
229
230 vmulSCode = '''
231 FpDest = FpOp1 * FpOp2;
232 if ((isinf(FpOp1) && FpOp2 == 0) || (isinf(FpOp2) && FpOp1 == 0)) {
233 FpDest = NAN;
234 }
235 '''
236 vmulSIop = InstObjParams("vmuls", "VmulS", "RegRegRegOp",
237 { "code": vmulSCode,
238 "predicate_test": predicateTest }, [])
239 header_output += RegRegRegOpDeclare.subst(vmulSIop);
240 decoder_output += RegRegRegOpConstructor.subst(vmulSIop);
241 exec_output += PredOpExecute.subst(vmulSIop);
242
243 vmulDCode = '''
244 IntDoubleUnion cOp1, cOp2, cDest;
245 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
246 cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32));
247 cDest.fp = cOp1.fp * cOp2.fp;
248 if ((isinf(cOp1.fp) && cOp2.fp == 0) ||
249 (isinf(cOp2.fp) && cOp1.fp == 0)) {
250 cDest.fp = NAN;
251 }
252 FpDestP0.uw = cDest.bits;
253 FpDestP1.uw = cDest.bits >> 32;
254 '''
255 vmulDIop = InstObjParams("vmuld", "VmulD", "RegRegRegOp",
256 { "code": vmulDCode,
257 "predicate_test": predicateTest }, [])
258 header_output += RegRegRegOpDeclare.subst(vmulDIop);
259 decoder_output += RegRegRegOpConstructor.subst(vmulDIop);
260 exec_output += PredOpExecute.subst(vmulDIop);
229}};
261}};