fp.isa (12236:126ac9da6050) fp.isa (13738:84439021dcf6)
1// -*- mode:c++ -*-
2
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010-2013,2016 ARM Limited
3// Copyright (c) 2010-2013,2016,2018-2019 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder. You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated

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988 vcvtFpSIntDRIop = InstObjParams("vcvtr", "VcvtFpSIntDR", "FpRegRegOp",
989 { "code": vcvtFpSIntDRCode,
990 "predicate_test": predicateTest,
991 "op_class": "SimdFloatCvtOp" }, [])
992 header_output += FpRegRegOpDeclare.subst(vcvtFpSIntDRIop);
993 decoder_output += FpRegRegOpConstructor.subst(vcvtFpSIntDRIop);
994 exec_output += PredOpExecute.subst(vcvtFpSIntDRIop);
995
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder. You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated

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988 vcvtFpSIntDRIop = InstObjParams("vcvtr", "VcvtFpSIntDR", "FpRegRegOp",
989 { "code": vcvtFpSIntDRCode,
990 "predicate_test": predicateTest,
991 "op_class": "SimdFloatCvtOp" }, [])
992 header_output += FpRegRegOpDeclare.subst(vcvtFpSIntDRIop);
993 decoder_output += FpRegRegOpConstructor.subst(vcvtFpSIntDRIop);
994 exec_output += PredOpExecute.subst(vcvtFpSIntDRIop);
995
996 vcvtFpUIntSCode = vfpEnabledCheckCode + '''
996 round_mode_suffix_to_mode = {
997 '': 'VfpRoundZero',
998 'a': 'VfpRoundAway',
999 'm': 'VfpRoundDown',
1000 'n': 'VfpRoundNearest',
1001 'p': 'VfpRoundUpward',
1002 }
1003
1004 def buildVcvt(code, className, roundModeSuffix):
1005 global header_output, decoder_output, exec_output, \
1006 vfpEnabledCheckCode, round_mode_suffix_to_mode
1007 full_code = vfpEnabledCheckCode + code.format(
1008 round_mode=round_mode_suffix_to_mode[roundModeSuffix],
1009 )
1010 iop = InstObjParams(
1011 "vcvt{}".format(roundModeSuffix),
1012 className.format(roundModeSuffix),
1013 "FpRegRegOp",
1014 { "code": full_code,
1015 "predicate_test": predicateTest,
1016 "op_class": "SimdFloatCvtOp" },
1017 []
1018 )
1019 header_output += FpRegRegOpDeclare.subst(iop);
1020 decoder_output += FpRegRegOpConstructor.subst(iop);
1021 exec_output += PredOpExecute.subst(iop);
1022
1023 code = '''
997 FPSCR fpscr = (FPSCR) FpscrExc;
998 vfpFlushToZero(fpscr, FpOp1);
999 VfpSavedState state = prepFpState(fpscr.rMode);
1000 fesetround(FeRoundZero);
1001 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
1024 FPSCR fpscr = (FPSCR) FpscrExc;
1025 vfpFlushToZero(fpscr, FpOp1);
1026 VfpSavedState state = prepFpState(fpscr.rMode);
1027 fesetround(FeRoundZero);
1028 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
1002 FpDest_uw = vfpFpToFixed<float>(FpOp1, false, 32, 0);
1029 FpDest_uw = vfpFpToFixed(
1030 FpOp1, false, 32, 0, true, {round_mode});
1003 __asm__ __volatile__("" :: "m" (FpDest_uw));
1004 finishVfp(fpscr, state, fpscr.fz);
1005 FpscrExc = fpscr;
1006 '''
1031 __asm__ __volatile__("" :: "m" (FpDest_uw));
1032 finishVfp(fpscr, state, fpscr.fz);
1033 FpscrExc = fpscr;
1034 '''
1007 vcvtFpUIntSIop = InstObjParams("vcvt", "VcvtFpUIntS", "FpRegRegOp",
1008 { "code": vcvtFpUIntSCode,
1009 "predicate_test": predicateTest,
1010 "op_class": "SimdFloatCvtOp" }, [])
1011 header_output += FpRegRegOpDeclare.subst(vcvtFpUIntSIop);
1012 decoder_output += FpRegRegOpConstructor.subst(vcvtFpUIntSIop);
1013 exec_output += PredOpExecute.subst(vcvtFpUIntSIop);
1035 for round_mode_suffix in round_mode_suffix_to_mode:
1036 buildVcvt(code, "Vcvt{}FpUIntS", round_mode_suffix)
1014
1037
1015 vcvtFpUIntDCode = vfpEnabledCheckCode + '''
1038 code = '''
1016 FPSCR fpscr = (FPSCR) FpscrExc;
1017 double cOp1 = dbl(FpOp1P0_uw, FpOp1P1_uw);
1018 vfpFlushToZero(fpscr, cOp1);
1019 VfpSavedState state = prepFpState(fpscr.rMode);
1020 fesetround(FeRoundZero);
1021 __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1));
1039 FPSCR fpscr = (FPSCR) FpscrExc;
1040 double cOp1 = dbl(FpOp1P0_uw, FpOp1P1_uw);
1041 vfpFlushToZero(fpscr, cOp1);
1042 VfpSavedState state = prepFpState(fpscr.rMode);
1043 fesetround(FeRoundZero);
1044 __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1));
1022 uint64_t result = vfpFpToFixed<double>(cOp1, false, 32, 0);
1045 uint64_t result = vfpFpToFixed(
1046 cOp1, false, 32, 0, true, {round_mode});
1023 __asm__ __volatile__("" :: "m" (result));
1024 finishVfp(fpscr, state, fpscr.fz);
1025 FpDestP0_uw = result;
1026 FpscrExc = fpscr;
1027 '''
1047 __asm__ __volatile__("" :: "m" (result));
1048 finishVfp(fpscr, state, fpscr.fz);
1049 FpDestP0_uw = result;
1050 FpscrExc = fpscr;
1051 '''
1028 vcvtFpUIntDIop = InstObjParams("vcvt", "VcvtFpUIntD", "FpRegRegOp",
1029 { "code": vcvtFpUIntDCode,
1030 "predicate_test": predicateTest,
1031 "op_class": "SimdFloatCvtOp" }, [])
1032 header_output += FpRegRegOpDeclare.subst(vcvtFpUIntDIop);
1033 decoder_output += FpRegRegOpConstructor.subst(vcvtFpUIntDIop);
1034 exec_output += PredOpExecute.subst(vcvtFpUIntDIop);
1052 for round_mode_suffix in round_mode_suffix_to_mode:
1053 buildVcvt(code, "Vcvt{}FpUIntD", round_mode_suffix)
1035
1054
1036 vcvtFpSIntSCode = vfpEnabledCheckCode + '''
1055 code = '''
1037 FPSCR fpscr = (FPSCR) FpscrExc;
1038 vfpFlushToZero(fpscr, FpOp1);
1039 VfpSavedState state = prepFpState(fpscr.rMode);
1040 fesetround(FeRoundZero);
1041 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
1056 FPSCR fpscr = (FPSCR) FpscrExc;
1057 vfpFlushToZero(fpscr, FpOp1);
1058 VfpSavedState state = prepFpState(fpscr.rMode);
1059 fesetround(FeRoundZero);
1060 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
1042 FpDest_sw = vfpFpToFixed<float>(FpOp1, true, 32, 0);
1061 FpDest_sw = vfpFpToFixed(
1062 FpOp1, true, 32, 0, true, {round_mode});
1043 __asm__ __volatile__("" :: "m" (FpDest_sw));
1044 finishVfp(fpscr, state, fpscr.fz);
1045 FpscrExc = fpscr;
1046 '''
1063 __asm__ __volatile__("" :: "m" (FpDest_sw));
1064 finishVfp(fpscr, state, fpscr.fz);
1065 FpscrExc = fpscr;
1066 '''
1047 vcvtFpSIntSIop = InstObjParams("vcvt", "VcvtFpSIntS", "FpRegRegOp",
1048 { "code": vcvtFpSIntSCode,
1049 "predicate_test": predicateTest,
1050 "op_class": "SimdFloatCvtOp" }, [])
1051 header_output += FpRegRegOpDeclare.subst(vcvtFpSIntSIop);
1052 decoder_output += FpRegRegOpConstructor.subst(vcvtFpSIntSIop);
1053 exec_output += PredOpExecute.subst(vcvtFpSIntSIop);
1067 for round_mode_suffix in round_mode_suffix_to_mode:
1068 buildVcvt(code, "Vcvt{}FpSIntS", round_mode_suffix)
1054
1069
1055 vcvtFpSIntDCode = vfpEnabledCheckCode + '''
1070 code = '''
1056 FPSCR fpscr = (FPSCR) FpscrExc;
1057 double cOp1 = dbl(FpOp1P0_uw, FpOp1P1_uw);
1058 vfpFlushToZero(fpscr, cOp1);
1059 VfpSavedState state = prepFpState(fpscr.rMode);
1060 fesetround(FeRoundZero);
1061 __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1));
1071 FPSCR fpscr = (FPSCR) FpscrExc;
1072 double cOp1 = dbl(FpOp1P0_uw, FpOp1P1_uw);
1073 vfpFlushToZero(fpscr, cOp1);
1074 VfpSavedState state = prepFpState(fpscr.rMode);
1075 fesetround(FeRoundZero);
1076 __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1));
1062 int64_t result = vfpFpToFixed<double>(cOp1, true, 32, 0);
1077 int64_t result = vfpFpToFixed(
1078 cOp1, true, 32, 0, true, {round_mode});
1063 __asm__ __volatile__("" :: "m" (result));
1064 finishVfp(fpscr, state, fpscr.fz);
1065 FpDestP0_uw = result;
1066 FpscrExc = fpscr;
1067 '''
1079 __asm__ __volatile__("" :: "m" (result));
1080 finishVfp(fpscr, state, fpscr.fz);
1081 FpDestP0_uw = result;
1082 FpscrExc = fpscr;
1083 '''
1068 vcvtFpSIntDIop = InstObjParams("vcvt", "VcvtFpSIntD", "FpRegRegOp",
1069 { "code": vcvtFpSIntDCode,
1070 "predicate_test": predicateTest,
1071 "op_class": "SimdFloatCvtOp" }, [])
1072 header_output += FpRegRegOpDeclare.subst(vcvtFpSIntDIop);
1073 decoder_output += FpRegRegOpConstructor.subst(vcvtFpSIntDIop);
1074 exec_output += PredOpExecute.subst(vcvtFpSIntDIop);
1084 for round_mode_suffix in round_mode_suffix_to_mode:
1085 buildVcvt(code, "Vcvt{}FpSIntD", round_mode_suffix)
1075
1076 vcvtFpSFpDCode = vfpEnabledCheckCode + '''
1077 FPSCR fpscr = (FPSCR) FpscrExc;
1078 vfpFlushToZero(fpscr, FpOp1);
1079 VfpSavedState state = prepFpState(fpscr.rMode);
1080 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
1081 double cDest = fixFpSFpDDest(FpscrExc, FpOp1);
1082 __asm__ __volatile__("" :: "m" (cDest));

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1087 vcvtFpSFpDCode = vfpEnabledCheckCode + '''
1088 FPSCR fpscr = (FPSCR) FpscrExc;
1089 vfpFlushToZero(fpscr, FpOp1);
1090 VfpSavedState state = prepFpState(fpscr.rMode);
1091 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
1092 double cDest = fixFpSFpDDest(FpscrExc, FpOp1);
1093 __asm__ __volatile__("" :: "m" (cDest));

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