fp.isa (11513:cb3a401c45d7) fp.isa (11671:520509f3e66c)
1// -*- mode:c++ -*-
2
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010-2013 ARM Limited
3// Copyright (c) 2010-2013,2016 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder. You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated

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637 header_output += declareTempl.subst(iop)
638 decoder_output += constructorTempl.subst(iop)
639 exec_output += PredOpExecute.subst(iop)
640
641 buildSimpleUnaryFpOp("vneg", "Vneg", "FpRegRegOp", "SimdFloatMiscOp",
642 "-FpOp1", "-dbl(FpOp1P0_uw, FpOp1P1_uw)")
643 buildSimpleUnaryFpOp("vabs", "Vabs", "FpRegRegOp", "SimdFloatMiscOp",
644 "fabsf(FpOp1)", "fabs(dbl(FpOp1P0_uw, FpOp1P1_uw))")
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder. You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated

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637 header_output += declareTempl.subst(iop)
638 decoder_output += constructorTempl.subst(iop)
639 exec_output += PredOpExecute.subst(iop)
640
641 buildSimpleUnaryFpOp("vneg", "Vneg", "FpRegRegOp", "SimdFloatMiscOp",
642 "-FpOp1", "-dbl(FpOp1P0_uw, FpOp1P1_uw)")
643 buildSimpleUnaryFpOp("vabs", "Vabs", "FpRegRegOp", "SimdFloatMiscOp",
644 "fabsf(FpOp1)", "fabs(dbl(FpOp1P0_uw, FpOp1P1_uw))")
645 buildSimpleUnaryFpOp("vrintp", "VRIntP", "FpRegRegOp", "SimdFloatMiscOp",
646 "fplibRoundInt<uint32_t>(FpOp1, FPRounding_POSINF, false, fpscr)",
647 "fplibRoundInt<uint64_t>(dbl(FpOp1P0_uw, FpOp1P1_uw), " \
648 "FPRounding_POSINF, false, fpscr)"
649 )
650 buildSimpleUnaryFpOp("vrintm", "VRIntM", "FpRegRegOp", "SimdFloatMiscOp",
651 "fplibRoundInt<uint32_t>(FpOp1, FPRounding_NEGINF, false, fpscr)",
652 "fplibRoundInt<uint64_t>(dbl(FpOp1P0_uw, FpOp1P1_uw), " \
653 "FPRounding_NEGINF, false, fpscr)"
654 )
655 buildSimpleUnaryFpOp("vrinta", "VRIntA", "FpRegRegOp", "SimdFloatMiscOp",
656 "fplibRoundInt<uint32_t>(FpOp1, FPRounding_TIEAWAY, false, fpscr)",
657 "fplibRoundInt<uint64_t>(dbl(FpOp1P0_uw, FpOp1P1_uw), " \
658 "FPRounding_TIEAWAY, false, fpscr)"
659 )
660 buildSimpleUnaryFpOp("vrintn", "VRIntN", "FpRegRegOp", "SimdFloatMiscOp",
661 "fplibRoundInt<uint32_t>(FpOp1, FPRounding_TIEEVEN, false, fpscr)",
662 "fplibRoundInt<uint64_t>(dbl(FpOp1P0_uw, FpOp1P1_uw), " \
663 "FPRounding_TIEEVEN, false, fpscr)"
664 )
645}};
646
647let {{
648
649 header_output = ""
650 decoder_output = ""
651 exec_output = ""
652

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1403}};
1404
1405let {{
1406
1407 header_output = ""
1408 decoder_output = ""
1409 exec_output = ""
1410
665}};
666
667let {{
668
669 header_output = ""
670 decoder_output = ""
671 exec_output = ""
672

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1423}};
1424
1425let {{
1426
1427 header_output = ""
1428 decoder_output = ""
1429 exec_output = ""
1430
1431 vselSCode = vfpEnabledCheckCode + '''
1432 if (testPredicate(CondCodesNZ, CondCodesC, CondCodesV, cond)) {
1433 FpDest = FpOp1;
1434 } else {
1435 FpDest = FpOp2;
1436 } '''
1437
1438 vselSIop = InstObjParams("vsels", "VselS", "FpRegRegRegCondOp",
1439 { "code" : vselSCode,
1440 "predicate_test" : predicateTest,
1441 "op_class" : "SimdFloatCmpOp" }, [] )
1442 header_output += FpRegRegRegCondOpDeclare.subst(vselSIop);
1443 decoder_output += FpRegRegRegCondOpConstructor.subst(vselSIop);
1444 exec_output += PredOpExecute.subst(vselSIop);
1445
1446 vselDCode = vfpEnabledCheckCode + '''
1447 if (testPredicate(CondCodesNZ, CondCodesC, CondCodesV, cond)) {
1448 FpDestP0_uw = FpOp1P0_uw;
1449 FpDestP1_uw = FpOp1P1_uw;
1450 } else {
1451 FpDestP0_uw = FpOp2P0_uw;
1452 FpDestP1_uw = FpOp2P1_uw;
1453 } '''
1454
1455 vselDIop = InstObjParams("vseld", "VselD", "FpRegRegRegCondOp",
1456 { "code" : vselDCode,
1457 "predicate_test" : predicateTest,
1458 "op_class" : "SimdFloatCmpOp" }, [] )
1459 header_output += FpRegRegRegCondOpDeclare.subst(vselDIop);
1460 decoder_output += FpRegRegRegCondOpConstructor.subst(vselDIop);
1461 exec_output += PredOpExecute.subst(vselDIop);
1462}};
1463
1464
1465let {{
1466
1467 header_output = ""
1468 decoder_output = ""
1469 exec_output = ""
1470
1411 vcvtFpSFixedSCode = vfpEnabledCheckCode + '''
1412 FPSCR fpscr = (FPSCR) FpscrExc;
1413 vfpFlushToZero(fpscr, FpOp1);
1414 VfpSavedState state = prepFpState(fpscr.rMode);
1415 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
1416 FpDest_sw = vfpFpToFixed<float>(FpOp1, true, 32, imm);
1417 __asm__ __volatile__("" :: "m" (FpDest_sw));
1418 finishVfp(fpscr, state, fpscr.fz);

--- 304 unchanged lines hidden --- 		1471 vcvtFpSFixedSCode = vfpEnabledCheckCode + '''
1472 FPSCR fpscr = (FPSCR) FpscrExc;
1473 vfpFlushToZero(fpscr, FpOp1);
1474 VfpSavedState state = prepFpState(fpscr.rMode);
1475 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
1476 FpDest_sw = vfpFpToFixed<float>(FpOp1, true, 32, imm);
1477 __asm__ __volatile__("" :: "m" (FpDest_sw));
1478 finishVfp(fpscr, state, fpscr.fz);

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