1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating --- 646 unchanged lines hidden (view full) --- 655 656let {{ 657 658 header_output = "" 659 decoder_output = "" 660 exec_output = "" 661 662 vcvtUIntFpSCode = ''' |
663 FPSCR fpscr = Fpscr; 664 VfpSavedState state = prepFpState(fpscr.rMode); |
665 __asm__ __volatile__("" : "=m" (FpOp1.uw) : "m" (FpOp1.uw)); 666 FpDest = FpOp1.uw; 667 __asm__ __volatile__("" :: "m" (FpDest)); |
668 finishVfp(fpscr, state); 669 Fpscr = fpscr; |
670 ''' 671 vcvtUIntFpSIop = InstObjParams("vcvt", "VcvtUIntFpS", "FpRegRegOp", 672 { "code": vcvtUIntFpSCode, 673 "predicate_test": predicateTest }, []) 674 header_output += FpRegRegOpDeclare.subst(vcvtUIntFpSIop); 675 decoder_output += FpRegRegOpConstructor.subst(vcvtUIntFpSIop); 676 exec_output += PredOpExecute.subst(vcvtUIntFpSIop); 677 678 vcvtUIntFpDCode = ''' |
679 FPSCR fpscr = Fpscr; 680 VfpSavedState state = prepFpState(fpscr.rMode); |
681 __asm__ __volatile__("" : "=m" (FpOp1P0.uw) : "m" (FpOp1P0.uw)); |
682 double cDest = (uint64_t)FpOp1P0.uw; 683 __asm__ __volatile__("" :: "m" (cDest)); 684 finishVfp(fpscr, state); 685 Fpscr = fpscr; 686 FpDestP0.uw = dblLow(cDest); 687 FpDestP1.uw = dblHi(cDest); |
688 ''' 689 vcvtUIntFpDIop = InstObjParams("vcvt", "VcvtUIntFpD", "FpRegRegOp", 690 { "code": vcvtUIntFpDCode, 691 "predicate_test": predicateTest }, []) 692 header_output += FpRegRegOpDeclare.subst(vcvtUIntFpDIop); 693 decoder_output += FpRegRegOpConstructor.subst(vcvtUIntFpDIop); 694 exec_output += PredOpExecute.subst(vcvtUIntFpDIop); 695 696 vcvtSIntFpSCode = ''' |
697 FPSCR fpscr = Fpscr; 698 VfpSavedState state = prepFpState(fpscr.rMode); |
699 __asm__ __volatile__("" : "=m" (FpOp1.sw) : "m" (FpOp1.sw)); 700 FpDest = FpOp1.sw; 701 __asm__ __volatile__("" :: "m" (FpDest)); |
702 finishVfp(fpscr, state); 703 Fpscr = fpscr; |
704 ''' 705 vcvtSIntFpSIop = InstObjParams("vcvt", "VcvtSIntFpS", "FpRegRegOp", 706 { "code": vcvtSIntFpSCode, 707 "predicate_test": predicateTest }, []) 708 header_output += FpRegRegOpDeclare.subst(vcvtSIntFpSIop); 709 decoder_output += FpRegRegOpConstructor.subst(vcvtSIntFpSIop); 710 exec_output += PredOpExecute.subst(vcvtSIntFpSIop); 711 712 vcvtSIntFpDCode = ''' |
713 FPSCR fpscr = Fpscr; 714 VfpSavedState state = prepFpState(fpscr.rMode); |
715 __asm__ __volatile__("" : "=m" (FpOp1P0.sw) : "m" (FpOp1P0.sw)); |
716 double cDest = FpOp1P0.sw; 717 __asm__ __volatile__("" :: "m" (cDest)); 718 finishVfp(fpscr, state); 719 Fpscr = fpscr; 720 FpDestP0.uw = dblLow(cDest); 721 FpDestP1.uw = dblHi(cDest); |
722 ''' 723 vcvtSIntFpDIop = InstObjParams("vcvt", "VcvtSIntFpD", "FpRegRegOp", 724 { "code": vcvtSIntFpDCode, 725 "predicate_test": predicateTest }, []) 726 header_output += FpRegRegOpDeclare.subst(vcvtSIntFpDIop); 727 decoder_output += FpRegRegOpConstructor.subst(vcvtSIntFpDIop); 728 exec_output += PredOpExecute.subst(vcvtSIntFpDIop); 729 730 vcvtFpUIntSRCode = ''' |
731 FPSCR fpscr = Fpscr; 732 VfpSavedState state = prepFpState(fpscr.rMode); 733 vfpFlushToZero(fpscr, FpOp1); |
734 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 735 FpDest.uw = vfpFpSToFixed(FpOp1, false, false, 0, false); 736 __asm__ __volatile__("" :: "m" (FpDest.uw)); |
737 finishVfp(fpscr, state); 738 Fpscr = fpscr; |
739 ''' 740 vcvtFpUIntSRIop = InstObjParams("vcvt", "VcvtFpUIntSR", "FpRegRegOp", 741 { "code": vcvtFpUIntSRCode, 742 "predicate_test": predicateTest }, []) 743 header_output += FpRegRegOpDeclare.subst(vcvtFpUIntSRIop); 744 decoder_output += FpRegRegOpConstructor.subst(vcvtFpUIntSRIop); 745 exec_output += PredOpExecute.subst(vcvtFpUIntSRIop); 746 747 vcvtFpUIntDRCode = ''' |
748 FPSCR fpscr = Fpscr; 749 double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw); 750 vfpFlushToZero(fpscr, cOp1); 751 VfpSavedState state = prepFpState(fpscr.rMode); 752 __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); 753 uint64_t result = vfpFpDToFixed(cOp1, false, false, 0, false); |
754 __asm__ __volatile__("" :: "m" (result)); |
755 finishVfp(fpscr, state); 756 Fpscr = fpscr; |
757 FpDestP0.uw = result; 758 ''' 759 vcvtFpUIntDRIop = InstObjParams("vcvtr", "VcvtFpUIntDR", "FpRegRegOp", 760 { "code": vcvtFpUIntDRCode, 761 "predicate_test": predicateTest }, []) 762 header_output += FpRegRegOpDeclare.subst(vcvtFpUIntDRIop); 763 decoder_output += FpRegRegOpConstructor.subst(vcvtFpUIntDRIop); 764 exec_output += PredOpExecute.subst(vcvtFpUIntDRIop); 765 766 vcvtFpSIntSRCode = ''' |
767 FPSCR fpscr = Fpscr; 768 VfpSavedState state = prepFpState(fpscr.rMode); 769 vfpFlushToZero(fpscr, FpOp1); |
770 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 771 FpDest.sw = vfpFpSToFixed(FpOp1, true, false, 0, false); 772 __asm__ __volatile__("" :: "m" (FpDest.sw)); |
773 finishVfp(fpscr, state); 774 Fpscr = fpscr; |
775 ''' 776 vcvtFpSIntSRIop = InstObjParams("vcvtr", "VcvtFpSIntSR", "FpRegRegOp", 777 { "code": vcvtFpSIntSRCode, 778 "predicate_test": predicateTest }, []) 779 header_output += FpRegRegOpDeclare.subst(vcvtFpSIntSRIop); 780 decoder_output += FpRegRegOpConstructor.subst(vcvtFpSIntSRIop); 781 exec_output += PredOpExecute.subst(vcvtFpSIntSRIop); 782 783 vcvtFpSIntDRCode = ''' |
784 FPSCR fpscr = Fpscr; 785 double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw); 786 vfpFlushToZero(fpscr, cOp1); 787 VfpSavedState state = prepFpState(fpscr.rMode); 788 __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); 789 int64_t result = vfpFpDToFixed(cOp1, true, false, 0, false); |
790 __asm__ __volatile__("" :: "m" (result)); |
791 finishVfp(fpscr, state); 792 Fpscr = fpscr; |
793 FpDestP0.uw = result; 794 ''' 795 vcvtFpSIntDRIop = InstObjParams("vcvtr", "VcvtFpSIntDR", "FpRegRegOp", 796 { "code": vcvtFpSIntDRCode, 797 "predicate_test": predicateTest }, []) 798 header_output += FpRegRegOpDeclare.subst(vcvtFpSIntDRIop); 799 decoder_output += FpRegRegOpConstructor.subst(vcvtFpSIntDRIop); 800 exec_output += PredOpExecute.subst(vcvtFpSIntDRIop); 801 802 vcvtFpUIntSCode = ''' |
803 FPSCR fpscr = Fpscr; 804 vfpFlushToZero(fpscr, FpOp1); 805 VfpSavedState state = prepFpState(fpscr.rMode); |
806 fesetround(FeRoundZero); 807 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 808 FpDest.uw = vfpFpSToFixed(FpOp1, false, false, 0); 809 __asm__ __volatile__("" :: "m" (FpDest.uw)); |
810 finishVfp(fpscr, state); 811 Fpscr = fpscr; |
812 ''' 813 vcvtFpUIntSIop = InstObjParams("vcvt", "VcvtFpUIntS", "FpRegRegOp", 814 { "code": vcvtFpUIntSCode, 815 "predicate_test": predicateTest }, []) 816 header_output += FpRegRegOpDeclare.subst(vcvtFpUIntSIop); 817 decoder_output += FpRegRegOpConstructor.subst(vcvtFpUIntSIop); 818 exec_output += PredOpExecute.subst(vcvtFpUIntSIop); 819 820 vcvtFpUIntDCode = ''' |
821 FPSCR fpscr = Fpscr; 822 double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw); 823 vfpFlushToZero(fpscr, cOp1); 824 VfpSavedState state = prepFpState(fpscr.rMode); |
825 fesetround(FeRoundZero); |
826 __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); 827 uint64_t result = vfpFpDToFixed(cOp1, false, false, 0); |
828 __asm__ __volatile__("" :: "m" (result)); |
829 finishVfp(fpscr, state); 830 Fpscr = fpscr; |
831 FpDestP0.uw = result; 832 ''' 833 vcvtFpUIntDIop = InstObjParams("vcvt", "VcvtFpUIntD", "FpRegRegOp", 834 { "code": vcvtFpUIntDCode, 835 "predicate_test": predicateTest }, []) 836 header_output += FpRegRegOpDeclare.subst(vcvtFpUIntDIop); 837 decoder_output += FpRegRegOpConstructor.subst(vcvtFpUIntDIop); 838 exec_output += PredOpExecute.subst(vcvtFpUIntDIop); 839 840 vcvtFpSIntSCode = ''' |
841 FPSCR fpscr = Fpscr; 842 vfpFlushToZero(fpscr, FpOp1); 843 VfpSavedState state = prepFpState(fpscr.rMode); |
844 fesetround(FeRoundZero); 845 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 846 FpDest.sw = vfpFpSToFixed(FpOp1, true, false, 0); 847 __asm__ __volatile__("" :: "m" (FpDest.sw)); |
848 finishVfp(fpscr, state); 849 Fpscr = fpscr; |
850 ''' 851 vcvtFpSIntSIop = InstObjParams("vcvt", "VcvtFpSIntS", "FpRegRegOp", 852 { "code": vcvtFpSIntSCode, 853 "predicate_test": predicateTest }, []) 854 header_output += FpRegRegOpDeclare.subst(vcvtFpSIntSIop); 855 decoder_output += FpRegRegOpConstructor.subst(vcvtFpSIntSIop); 856 exec_output += PredOpExecute.subst(vcvtFpSIntSIop); 857 858 vcvtFpSIntDCode = ''' |
859 FPSCR fpscr = Fpscr; 860 double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw); 861 vfpFlushToZero(fpscr, cOp1); 862 VfpSavedState state = prepFpState(fpscr.rMode); |
863 fesetround(FeRoundZero); |
864 __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); 865 int64_t result = vfpFpDToFixed(cOp1, true, false, 0); |
866 __asm__ __volatile__("" :: "m" (result)); |
867 finishVfp(fpscr, state); 868 Fpscr = fpscr; |
869 FpDestP0.uw = result; 870 ''' 871 vcvtFpSIntDIop = InstObjParams("vcvt", "VcvtFpSIntD", "FpRegRegOp", 872 { "code": vcvtFpSIntDCode, 873 "predicate_test": predicateTest }, []) 874 header_output += FpRegRegOpDeclare.subst(vcvtFpSIntDIop); 875 decoder_output += FpRegRegOpConstructor.subst(vcvtFpSIntDIop); 876 exec_output += PredOpExecute.subst(vcvtFpSIntDIop); 877 878 vcvtFpSFpDCode = ''' |
879 FPSCR fpscr = Fpscr; 880 vfpFlushToZero(fpscr, FpOp1); 881 VfpSavedState state = prepFpState(fpscr.rMode); |
882 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); |
883 double cDest = fixFpSFpDDest(Fpscr, FpOp1); 884 __asm__ __volatile__("" :: "m" (cDest)); 885 finishVfp(fpscr, state); 886 Fpscr = fpscr; 887 FpDestP0.uw = dblLow(cDest); 888 FpDestP1.uw = dblHi(cDest); |
889 ''' 890 vcvtFpSFpDIop = InstObjParams("vcvt", "VcvtFpSFpD", "FpRegRegOp", 891 { "code": vcvtFpSFpDCode, 892 "predicate_test": predicateTest }, []) 893 header_output += FpRegRegOpDeclare.subst(vcvtFpSFpDIop); 894 decoder_output += FpRegRegOpConstructor.subst(vcvtFpSFpDIop); 895 exec_output += PredOpExecute.subst(vcvtFpSFpDIop); 896 897 vcvtFpDFpSCode = ''' |
898 FPSCR fpscr = Fpscr; 899 double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw); 900 vfpFlushToZero(fpscr, cOp1); 901 VfpSavedState state = prepFpState(fpscr.rMode); 902 __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); 903 FpDest = fixFpDFpSDest(Fpscr, cOp1); |
904 __asm__ __volatile__("" :: "m" (FpDest)); |
905 finishVfp(fpscr, state); 906 Fpscr = fpscr; |
907 ''' 908 vcvtFpDFpSIop = InstObjParams("vcvt", "VcvtFpDFpS", "FpRegRegOp", 909 { "code": vcvtFpDFpSCode, 910 "predicate_test": predicateTest }, []) 911 header_output += FpRegRegOpDeclare.subst(vcvtFpDFpSIop); 912 decoder_output += FpRegRegOpConstructor.subst(vcvtFpDFpSIop); 913 exec_output += PredOpExecute.subst(vcvtFpDFpSIop); 914 915 vcmpSCode = ''' |
916 FPSCR fpscr = Fpscr; |
917 vfpFlushToZero(fpscr, FpDest, FpOp1); |
918 if (FpDest == FpOp1) { 919 fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 920 } else if (FpDest < FpOp1) { 921 fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 922 } else if (FpDest > FpOp1) { 923 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 924 } else { 925 const uint32_t qnan = 0x7fc00000; --- 10 unchanged lines hidden (view full) --- 936 vcmpSIop = InstObjParams("vcmps", "VcmpS", "FpRegRegOp", 937 { "code": vcmpSCode, 938 "predicate_test": predicateTest }, []) 939 header_output += FpRegRegOpDeclare.subst(vcmpSIop); 940 decoder_output += FpRegRegOpConstructor.subst(vcmpSIop); 941 exec_output += PredOpExecute.subst(vcmpSIop); 942 943 vcmpDCode = ''' |
944 double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw); 945 double cDest = dbl(FpDestP0.uw, FpDestP1.uw); |
946 FPSCR fpscr = Fpscr; |
947 vfpFlushToZero(fpscr, cDest, cOp1); 948 if (cDest == cOp1) { |
949 fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; |
950 } else if (cDest < cOp1) { |
951 fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; |
952 } else if (cDest > cOp1) { |
953 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 954 } else { 955 const uint64_t qnan = ULL(0x7ff8000000000000); |
956 const bool nan1 = std::isnan(cDest); 957 const bool signal1 = nan1 && ((fpToBits(cDest) & qnan) != qnan); 958 const bool nan2 = std::isnan(cOp1); 959 const bool signal2 = nan2 && ((fpToBits(cOp1) & qnan) != qnan); |
960 if (signal1 || signal2) 961 fpscr.ioc = 1; 962 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 963 } 964 Fpscr = fpscr; 965 ''' 966 vcmpDIop = InstObjParams("vcmpd", "VcmpD", "FpRegRegOp", 967 { "code": vcmpDCode, 968 "predicate_test": predicateTest }, []) 969 header_output += FpRegRegOpDeclare.subst(vcmpDIop); 970 decoder_output += FpRegRegOpConstructor.subst(vcmpDIop); 971 exec_output += PredOpExecute.subst(vcmpDIop); 972 973 vcmpZeroSCode = ''' |
974 FPSCR fpscr = Fpscr; |
975 vfpFlushToZero(fpscr, FpDest); |
976 // This only handles imm == 0 for now. 977 assert(imm == 0); 978 if (FpDest == imm) { 979 fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 980 } else if (FpDest < imm) { 981 fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 982 } else if (FpDest > imm) { 983 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; --- 10 unchanged lines hidden (view full) --- 994 vcmpZeroSIop = InstObjParams("vcmpZeros", "VcmpZeroS", "FpRegImmOp", 995 { "code": vcmpZeroSCode, 996 "predicate_test": predicateTest }, []) 997 header_output += FpRegImmOpDeclare.subst(vcmpZeroSIop); 998 decoder_output += FpRegImmOpConstructor.subst(vcmpZeroSIop); 999 exec_output += PredOpExecute.subst(vcmpZeroSIop); 1000 1001 vcmpZeroDCode = ''' |
1002 // This only handles imm == 0 for now. 1003 assert(imm == 0); |
1004 double cDest = dbl(FpDestP0.uw, FpDestP1.uw); |
1005 FPSCR fpscr = Fpscr; |
1006 vfpFlushToZero(fpscr, cDest); 1007 if (cDest == imm) { |
1008 fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; |
1009 } else if (cDest < imm) { |
1010 fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; |
1011 } else if (cDest > imm) { |
1012 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 1013 } else { 1014 const uint64_t qnan = ULL(0x7ff8000000000000); |
1015 const bool nan = std::isnan(cDest); 1016 const bool signal = nan && ((fpToBits(cDest) & qnan) != qnan); |
1017 if (signal) 1018 fpscr.ioc = 1; 1019 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 1020 } 1021 Fpscr = fpscr; 1022 ''' 1023 vcmpZeroDIop = InstObjParams("vcmpZerod", "VcmpZeroD", "FpRegImmOp", 1024 { "code": vcmpZeroDCode, 1025 "predicate_test": predicateTest }, []) 1026 header_output += FpRegImmOpDeclare.subst(vcmpZeroDIop); 1027 decoder_output += FpRegImmOpConstructor.subst(vcmpZeroDIop); 1028 exec_output += PredOpExecute.subst(vcmpZeroDIop); 1029 1030 vcmpeSCode = ''' |
1031 FPSCR fpscr = Fpscr; |
1032 vfpFlushToZero(fpscr, FpDest, FpOp1); |
1033 if (FpDest == FpOp1) { 1034 fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 1035 } else if (FpDest < FpOp1) { 1036 fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 1037 } else if (FpDest > FpOp1) { 1038 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 1039 } else { 1040 fpscr.ioc = 1; --- 4 unchanged lines hidden (view full) --- 1045 vcmpeSIop = InstObjParams("vcmpes", "VcmpeS", "FpRegRegOp", 1046 { "code": vcmpeSCode, 1047 "predicate_test": predicateTest }, []) 1048 header_output += FpRegRegOpDeclare.subst(vcmpeSIop); 1049 decoder_output += FpRegRegOpConstructor.subst(vcmpeSIop); 1050 exec_output += PredOpExecute.subst(vcmpeSIop); 1051 1052 vcmpeDCode = ''' |
1053 double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw); 1054 double cDest = dbl(FpDestP0.uw, FpDestP1.uw); |
1055 FPSCR fpscr = Fpscr; |
1056 vfpFlushToZero(fpscr, cDest, cOp1); 1057 if (cDest == cOp1) { |
1058 fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; |
1059 } else if (cDest < cOp1) { |
1060 fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; |
1061 } else if (cDest > cOp1) { |
1062 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 1063 } else { 1064 fpscr.ioc = 1; 1065 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 1066 } 1067 Fpscr = fpscr; 1068 ''' 1069 vcmpeDIop = InstObjParams("vcmped", "VcmpeD", "FpRegRegOp", 1070 { "code": vcmpeDCode, 1071 "predicate_test": predicateTest }, []) 1072 header_output += FpRegRegOpDeclare.subst(vcmpeDIop); 1073 decoder_output += FpRegRegOpConstructor.subst(vcmpeDIop); 1074 exec_output += PredOpExecute.subst(vcmpeDIop); 1075 1076 vcmpeZeroSCode = ''' |
1077 FPSCR fpscr = Fpscr; |
1078 vfpFlushToZero(fpscr, FpDest); |
1079 if (FpDest == imm) { 1080 fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 1081 } else if (FpDest < imm) { 1082 fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 1083 } else if (FpDest > imm) { 1084 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 1085 } else { 1086 fpscr.ioc = 1; --- 4 unchanged lines hidden (view full) --- 1091 vcmpeZeroSIop = InstObjParams("vcmpeZeros", "VcmpeZeroS", "FpRegImmOp", 1092 { "code": vcmpeZeroSCode, 1093 "predicate_test": predicateTest }, []) 1094 header_output += FpRegImmOpDeclare.subst(vcmpeZeroSIop); 1095 decoder_output += FpRegImmOpConstructor.subst(vcmpeZeroSIop); 1096 exec_output += PredOpExecute.subst(vcmpeZeroSIop); 1097 1098 vcmpeZeroDCode = ''' |
1099 double cDest = dbl(FpDestP0.uw, FpDestP1.uw); |
1100 FPSCR fpscr = Fpscr; |
1101 vfpFlushToZero(fpscr, cDest); 1102 if (cDest == imm) { |
1103 fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; |
1104 } else if (cDest < imm) { |
1105 fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; |
1106 } else if (cDest > imm) { |
1107 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 1108 } else { 1109 fpscr.ioc = 1; 1110 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 1111 } 1112 Fpscr = fpscr; 1113 ''' 1114 vcmpeZeroDIop = InstObjParams("vcmpeZerod", "VcmpeZeroD", "FpRegImmOp", --- 6 unchanged lines hidden (view full) --- 1121 1122let {{ 1123 1124 header_output = "" 1125 decoder_output = "" 1126 exec_output = "" 1127 1128 vcvtFpSFixedSCode = ''' |
1129 FPSCR fpscr = Fpscr; 1130 vfpFlushToZero(fpscr, FpOp1); 1131 VfpSavedState state = prepFpState(fpscr.rMode); |
1132 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 1133 FpDest.sw = vfpFpSToFixed(FpOp1, true, false, imm); 1134 __asm__ __volatile__("" :: "m" (FpDest.sw)); |
1135 finishVfp(fpscr, state); 1136 Fpscr = fpscr; |
1137 ''' 1138 vcvtFpSFixedSIop = InstObjParams("vcvt", "VcvtFpSFixedS", "FpRegRegImmOp", 1139 { "code": vcvtFpSFixedSCode, 1140 "predicate_test": predicateTest }, []) 1141 header_output += FpRegRegImmOpDeclare.subst(vcvtFpSFixedSIop); 1142 decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpSFixedSIop); 1143 exec_output += PredOpExecute.subst(vcvtFpSFixedSIop); 1144 1145 vcvtFpSFixedDCode = ''' |
1146 FPSCR fpscr = Fpscr; 1147 double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw); 1148 vfpFlushToZero(fpscr, cOp1); 1149 VfpSavedState state = prepFpState(fpscr.rMode); 1150 __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); 1151 uint64_t mid = vfpFpDToFixed(cOp1, true, false, imm); |
1152 __asm__ __volatile__("" :: "m" (mid)); |
1153 finishVfp(fpscr, state); 1154 Fpscr = fpscr; |
1155 FpDestP0.uw = mid; 1156 FpDestP1.uw = mid >> 32; 1157 ''' 1158 vcvtFpSFixedDIop = InstObjParams("vcvt", "VcvtFpSFixedD", "FpRegRegImmOp", 1159 { "code": vcvtFpSFixedDCode, 1160 "predicate_test": predicateTest }, []) 1161 header_output += FpRegRegImmOpDeclare.subst(vcvtFpSFixedDIop); 1162 decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpSFixedDIop); 1163 exec_output += PredOpExecute.subst(vcvtFpSFixedDIop); 1164 1165 vcvtFpUFixedSCode = ''' |
1166 FPSCR fpscr = Fpscr; 1167 vfpFlushToZero(fpscr, FpOp1); 1168 VfpSavedState state = prepFpState(fpscr.rMode); |
1169 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 1170 FpDest.uw = vfpFpSToFixed(FpOp1, false, false, imm); 1171 __asm__ __volatile__("" :: "m" (FpDest.uw)); |
1172 finishVfp(fpscr, state); 1173 Fpscr = fpscr; |
1174 ''' 1175 vcvtFpUFixedSIop = InstObjParams("vcvt", "VcvtFpUFixedS", "FpRegRegImmOp", 1176 { "code": vcvtFpUFixedSCode, 1177 "predicate_test": predicateTest }, []) 1178 header_output += FpRegRegImmOpDeclare.subst(vcvtFpUFixedSIop); 1179 decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpUFixedSIop); 1180 exec_output += PredOpExecute.subst(vcvtFpUFixedSIop); 1181 1182 vcvtFpUFixedDCode = ''' |
1183 FPSCR fpscr = Fpscr; 1184 double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw); 1185 vfpFlushToZero(fpscr, cOp1); 1186 VfpSavedState state = prepFpState(fpscr.rMode); 1187 __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); 1188 uint64_t mid = vfpFpDToFixed(cOp1, false, false, imm); |
1189 __asm__ __volatile__("" :: "m" (mid)); |
1190 finishVfp(fpscr, state); 1191 Fpscr = fpscr; |
1192 FpDestP0.uw = mid; 1193 FpDestP1.uw = mid >> 32; 1194 ''' 1195 vcvtFpUFixedDIop = InstObjParams("vcvt", "VcvtFpUFixedD", "FpRegRegImmOp", 1196 { "code": vcvtFpUFixedDCode, 1197 "predicate_test": predicateTest }, []) 1198 header_output += FpRegRegImmOpDeclare.subst(vcvtFpUFixedDIop); 1199 decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpUFixedDIop); 1200 exec_output += PredOpExecute.subst(vcvtFpUFixedDIop); 1201 1202 vcvtSFixedFpSCode = ''' |
1203 FPSCR fpscr = Fpscr; 1204 VfpSavedState state = prepFpState(fpscr.rMode); |
1205 __asm__ __volatile__("" : "=m" (FpOp1.sw) : "m" (FpOp1.sw)); 1206 FpDest = vfpSFixedToFpS(Fpscr, FpOp1.sw, false, imm); 1207 __asm__ __volatile__("" :: "m" (FpDest)); |
1208 finishVfp(fpscr, state); 1209 Fpscr = fpscr; |
1210 ''' 1211 vcvtSFixedFpSIop = InstObjParams("vcvt", "VcvtSFixedFpS", "FpRegRegImmOp", 1212 { "code": vcvtSFixedFpSCode, 1213 "predicate_test": predicateTest }, []) 1214 header_output += FpRegRegImmOpDeclare.subst(vcvtSFixedFpSIop); 1215 decoder_output += FpRegRegImmOpConstructor.subst(vcvtSFixedFpSIop); 1216 exec_output += PredOpExecute.subst(vcvtSFixedFpSIop); 1217 1218 vcvtSFixedFpDCode = ''' |
1219 FPSCR fpscr = Fpscr; |
1220 uint64_t mid = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); |
1221 VfpSavedState state = prepFpState(fpscr.rMode); |
1222 __asm__ __volatile__("" : "=m" (mid) : "m" (mid)); |
1223 double cDest = vfpSFixedToFpD(Fpscr, mid, false, imm); 1224 __asm__ __volatile__("" :: "m" (cDest)); 1225 finishVfp(fpscr, state); 1226 Fpscr = fpscr; 1227 FpDestP0.uw = dblLow(cDest); 1228 FpDestP1.uw = dblHi(cDest); |
1229 ''' 1230 vcvtSFixedFpDIop = InstObjParams("vcvt", "VcvtSFixedFpD", "FpRegRegImmOp", 1231 { "code": vcvtSFixedFpDCode, 1232 "predicate_test": predicateTest }, []) 1233 header_output += FpRegRegImmOpDeclare.subst(vcvtSFixedFpDIop); 1234 decoder_output += FpRegRegImmOpConstructor.subst(vcvtSFixedFpDIop); 1235 exec_output += PredOpExecute.subst(vcvtSFixedFpDIop); 1236 1237 vcvtUFixedFpSCode = ''' |
1238 FPSCR fpscr = Fpscr; 1239 VfpSavedState state = prepFpState(fpscr.rMode); |
1240 __asm__ __volatile__("" : "=m" (FpOp1.uw) : "m" (FpOp1.uw)); 1241 FpDest = vfpUFixedToFpS(Fpscr, FpOp1.uw, false, imm); 1242 __asm__ __volatile__("" :: "m" (FpDest)); |
1243 finishVfp(fpscr, state); 1244 Fpscr = fpscr; |
1245 ''' 1246 vcvtUFixedFpSIop = InstObjParams("vcvt", "VcvtUFixedFpS", "FpRegRegImmOp", 1247 { "code": vcvtUFixedFpSCode, 1248 "predicate_test": predicateTest }, []) 1249 header_output += FpRegRegImmOpDeclare.subst(vcvtUFixedFpSIop); 1250 decoder_output += FpRegRegImmOpConstructor.subst(vcvtUFixedFpSIop); 1251 exec_output += PredOpExecute.subst(vcvtUFixedFpSIop); 1252 1253 vcvtUFixedFpDCode = ''' |
1254 FPSCR fpscr = Fpscr; |
1255 uint64_t mid = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); |
1256 VfpSavedState state = prepFpState(fpscr.rMode); |
1257 __asm__ __volatile__("" : "=m" (mid) : "m" (mid)); |
1258 double cDest = vfpUFixedToFpD(Fpscr, mid, false, imm); 1259 __asm__ __volatile__("" :: "m" (cDest)); 1260 finishVfp(fpscr, state); 1261 Fpscr = fpscr; 1262 FpDestP0.uw = dblLow(cDest); 1263 FpDestP1.uw = dblHi(cDest); |
1264 ''' 1265 vcvtUFixedFpDIop = InstObjParams("vcvt", "VcvtUFixedFpD", "FpRegRegImmOp", 1266 { "code": vcvtUFixedFpDCode, 1267 "predicate_test": predicateTest }, []) 1268 header_output += FpRegRegImmOpDeclare.subst(vcvtUFixedFpDIop); 1269 decoder_output += FpRegRegImmOpConstructor.subst(vcvtUFixedFpDIop); 1270 exec_output += PredOpExecute.subst(vcvtUFixedFpDIop); 1271 1272 vcvtFpSHFixedSCode = ''' |
1273 FPSCR fpscr = Fpscr; 1274 vfpFlushToZero(fpscr, FpOp1); 1275 VfpSavedState state = prepFpState(fpscr.rMode); |
1276 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 1277 FpDest.sh = vfpFpSToFixed(FpOp1, true, true, imm); 1278 __asm__ __volatile__("" :: "m" (FpDest.sh)); |
1279 finishVfp(fpscr, state); 1280 Fpscr = fpscr; |
1281 ''' 1282 vcvtFpSHFixedSIop = InstObjParams("vcvt", "VcvtFpSHFixedS", 1283 "FpRegRegImmOp", 1284 { "code": vcvtFpSHFixedSCode, 1285 "predicate_test": predicateTest }, []) 1286 header_output += FpRegRegImmOpDeclare.subst(vcvtFpSHFixedSIop); 1287 decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpSHFixedSIop); 1288 exec_output += PredOpExecute.subst(vcvtFpSHFixedSIop); 1289 1290 vcvtFpSHFixedDCode = ''' |
1291 FPSCR fpscr = Fpscr; 1292 double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw); 1293 vfpFlushToZero(fpscr, cOp1); 1294 VfpSavedState state = prepFpState(fpscr.rMode); 1295 __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); 1296 uint64_t result = vfpFpDToFixed(cOp1, true, true, imm); |
1297 __asm__ __volatile__("" :: "m" (result)); |
1298 finishVfp(fpscr, state); 1299 Fpscr = fpscr; |
1300 FpDestP0.uw = result; 1301 FpDestP1.uw = result >> 32; 1302 ''' 1303 vcvtFpSHFixedDIop = InstObjParams("vcvt", "VcvtFpSHFixedD", 1304 "FpRegRegImmOp", 1305 { "code": vcvtFpSHFixedDCode, 1306 "predicate_test": predicateTest }, []) 1307 header_output += FpRegRegImmOpDeclare.subst(vcvtFpSHFixedDIop); 1308 decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpSHFixedDIop); 1309 exec_output += PredOpExecute.subst(vcvtFpSHFixedDIop); 1310 1311 vcvtFpUHFixedSCode = ''' |
1312 FPSCR fpscr = Fpscr; 1313 vfpFlushToZero(fpscr, FpOp1); 1314 VfpSavedState state = prepFpState(fpscr.rMode); |
1315 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 1316 FpDest.uh = vfpFpSToFixed(FpOp1, false, true, imm); 1317 __asm__ __volatile__("" :: "m" (FpDest.uh)); |
1318 finishVfp(fpscr, state); 1319 Fpscr = fpscr; |
1320 ''' 1321 vcvtFpUHFixedSIop = InstObjParams("vcvt", "VcvtFpUHFixedS", 1322 "FpRegRegImmOp", 1323 { "code": vcvtFpUHFixedSCode, 1324 "predicate_test": predicateTest }, []) 1325 header_output += FpRegRegImmOpDeclare.subst(vcvtFpUHFixedSIop); 1326 decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpUHFixedSIop); 1327 exec_output += PredOpExecute.subst(vcvtFpUHFixedSIop); 1328 1329 vcvtFpUHFixedDCode = ''' |
1330 FPSCR fpscr = Fpscr; 1331 double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw); 1332 vfpFlushToZero(fpscr, cOp1); 1333 VfpSavedState state = prepFpState(fpscr.rMode); 1334 __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); 1335 uint64_t mid = vfpFpDToFixed(cOp1, false, true, imm); |
1336 __asm__ __volatile__("" :: "m" (mid)); |
1337 finishVfp(fpscr, state); 1338 Fpscr = fpscr; |
1339 FpDestP0.uw = mid; 1340 FpDestP1.uw = mid >> 32; 1341 ''' 1342 vcvtFpUHFixedDIop = InstObjParams("vcvt", "VcvtFpUHFixedD", 1343 "FpRegRegImmOp", 1344 { "code": vcvtFpUHFixedDCode, 1345 "predicate_test": predicateTest }, []) 1346 header_output += FpRegRegImmOpDeclare.subst(vcvtFpUHFixedDIop); 1347 decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpUHFixedDIop); 1348 exec_output += PredOpExecute.subst(vcvtFpUHFixedDIop); 1349 1350 vcvtSHFixedFpSCode = ''' |
1351 FPSCR fpscr = Fpscr; 1352 VfpSavedState state = prepFpState(fpscr.rMode); |
1353 __asm__ __volatile__("" : "=m" (FpOp1.sh) : "m" (FpOp1.sh)); 1354 FpDest = vfpSFixedToFpS(Fpscr, FpOp1.sh, true, imm); 1355 __asm__ __volatile__("" :: "m" (FpDest)); |
1356 finishVfp(fpscr, state); 1357 Fpscr = fpscr; |
1358 ''' 1359 vcvtSHFixedFpSIop = InstObjParams("vcvt", "VcvtSHFixedFpS", 1360 "FpRegRegImmOp", 1361 { "code": vcvtSHFixedFpSCode, 1362 "predicate_test": predicateTest }, []) 1363 header_output += FpRegRegImmOpDeclare.subst(vcvtSHFixedFpSIop); 1364 decoder_output += FpRegRegImmOpConstructor.subst(vcvtSHFixedFpSIop); 1365 exec_output += PredOpExecute.subst(vcvtSHFixedFpSIop); 1366 1367 vcvtSHFixedFpDCode = ''' |
1368 FPSCR fpscr = Fpscr; |
1369 uint64_t mid = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); |
1370 VfpSavedState state = prepFpState(fpscr.rMode); |
1371 __asm__ __volatile__("" : "=m" (mid) : "m" (mid)); |
1372 double cDest = vfpSFixedToFpD(Fpscr, mid, true, imm); 1373 __asm__ __volatile__("" :: "m" (cDest)); 1374 finishVfp(fpscr, state); 1375 Fpscr = fpscr; 1376 FpDestP0.uw = dblLow(cDest); 1377 FpDestP1.uw = dblHi(cDest); |
1378 ''' 1379 vcvtSHFixedFpDIop = InstObjParams("vcvt", "VcvtSHFixedFpD", 1380 "FpRegRegImmOp", 1381 { "code": vcvtSHFixedFpDCode, 1382 "predicate_test": predicateTest }, []) 1383 header_output += FpRegRegImmOpDeclare.subst(vcvtSHFixedFpDIop); 1384 decoder_output += FpRegRegImmOpConstructor.subst(vcvtSHFixedFpDIop); 1385 exec_output += PredOpExecute.subst(vcvtSHFixedFpDIop); 1386 1387 vcvtUHFixedFpSCode = ''' |
1388 FPSCR fpscr = Fpscr; 1389 VfpSavedState state = prepFpState(fpscr.rMode); |
1390 __asm__ __volatile__("" : "=m" (FpOp1.uh) : "m" (FpOp1.uh)); 1391 FpDest = vfpUFixedToFpS(Fpscr, FpOp1.uh, true, imm); 1392 __asm__ __volatile__("" :: "m" (FpDest)); |
1393 finishVfp(fpscr, state); 1394 Fpscr = fpscr; |
1395 ''' 1396 vcvtUHFixedFpSIop = InstObjParams("vcvt", "VcvtUHFixedFpS", 1397 "FpRegRegImmOp", 1398 { "code": vcvtUHFixedFpSCode, 1399 "predicate_test": predicateTest }, []) 1400 header_output += FpRegRegImmOpDeclare.subst(vcvtUHFixedFpSIop); 1401 decoder_output += FpRegRegImmOpConstructor.subst(vcvtUHFixedFpSIop); 1402 exec_output += PredOpExecute.subst(vcvtUHFixedFpSIop); 1403 1404 vcvtUHFixedFpDCode = ''' |
1405 FPSCR fpscr = Fpscr; |
1406 uint64_t mid = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); |
1407 VfpSavedState state = prepFpState(fpscr.rMode); |
1408 __asm__ __volatile__("" : "=m" (mid) : "m" (mid)); |
1409 double cDest = vfpUFixedToFpD(Fpscr, mid, true, imm); 1410 __asm__ __volatile__("" :: "m" (cDest)); 1411 finishVfp(fpscr, state); 1412 Fpscr = fpscr; 1413 FpDestP0.uw = dblLow(cDest); 1414 FpDestP1.uw = dblHi(cDest); |
1415 ''' 1416 vcvtUHFixedFpDIop = InstObjParams("vcvt", "VcvtUHFixedFpD", 1417 "FpRegRegImmOp", 1418 { "code": vcvtUHFixedFpDCode, 1419 "predicate_test": predicateTest }, []) 1420 header_output += FpRegRegImmOpDeclare.subst(vcvtUHFixedFpDIop); 1421 decoder_output += FpRegRegImmOpConstructor.subst(vcvtUHFixedFpDIop); 1422 exec_output += PredOpExecute.subst(vcvtUHFixedFpDIop); 1423}}; |