1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating --- 360 unchanged lines hidden (view full) --- 369 Op1.uw = FpOp2P1.uw; 370 ''' 371 vmov2Core2RegIop = InstObjParams("vmov", "Vmov2Core2Reg", "VfpRegRegRegOp", 372 { "code": vmov2Core2RegCode, 373 "predicate_test": predicateTest }, []) 374 header_output += VfpRegRegRegOpDeclare.subst(vmov2Core2RegIop); 375 decoder_output += VfpRegRegRegOpConstructor.subst(vmov2Core2RegIop); 376 exec_output += PredOpExecute.subst(vmov2Core2RegIop); |
377}}; |
378 |
379let {{ 380 381 header_output = "" 382 decoder_output = "" 383 exec_output = "" 384 |
385 vmulSCode = ''' 386 VfpSavedState state = prepVfpFpscr(Fpscr); |
387 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); |
388 FpDest = FpOp1 * FpOp2; |
389 __asm__ __volatile__("" :: "m" (FpDest)); |
390 Fpscr = setVfpFpscr(Fpscr, state); 391 if ((isinf(FpOp1) && FpOp2 == 0) || (isinf(FpOp2) && FpOp1 == 0)) { 392 FpDest = NAN; 393 } 394 ''' 395 vmulSIop = InstObjParams("vmuls", "VmulS", "VfpRegRegRegOp", 396 { "code": vmulSCode, 397 "predicate_test": predicateTest }, []) 398 header_output += VfpRegRegRegOpDeclare.subst(vmulSIop); 399 decoder_output += VfpRegRegRegOpConstructor.subst(vmulSIop); 400 exec_output += PredOpExecute.subst(vmulSIop); 401 402 vmulDCode = ''' 403 IntDoubleUnion cOp1, cOp2, cDest; 404 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 405 cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32)); 406 VfpSavedState state = prepVfpFpscr(Fpscr); |
407 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp)); |
408 cDest.fp = cOp1.fp * cOp2.fp; |
409 __asm__ __volatile__("" :: "m" (cDest.fp)); |
410 Fpscr = setVfpFpscr(Fpscr, state); 411 if ((isinf(cOp1.fp) && cOp2.fp == 0) || 412 (isinf(cOp2.fp) && cOp1.fp == 0)) { 413 cDest.fp = NAN; 414 } 415 FpDestP0.uw = cDest.bits; 416 FpDestP1.uw = cDest.bits >> 32; 417 ''' --- 49 unchanged lines hidden (view full) --- 467 { "code": vabsDCode, 468 "predicate_test": predicateTest }, []) 469 header_output += VfpRegRegOpDeclare.subst(vabsDIop); 470 decoder_output += VfpRegRegOpConstructor.subst(vabsDIop); 471 exec_output += PredOpExecute.subst(vabsDIop); 472 473 vaddSCode = ''' 474 VfpSavedState state = prepVfpFpscr(Fpscr); |
475 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); |
476 FpDest = FpOp1 + FpOp2; |
477 __asm__ __volatile__("" :: "m" (FpDest)); |
478 Fpscr = setVfpFpscr(Fpscr, state); 479 ''' 480 vaddSIop = InstObjParams("vadds", "VaddS", "VfpRegRegRegOp", 481 { "code": vaddSCode, 482 "predicate_test": predicateTest }, []) 483 header_output += VfpRegRegRegOpDeclare.subst(vaddSIop); 484 decoder_output += VfpRegRegRegOpConstructor.subst(vaddSIop); 485 exec_output += PredOpExecute.subst(vaddSIop); 486 487 vaddDCode = ''' 488 IntDoubleUnion cOp1, cOp2, cDest; 489 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 490 cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32)); 491 VfpSavedState state = prepVfpFpscr(Fpscr); |
492 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp)); |
493 cDest.fp = cOp1.fp + cOp2.fp; |
494 __asm__ __volatile__("" :: "m" (cDest.fp)); |
495 Fpscr = setVfpFpscr(Fpscr, state); 496 FpDestP0.uw = cDest.bits; 497 FpDestP1.uw = cDest.bits >> 32; 498 ''' 499 vaddDIop = InstObjParams("vaddd", "VaddD", "VfpRegRegRegOp", 500 { "code": vaddDCode, 501 "predicate_test": predicateTest }, []) 502 header_output += VfpRegRegRegOpDeclare.subst(vaddDIop); 503 decoder_output += VfpRegRegRegOpConstructor.subst(vaddDIop); 504 exec_output += PredOpExecute.subst(vaddDIop); 505 506 vsubSCode = ''' 507 VfpSavedState state = prepVfpFpscr(Fpscr); |
508 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); |
509 FpDest = FpOp1 - FpOp2; |
510 __asm__ __volatile__("" :: "m" (FpDest)); |
511 Fpscr = setVfpFpscr(Fpscr, state) 512 ''' 513 vsubSIop = InstObjParams("vsubs", "VsubS", "VfpRegRegRegOp", 514 { "code": vsubSCode, 515 "predicate_test": predicateTest }, []) 516 header_output += VfpRegRegRegOpDeclare.subst(vsubSIop); 517 decoder_output += VfpRegRegRegOpConstructor.subst(vsubSIop); 518 exec_output += PredOpExecute.subst(vsubSIop); 519 520 vsubDCode = ''' 521 IntDoubleUnion cOp1, cOp2, cDest; 522 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 523 cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32)); 524 VfpSavedState state = prepVfpFpscr(Fpscr); |
525 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp)); |
526 cDest.fp = cOp1.fp - cOp2.fp; |
527 __asm__ __volatile__("" :: "m" (cDest.fp)); |
528 Fpscr = setVfpFpscr(Fpscr, state); 529 FpDestP0.uw = cDest.bits; 530 FpDestP1.uw = cDest.bits >> 32; 531 ''' 532 vsubDIop = InstObjParams("vsubd", "VsubD", "VfpRegRegRegOp", 533 { "code": vsubDCode, 534 "predicate_test": predicateTest }, []) 535 header_output += VfpRegRegRegOpDeclare.subst(vsubDIop); 536 decoder_output += VfpRegRegRegOpConstructor.subst(vsubDIop); 537 exec_output += PredOpExecute.subst(vsubDIop); 538 539 vdivSCode = ''' 540 VfpSavedState state = prepVfpFpscr(Fpscr); |
541 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); |
542 FpDest = FpOp1 / FpOp2; |
543 __asm__ __volatile__("" :: "m" (FpDest)); |
544 Fpscr = setVfpFpscr(Fpscr, state); 545 ''' 546 vdivSIop = InstObjParams("vdivs", "VdivS", "VfpRegRegRegOp", 547 { "code": vdivSCode, 548 "predicate_test": predicateTest }, []) 549 header_output += VfpRegRegRegOpDeclare.subst(vdivSIop); 550 decoder_output += VfpRegRegRegOpConstructor.subst(vdivSIop); 551 exec_output += PredOpExecute.subst(vdivSIop); 552 553 vdivDCode = ''' 554 IntDoubleUnion cOp1, cOp2, cDest; 555 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 556 cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32)); 557 VfpSavedState state = prepVfpFpscr(Fpscr); |
558 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cDest.fp)); |
559 cDest.fp = cOp1.fp / cOp2.fp; |
560 __asm__ __volatile__("" :: "m" (cDest.fp)); |
561 Fpscr = setVfpFpscr(Fpscr, state); 562 FpDestP0.uw = cDest.bits; 563 FpDestP1.uw = cDest.bits >> 32; 564 ''' 565 vdivDIop = InstObjParams("vdivd", "VdivD", "VfpRegRegRegOp", 566 { "code": vdivDCode, 567 "predicate_test": predicateTest }, []) 568 header_output += VfpRegRegRegOpDeclare.subst(vdivDIop); 569 decoder_output += VfpRegRegRegOpConstructor.subst(vdivDIop); 570 exec_output += PredOpExecute.subst(vdivDIop); 571 572 vsqrtSCode = ''' 573 VfpSavedState state = prepVfpFpscr(Fpscr); |
574 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); |
575 FpDest = sqrtf(FpOp1); |
576 __asm__ __volatile__("" :: "m" (FpDest)); |
577 Fpscr = setVfpFpscr(Fpscr, state); 578 if (FpOp1 < 0) { 579 FpDest = NAN; 580 } 581 ''' 582 vsqrtSIop = InstObjParams("vsqrts", "VsqrtS", "VfpRegRegOp", 583 { "code": vsqrtSCode, 584 "predicate_test": predicateTest }, []) 585 header_output += VfpRegRegOpDeclare.subst(vsqrtSIop); 586 decoder_output += VfpRegRegOpConstructor.subst(vsqrtSIop); 587 exec_output += PredOpExecute.subst(vsqrtSIop); 588 589 vsqrtDCode = ''' 590 IntDoubleUnion cOp1, cDest; 591 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 592 VfpSavedState state = prepVfpFpscr(Fpscr); |
593 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cDest.fp)); |
594 cDest.fp = sqrt(cOp1.fp); |
595 __asm__ __volatile__("" :: "m" (cDest.fp)); |
596 Fpscr = setVfpFpscr(Fpscr, state); 597 if (cOp1.fp < 0) { 598 cDest.fp = NAN; 599 } 600 FpDestP0.uw = cDest.bits; 601 FpDestP1.uw = cDest.bits >> 32; 602 ''' 603 vsqrtDIop = InstObjParams("vsqrtd", "VsqrtD", "VfpRegRegOp", 604 { "code": vsqrtDCode, 605 "predicate_test": predicateTest }, []) 606 header_output += VfpRegRegOpDeclare.subst(vsqrtDIop); 607 decoder_output += VfpRegRegOpConstructor.subst(vsqrtDIop); 608 exec_output += PredOpExecute.subst(vsqrtDIop); |
609}}; |
610 |
611let {{ 612 613 header_output = "" 614 decoder_output = "" 615 exec_output = "" 616 |
617 vmlaSCode = ''' 618 VfpSavedState state = prepVfpFpscr(Fpscr); |
619 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); |
620 float mid = FpOp1 * FpOp2; 621 if ((isinf(FpOp1) && FpOp2 == 0) || (isinf(FpOp2) && FpOp1 == 0)) { 622 mid = NAN; 623 } 624 FpDest = FpDest + mid; |
625 __asm__ __volatile__("" :: "m" (FpDest)); |
626 Fpscr = setVfpFpscr(Fpscr, state); 627 ''' 628 vmlaSIop = InstObjParams("vmlas", "VmlaS", "VfpRegRegRegOp", 629 { "code": vmlaSCode, 630 "predicate_test": predicateTest }, []) 631 header_output += VfpRegRegRegOpDeclare.subst(vmlaSIop); 632 decoder_output += VfpRegRegRegOpConstructor.subst(vmlaSIop); 633 exec_output += PredOpExecute.subst(vmlaSIop); 634 635 vmlaDCode = ''' 636 IntDoubleUnion cOp1, cOp2, cDest; 637 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 638 cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32)); 639 cDest.bits = ((uint64_t)FpDestP0.uw | ((uint64_t)FpDestP1.uw << 32)); 640 VfpSavedState state = prepVfpFpscr(Fpscr); |
641 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp)); |
642 double mid = cOp1.fp * cOp2.fp; 643 if ((isinf(cOp1.fp) && cOp2.fp == 0) || 644 (isinf(cOp2.fp) && cOp1.fp == 0)) { 645 mid = NAN; 646 } 647 cDest.fp = cDest.fp + mid; |
648 __asm__ __volatile__("" :: "m" (cDest.fp)); |
649 Fpscr = setVfpFpscr(Fpscr, state); 650 FpDestP0.uw = cDest.bits; 651 FpDestP1.uw = cDest.bits >> 32; 652 ''' 653 vmlaDIop = InstObjParams("vmlad", "VmlaD", "VfpRegRegRegOp", 654 { "code": vmlaDCode, 655 "predicate_test": predicateTest }, []) 656 header_output += VfpRegRegRegOpDeclare.subst(vmlaDIop); 657 decoder_output += VfpRegRegRegOpConstructor.subst(vmlaDIop); 658 exec_output += PredOpExecute.subst(vmlaDIop); 659 660 vmlsSCode = ''' 661 VfpSavedState state = prepVfpFpscr(Fpscr); |
662 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); |
663 float mid = FpOp1 * FpOp2; 664 if ((isinf(FpOp1) && FpOp2 == 0) || (isinf(FpOp2) && FpOp1 == 0)) { 665 mid = NAN; 666 } 667 FpDest = FpDest - mid; |
668 __asm__ __volatile__("" :: "m" (FpDest)); |
669 Fpscr = setVfpFpscr(Fpscr, state); 670 ''' 671 vmlsSIop = InstObjParams("vmlss", "VmlsS", "VfpRegRegRegOp", 672 { "code": vmlsSCode, 673 "predicate_test": predicateTest }, []) 674 header_output += VfpRegRegRegOpDeclare.subst(vmlsSIop); 675 decoder_output += VfpRegRegRegOpConstructor.subst(vmlsSIop); 676 exec_output += PredOpExecute.subst(vmlsSIop); 677 678 vmlsDCode = ''' 679 IntDoubleUnion cOp1, cOp2, cDest; 680 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 681 cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32)); 682 cDest.bits = ((uint64_t)FpDestP0.uw | ((uint64_t)FpDestP1.uw << 32)); 683 VfpSavedState state = prepVfpFpscr(Fpscr); |
684 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp)); |
685 double mid = cOp1.fp * cOp2.fp; 686 if ((isinf(cOp1.fp) && cOp2.fp == 0) || 687 (isinf(cOp2.fp) && cOp1.fp == 0)) { 688 mid = NAN; 689 } 690 cDest.fp = cDest.fp - mid; |
691 __asm__ __volatile__("" :: "m" (cDest.fp)); |
692 Fpscr = setVfpFpscr(Fpscr, state); 693 FpDestP0.uw = cDest.bits; 694 FpDestP1.uw = cDest.bits >> 32; 695 ''' 696 vmlsDIop = InstObjParams("vmlsd", "VmlsD", "VfpRegRegRegOp", 697 { "code": vmlsDCode, 698 "predicate_test": predicateTest }, []) 699 header_output += VfpRegRegRegOpDeclare.subst(vmlsDIop); 700 decoder_output += VfpRegRegRegOpConstructor.subst(vmlsDIop); 701 exec_output += PredOpExecute.subst(vmlsDIop); 702 703 vnmlaSCode = ''' 704 VfpSavedState state = prepVfpFpscr(Fpscr); |
705 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); |
706 float mid = FpOp1 * FpOp2; 707 if ((isinf(FpOp1) && FpOp2 == 0) || (isinf(FpOp2) && FpOp1 == 0)) { 708 mid = NAN; 709 } 710 FpDest = -FpDest - mid; |
711 __asm__ __volatile__("" :: "m" (FpDest)); |
712 Fpscr = setVfpFpscr(Fpscr, state); 713 ''' 714 vnmlaSIop = InstObjParams("vnmlas", "VnmlaS", "VfpRegRegRegOp", 715 { "code": vnmlaSCode, 716 "predicate_test": predicateTest }, []) 717 header_output += VfpRegRegRegOpDeclare.subst(vnmlaSIop); 718 decoder_output += VfpRegRegRegOpConstructor.subst(vnmlaSIop); 719 exec_output += PredOpExecute.subst(vnmlaSIop); 720 721 vnmlaDCode = ''' 722 IntDoubleUnion cOp1, cOp2, cDest; 723 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 724 cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32)); 725 cDest.bits = ((uint64_t)FpDestP0.uw | ((uint64_t)FpDestP1.uw << 32)); 726 VfpSavedState state = prepVfpFpscr(Fpscr); |
727 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp)); |
728 double mid = cOp1.fp * cOp2.fp; 729 if ((isinf(cOp1.fp) && cOp2.fp == 0) || 730 (isinf(cOp2.fp) && cOp1.fp == 0)) { 731 mid = NAN; 732 } 733 cDest.fp = -cDest.fp - mid; |
734 __asm__ __volatile__("" :: "m" (cDest.fp)); |
735 Fpscr = setVfpFpscr(Fpscr, state); 736 FpDestP0.uw = cDest.bits; 737 FpDestP1.uw = cDest.bits >> 32; 738 ''' 739 vnmlaDIop = InstObjParams("vnmlad", "VnmlaD", "VfpRegRegRegOp", 740 { "code": vnmlaDCode, 741 "predicate_test": predicateTest }, []) 742 header_output += VfpRegRegRegOpDeclare.subst(vnmlaDIop); 743 decoder_output += VfpRegRegRegOpConstructor.subst(vnmlaDIop); 744 exec_output += PredOpExecute.subst(vnmlaDIop); 745 746 vnmlsSCode = ''' 747 VfpSavedState state = prepVfpFpscr(Fpscr); |
748 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); |
749 float mid = FpOp1 * FpOp2; 750 if ((isinf(FpOp1) && FpOp2 == 0) || (isinf(FpOp2) && FpOp1 == 0)) { 751 mid = NAN; 752 } 753 FpDest = -FpDest + mid; |
754 __asm__ __volatile__("" :: "m" (FpDest)); |
755 Fpscr = setVfpFpscr(Fpscr, state); 756 ''' 757 vnmlsSIop = InstObjParams("vnmlss", "VnmlsS", "VfpRegRegRegOp", 758 { "code": vnmlsSCode, 759 "predicate_test": predicateTest }, []) 760 header_output += VfpRegRegRegOpDeclare.subst(vnmlsSIop); 761 decoder_output += VfpRegRegRegOpConstructor.subst(vnmlsSIop); 762 exec_output += PredOpExecute.subst(vnmlsSIop); 763 764 vnmlsDCode = ''' 765 IntDoubleUnion cOp1, cOp2, cDest; 766 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 767 cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32)); 768 cDest.bits = ((uint64_t)FpDestP0.uw | ((uint64_t)FpDestP1.uw << 32)); 769 VfpSavedState state = prepVfpFpscr(Fpscr); |
770 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp)); |
771 double mid = cOp1.fp * cOp2.fp; 772 if ((isinf(cOp1.fp) && cOp2.fp == 0) || 773 (isinf(cOp2.fp) && cOp1.fp == 0)) { 774 mid = NAN; 775 } 776 cDest.fp = -cDest.fp + mid; |
777 __asm__ __volatile__("" :: "m" (cDest.fp)); |
778 Fpscr = setVfpFpscr(Fpscr, state); 779 FpDestP0.uw = cDest.bits; 780 FpDestP1.uw = cDest.bits >> 32; 781 ''' 782 vnmlsDIop = InstObjParams("vnmlsd", "VnmlsD", "VfpRegRegRegOp", 783 { "code": vnmlsDCode, 784 "predicate_test": predicateTest }, []) 785 header_output += VfpRegRegRegOpDeclare.subst(vnmlsDIop); 786 decoder_output += VfpRegRegRegOpConstructor.subst(vnmlsDIop); 787 exec_output += PredOpExecute.subst(vnmlsDIop); 788 789 vnmulSCode = ''' 790 VfpSavedState state = prepVfpFpscr(Fpscr); |
791 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); |
792 float mid = FpOp1 * FpOp2; 793 if ((isinf(FpOp1) && FpOp2 == 0) || (isinf(FpOp2) && FpOp1 == 0)) { 794 mid = NAN; 795 } 796 FpDest = -mid; |
797 __asm__ __volatile__("" :: "m" (FpDest)); |
798 Fpscr = setVfpFpscr(Fpscr, state); 799 ''' 800 vnmulSIop = InstObjParams("vnmuls", "VnmulS", "VfpRegRegRegOp", 801 { "code": vnmulSCode, 802 "predicate_test": predicateTest }, []) 803 header_output += VfpRegRegRegOpDeclare.subst(vnmulSIop); 804 decoder_output += VfpRegRegRegOpConstructor.subst(vnmulSIop); 805 exec_output += PredOpExecute.subst(vnmulSIop); 806 807 vnmulDCode = ''' 808 IntDoubleUnion cOp1, cOp2, cDest; 809 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 810 cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32)); 811 cDest.bits = ((uint64_t)FpDestP0.uw | ((uint64_t)FpDestP1.uw << 32)); 812 VfpSavedState state = prepVfpFpscr(Fpscr); |
813 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp)); |
814 double mid = cOp1.fp * cOp2.fp; 815 if ((isinf(cOp1.fp) && cOp2.fp == 0) || 816 (isinf(cOp2.fp) && cOp1.fp == 0)) { 817 mid = NAN; 818 } 819 cDest.fp = -mid; |
820 __asm__ __volatile__("" :: "m" (cDest.fp)); |
821 Fpscr = setVfpFpscr(Fpscr, state); 822 FpDestP0.uw = cDest.bits; 823 FpDestP1.uw = cDest.bits >> 32; 824 ''' 825 vnmulDIop = InstObjParams("vnmuld", "VnmulD", "VfpRegRegRegOp", 826 { "code": vnmulDCode, 827 "predicate_test": predicateTest }, []) 828 header_output += VfpRegRegRegOpDeclare.subst(vnmulDIop); 829 decoder_output += VfpRegRegRegOpConstructor.subst(vnmulDIop); 830 exec_output += PredOpExecute.subst(vnmulDIop); |
831}}; |
832 |
833let {{ 834 835 header_output = "" 836 decoder_output = "" 837 exec_output = "" 838 |
839 vcvtUIntFpSCode = ''' 840 VfpSavedState state = prepVfpFpscr(Fpscr); |
841 __asm__ __volatile__("" : "=m" (FpOp1.uw) : "m" (FpOp1.uw)); |
842 FpDest = FpOp1.uw; |
843 __asm__ __volatile__("" :: "m" (FpDest)); |
844 Fpscr = setVfpFpscr(Fpscr, state); 845 ''' 846 vcvtUIntFpSIop = InstObjParams("vcvt", "VcvtUIntFpS", "VfpRegRegOp", 847 { "code": vcvtUIntFpSCode, 848 "predicate_test": predicateTest }, []) 849 header_output += VfpRegRegOpDeclare.subst(vcvtUIntFpSIop); 850 decoder_output += VfpRegRegOpConstructor.subst(vcvtUIntFpSIop); 851 exec_output += PredOpExecute.subst(vcvtUIntFpSIop); 852 853 vcvtUIntFpDCode = ''' 854 IntDoubleUnion cDest; 855 VfpSavedState state = prepVfpFpscr(Fpscr); |
856 __asm__ __volatile__("" : "=m" (FpOp1P0.uw) : "m" (FpOp1P0.uw)); |
857 cDest.fp = (uint64_t)FpOp1P0.uw; |
858 __asm__ __volatile__("" :: "m" (cDest.fp)); |
859 Fpscr = setVfpFpscr(Fpscr, state); 860 FpDestP0.uw = cDest.bits; 861 FpDestP1.uw = cDest.bits >> 32; 862 ''' 863 vcvtUIntFpDIop = InstObjParams("vcvt", "VcvtUIntFpD", "VfpRegRegOp", 864 { "code": vcvtUIntFpDCode, 865 "predicate_test": predicateTest }, []) 866 header_output += VfpRegRegOpDeclare.subst(vcvtUIntFpDIop); 867 decoder_output += VfpRegRegOpConstructor.subst(vcvtUIntFpDIop); 868 exec_output += PredOpExecute.subst(vcvtUIntFpDIop); 869 870 vcvtSIntFpSCode = ''' 871 VfpSavedState state = prepVfpFpscr(Fpscr); |
872 __asm__ __volatile__("" : "=m" (FpOp1.sw) : "m" (FpOp1.sw)); |
873 FpDest = FpOp1.sw; |
874 __asm__ __volatile__("" :: "m" (FpDest)); |
875 Fpscr = setVfpFpscr(Fpscr, state); 876 ''' 877 vcvtSIntFpSIop = InstObjParams("vcvt", "VcvtSIntFpS", "VfpRegRegOp", 878 { "code": vcvtSIntFpSCode, 879 "predicate_test": predicateTest }, []) 880 header_output += VfpRegRegOpDeclare.subst(vcvtSIntFpSIop); 881 decoder_output += VfpRegRegOpConstructor.subst(vcvtSIntFpSIop); 882 exec_output += PredOpExecute.subst(vcvtSIntFpSIop); 883 884 vcvtSIntFpDCode = ''' 885 IntDoubleUnion cDest; 886 VfpSavedState state = prepVfpFpscr(Fpscr); |
887 __asm__ __volatile__("" : "=m" (FpOp1P0.sw) : "m" (FpOp1P0.sw)); |
888 cDest.fp = FpOp1P0.sw; |
889 __asm__ __volatile__("" :: "m" (cDest.fp)); |
890 Fpscr = setVfpFpscr(Fpscr, state); 891 FpDestP0.uw = cDest.bits; 892 FpDestP1.uw = cDest.bits >> 32; 893 ''' 894 vcvtSIntFpDIop = InstObjParams("vcvt", "VcvtSIntFpD", "VfpRegRegOp", 895 { "code": vcvtSIntFpDCode, 896 "predicate_test": predicateTest }, []) 897 header_output += VfpRegRegOpDeclare.subst(vcvtSIntFpDIop); 898 decoder_output += VfpRegRegOpConstructor.subst(vcvtSIntFpDIop); 899 exec_output += PredOpExecute.subst(vcvtSIntFpDIop); 900 901 vcvtFpUIntSRCode = ''' 902 VfpSavedState state = prepVfpFpscr(Fpscr); |
903 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); |
904 FpDest.uw = FpOp1; |
905 __asm__ __volatile__("" :: "m" (FpDest.uw)); |
906 Fpscr = setVfpFpscr(Fpscr, state); 907 ''' 908 vcvtFpUIntSRIop = InstObjParams("vcvt", "VcvtFpUIntSR", "VfpRegRegOp", 909 { "code": vcvtFpUIntSRCode, 910 "predicate_test": predicateTest }, []) 911 header_output += VfpRegRegOpDeclare.subst(vcvtFpUIntSRIop); 912 decoder_output += VfpRegRegOpConstructor.subst(vcvtFpUIntSRIop); 913 exec_output += PredOpExecute.subst(vcvtFpUIntSRIop); 914 915 vcvtFpUIntDRCode = ''' 916 IntDoubleUnion cOp1; 917 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 918 VfpSavedState state = prepVfpFpscr(Fpscr); |
919 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp)); |
920 uint64_t result = cOp1.fp; |
921 __asm__ __volatile__("" :: "m" (result)); |
922 Fpscr = setVfpFpscr(Fpscr, state); 923 FpDestP0.uw = result; 924 ''' 925 vcvtFpUIntDRIop = InstObjParams("vcvtr", "VcvtFpUIntDR", "VfpRegRegOp", 926 { "code": vcvtFpUIntDRCode, 927 "predicate_test": predicateTest }, []) 928 header_output += VfpRegRegOpDeclare.subst(vcvtFpUIntDRIop); 929 decoder_output += VfpRegRegOpConstructor.subst(vcvtFpUIntDRIop); 930 exec_output += PredOpExecute.subst(vcvtFpUIntDRIop); 931 932 vcvtFpSIntSRCode = ''' 933 VfpSavedState state = prepVfpFpscr(Fpscr); |
934 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); |
935 FpDest.sw = FpOp1; |
936 __asm__ __volatile__("" :: "m" (FpDest.sw)); |
937 Fpscr = setVfpFpscr(Fpscr, state); 938 ''' 939 vcvtFpSIntSRIop = InstObjParams("vcvtr", "VcvtFpSIntSR", "VfpRegRegOp", 940 { "code": vcvtFpSIntSRCode, 941 "predicate_test": predicateTest }, []) 942 header_output += VfpRegRegOpDeclare.subst(vcvtFpSIntSRIop); 943 decoder_output += VfpRegRegOpConstructor.subst(vcvtFpSIntSRIop); 944 exec_output += PredOpExecute.subst(vcvtFpSIntSRIop); 945 946 vcvtFpSIntDRCode = ''' 947 IntDoubleUnion cOp1; 948 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 949 VfpSavedState state = prepVfpFpscr(Fpscr); |
950 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp)); |
951 int64_t result = cOp1.fp; |
952 __asm__ __volatile__("" :: "m" (result)); |
953 Fpscr = setVfpFpscr(Fpscr, state); 954 FpDestP0.uw = result; 955 ''' 956 vcvtFpSIntDRIop = InstObjParams("vcvtr", "VcvtFpSIntDR", "VfpRegRegOp", 957 { "code": vcvtFpSIntDRCode, 958 "predicate_test": predicateTest }, []) 959 header_output += VfpRegRegOpDeclare.subst(vcvtFpSIntDRIop); 960 decoder_output += VfpRegRegOpConstructor.subst(vcvtFpSIntDRIop); 961 exec_output += PredOpExecute.subst(vcvtFpSIntDRIop); 962 963 vcvtFpUIntSCode = ''' 964 VfpSavedState state = prepVfpFpscr(Fpscr); 965 fesetround(FeRoundZero); |
966 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); |
967 FpDest.uw = FpOp1; |
968 __asm__ __volatile__("" :: "m" (FpDest.uw)); |
969 Fpscr = setVfpFpscr(Fpscr, state); 970 ''' 971 vcvtFpUIntSIop = InstObjParams("vcvt", "VcvtFpUIntS", "VfpRegRegOp", 972 { "code": vcvtFpUIntSCode, 973 "predicate_test": predicateTest }, []) 974 header_output += VfpRegRegOpDeclare.subst(vcvtFpUIntSIop); 975 decoder_output += VfpRegRegOpConstructor.subst(vcvtFpUIntSIop); 976 exec_output += PredOpExecute.subst(vcvtFpUIntSIop); 977 978 vcvtFpUIntDCode = ''' 979 IntDoubleUnion cOp1; 980 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 981 VfpSavedState state = prepVfpFpscr(Fpscr); 982 fesetround(FeRoundZero); |
983 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp)); |
984 uint64_t result = cOp1.fp; |
985 __asm__ __volatile__("" :: "m" (result)); |
986 Fpscr = setVfpFpscr(Fpscr, state); 987 FpDestP0.uw = result; 988 ''' 989 vcvtFpUIntDIop = InstObjParams("vcvt", "VcvtFpUIntD", "VfpRegRegOp", 990 { "code": vcvtFpUIntDCode, 991 "predicate_test": predicateTest }, []) 992 header_output += VfpRegRegOpDeclare.subst(vcvtFpUIntDIop); 993 decoder_output += VfpRegRegOpConstructor.subst(vcvtFpUIntDIop); 994 exec_output += PredOpExecute.subst(vcvtFpUIntDIop); 995 996 vcvtFpSIntSCode = ''' 997 VfpSavedState state = prepVfpFpscr(Fpscr); 998 fesetround(FeRoundZero); |
999 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); |
1000 FpDest.sw = FpOp1; |
1001 __asm__ __volatile__("" :: "m" (FpDest.sw)); |
1002 Fpscr = setVfpFpscr(Fpscr, state); 1003 ''' 1004 vcvtFpSIntSIop = InstObjParams("vcvt", "VcvtFpSIntS", "VfpRegRegOp", 1005 { "code": vcvtFpSIntSCode, 1006 "predicate_test": predicateTest }, []) 1007 header_output += VfpRegRegOpDeclare.subst(vcvtFpSIntSIop); 1008 decoder_output += VfpRegRegOpConstructor.subst(vcvtFpSIntSIop); 1009 exec_output += PredOpExecute.subst(vcvtFpSIntSIop); 1010 1011 vcvtFpSIntDCode = ''' 1012 IntDoubleUnion cOp1; 1013 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 1014 VfpSavedState state = prepVfpFpscr(Fpscr); 1015 fesetround(FeRoundZero); |
1016 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp)); |
1017 int64_t result = cOp1.fp; |
1018 __asm__ __volatile__("" :: "m" (result)); |
1019 Fpscr = setVfpFpscr(Fpscr, state); 1020 FpDestP0.uw = result; 1021 ''' 1022 vcvtFpSIntDIop = InstObjParams("vcvt", "VcvtFpSIntD", "VfpRegRegOp", 1023 { "code": vcvtFpSIntDCode, 1024 "predicate_test": predicateTest }, []) 1025 header_output += VfpRegRegOpDeclare.subst(vcvtFpSIntDIop); 1026 decoder_output += VfpRegRegOpConstructor.subst(vcvtFpSIntDIop); 1027 exec_output += PredOpExecute.subst(vcvtFpSIntDIop); 1028 1029 vcvtFpSFpDCode = ''' 1030 IntDoubleUnion cDest; 1031 VfpSavedState state = prepVfpFpscr(Fpscr); |
1032 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); |
1033 cDest.fp = FpOp1; |
1034 __asm__ __volatile__("" :: "m" (cDest.fp)); |
1035 Fpscr = setVfpFpscr(Fpscr, state); 1036 FpDestP0.uw = cDest.bits; 1037 FpDestP1.uw = cDest.bits >> 32; 1038 ''' 1039 vcvtFpSFpDIop = InstObjParams("vcvt", "VcvtFpSFpD", "VfpRegRegOp", 1040 { "code": vcvtFpSFpDCode, 1041 "predicate_test": predicateTest }, []) 1042 header_output += VfpRegRegOpDeclare.subst(vcvtFpSFpDIop); 1043 decoder_output += VfpRegRegOpConstructor.subst(vcvtFpSFpDIop); 1044 exec_output += PredOpExecute.subst(vcvtFpSFpDIop); 1045 1046 vcvtFpDFpSCode = ''' 1047 IntDoubleUnion cOp1; 1048 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 1049 VfpSavedState state = prepVfpFpscr(Fpscr); |
1050 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp)); |
1051 FpDest = cOp1.fp; |
1052 __asm__ __volatile__("" :: "m" (FpDest)); |
1053 Fpscr = setVfpFpscr(Fpscr, state); 1054 ''' 1055 vcvtFpDFpSIop = InstObjParams("vcvt", "VcvtFpDFpS", "VfpRegRegOp", 1056 { "code": vcvtFpDFpSCode, 1057 "predicate_test": predicateTest }, []) 1058 header_output += VfpRegRegOpDeclare.subst(vcvtFpDFpSIop); 1059 decoder_output += VfpRegRegOpConstructor.subst(vcvtFpDFpSIop); 1060 exec_output += PredOpExecute.subst(vcvtFpDFpSIop); --- 87 unchanged lines hidden (view full) --- 1148let {{ 1149 1150 header_output = "" 1151 decoder_output = "" 1152 exec_output = "" 1153 1154 vcvtFpSFixedSCode = ''' 1155 VfpSavedState state = prepVfpFpscr(Fpscr); |
1156 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); |
1157 FpDest.sw = vfpFpSToFixed(FpOp1, true, false, imm); |
1158 __asm__ __volatile__("" :: "m" (FpDest.sw)); |
1159 Fpscr = setVfpFpscr(Fpscr, state); 1160 ''' 1161 vcvtFpSFixedSIop = InstObjParams("vcvt", "VcvtFpSFixedS", "VfpRegRegImmOp", 1162 { "code": vcvtFpSFixedSCode, 1163 "predicate_test": predicateTest }, []) 1164 header_output += VfpRegRegImmOpDeclare.subst(vcvtFpSFixedSIop); 1165 decoder_output += VfpRegRegImmOpConstructor.subst(vcvtFpSFixedSIop); 1166 exec_output += PredOpExecute.subst(vcvtFpSFixedSIop); 1167 1168 vcvtFpSFixedDCode = ''' 1169 IntDoubleUnion cOp1; 1170 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 1171 VfpSavedState state = prepVfpFpscr(Fpscr); |
1172 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp)); |
1173 uint64_t mid = vfpFpDToFixed(cOp1.fp, true, false, imm); |
1174 __asm__ __volatile__("" :: "m" (mid)); |
1175 Fpscr = setVfpFpscr(Fpscr, state); 1176 FpDestP0.uw = mid; 1177 FpDestP1.uw = mid >> 32; 1178 ''' 1179 vcvtFpSFixedDIop = InstObjParams("vcvt", "VcvtFpSFixedD", "VfpRegRegImmOp", 1180 { "code": vcvtFpSFixedDCode, 1181 "predicate_test": predicateTest }, []) 1182 header_output += VfpRegRegImmOpDeclare.subst(vcvtFpSFixedDIop); 1183 decoder_output += VfpRegRegImmOpConstructor.subst(vcvtFpSFixedDIop); 1184 exec_output += PredOpExecute.subst(vcvtFpSFixedDIop); 1185 1186 vcvtFpUFixedSCode = ''' 1187 VfpSavedState state = prepVfpFpscr(Fpscr); |
1188 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); |
1189 FpDest.uw = vfpFpSToFixed(FpOp1, false, false, imm); |
1190 __asm__ __volatile__("" :: "m" (FpDest.uw)); |
1191 Fpscr = setVfpFpscr(Fpscr, state); 1192 ''' 1193 vcvtFpUFixedSIop = InstObjParams("vcvt", "VcvtFpUFixedS", "VfpRegRegImmOp", 1194 { "code": vcvtFpUFixedSCode, 1195 "predicate_test": predicateTest }, []) 1196 header_output += VfpRegRegImmOpDeclare.subst(vcvtFpUFixedSIop); 1197 decoder_output += VfpRegRegImmOpConstructor.subst(vcvtFpUFixedSIop); 1198 exec_output += PredOpExecute.subst(vcvtFpUFixedSIop); 1199 1200 vcvtFpUFixedDCode = ''' 1201 IntDoubleUnion cOp1; 1202 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 1203 VfpSavedState state = prepVfpFpscr(Fpscr); |
1204 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp)); |
1205 uint64_t mid = vfpFpDToFixed(cOp1.fp, false, false, imm); |
1206 __asm__ __volatile__("" :: "m" (mid)); |
1207 Fpscr = setVfpFpscr(Fpscr, state); 1208 FpDestP0.uw = mid; 1209 FpDestP1.uw = mid >> 32; 1210 ''' 1211 vcvtFpUFixedDIop = InstObjParams("vcvt", "VcvtFpUFixedD", "VfpRegRegImmOp", 1212 { "code": vcvtFpUFixedDCode, 1213 "predicate_test": predicateTest }, []) 1214 header_output += VfpRegRegImmOpDeclare.subst(vcvtFpUFixedDIop); 1215 decoder_output += VfpRegRegImmOpConstructor.subst(vcvtFpUFixedDIop); 1216 exec_output += PredOpExecute.subst(vcvtFpUFixedDIop); 1217 1218 vcvtSFixedFpSCode = ''' 1219 VfpSavedState state = prepVfpFpscr(Fpscr); |
1220 __asm__ __volatile__("" : "=m" (FpOp1.sw) : "m" (FpOp1.sw)); |
1221 FpDest = vfpSFixedToFpS(FpOp1.sw, false, imm); |
1222 __asm__ __volatile__("" :: "m" (FpDest)); |
1223 Fpscr = setVfpFpscr(Fpscr, state); 1224 ''' 1225 vcvtSFixedFpSIop = InstObjParams("vcvt", "VcvtSFixedFpS", "VfpRegRegImmOp", 1226 { "code": vcvtSFixedFpSCode, 1227 "predicate_test": predicateTest }, []) 1228 header_output += VfpRegRegImmOpDeclare.subst(vcvtSFixedFpSIop); 1229 decoder_output += VfpRegRegImmOpConstructor.subst(vcvtSFixedFpSIop); 1230 exec_output += PredOpExecute.subst(vcvtSFixedFpSIop); 1231 1232 vcvtSFixedFpDCode = ''' 1233 IntDoubleUnion cDest; 1234 uint64_t mid = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 1235 VfpSavedState state = prepVfpFpscr(Fpscr); |
1236 __asm__ __volatile__("" : "=m" (mid) : "m" (mid)); |
1237 cDest.fp = vfpSFixedToFpD(mid, false, imm); |
1238 __asm__ __volatile__("" :: "m" (cDest.fp)); |
1239 Fpscr = setVfpFpscr(Fpscr, state); 1240 FpDestP0.uw = cDest.bits; 1241 FpDestP1.uw = cDest.bits >> 32; 1242 ''' 1243 vcvtSFixedFpDIop = InstObjParams("vcvt", "VcvtSFixedFpD", "VfpRegRegImmOp", 1244 { "code": vcvtSFixedFpDCode, 1245 "predicate_test": predicateTest }, []) 1246 header_output += VfpRegRegImmOpDeclare.subst(vcvtSFixedFpDIop); 1247 decoder_output += VfpRegRegImmOpConstructor.subst(vcvtSFixedFpDIop); 1248 exec_output += PredOpExecute.subst(vcvtSFixedFpDIop); 1249 1250 vcvtUFixedFpSCode = ''' 1251 VfpSavedState state = prepVfpFpscr(Fpscr); |
1252 __asm__ __volatile__("" : "=m" (FpOp1.uw) : "m" (FpOp1.uw)); |
1253 FpDest = vfpUFixedToFpS(FpOp1.uw, false, imm); |
1254 __asm__ __volatile__("" :: "m" (FpDest)); |
1255 Fpscr = setVfpFpscr(Fpscr, state); 1256 ''' 1257 vcvtUFixedFpSIop = InstObjParams("vcvt", "VcvtUFixedFpS", "VfpRegRegImmOp", 1258 { "code": vcvtUFixedFpSCode, 1259 "predicate_test": predicateTest }, []) 1260 header_output += VfpRegRegImmOpDeclare.subst(vcvtUFixedFpSIop); 1261 decoder_output += VfpRegRegImmOpConstructor.subst(vcvtUFixedFpSIop); 1262 exec_output += PredOpExecute.subst(vcvtUFixedFpSIop); 1263 1264 vcvtUFixedFpDCode = ''' 1265 IntDoubleUnion cDest; 1266 uint64_t mid = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 1267 VfpSavedState state = prepVfpFpscr(Fpscr); |
1268 __asm__ __volatile__("" : "=m" (mid) : "m" (mid)); |
1269 cDest.fp = vfpUFixedToFpD(mid, false, imm); |
1270 __asm__ __volatile__("" :: "m" (cDest.fp)); |
1271 Fpscr = setVfpFpscr(Fpscr, state); 1272 FpDestP0.uw = cDest.bits; 1273 FpDestP1.uw = cDest.bits >> 32; 1274 ''' 1275 vcvtUFixedFpDIop = InstObjParams("vcvt", "VcvtUFixedFpD", "VfpRegRegImmOp", 1276 { "code": vcvtUFixedFpDCode, 1277 "predicate_test": predicateTest }, []) 1278 header_output += VfpRegRegImmOpDeclare.subst(vcvtUFixedFpDIop); 1279 decoder_output += VfpRegRegImmOpConstructor.subst(vcvtUFixedFpDIop); 1280 exec_output += PredOpExecute.subst(vcvtUFixedFpDIop); 1281 1282 vcvtFpSHFixedSCode = ''' 1283 VfpSavedState state = prepVfpFpscr(Fpscr); |
1284 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); |
1285 FpDest.sh = vfpFpSToFixed(FpOp1, true, true, imm); |
1286 __asm__ __volatile__("" :: "m" (FpDest.sh)); |
1287 Fpscr = setVfpFpscr(Fpscr, state); 1288 ''' 1289 vcvtFpSHFixedSIop = InstObjParams("vcvt", "VcvtFpSHFixedS", 1290 "VfpRegRegImmOp", 1291 { "code": vcvtFpSHFixedSCode, 1292 "predicate_test": predicateTest }, []) 1293 header_output += VfpRegRegImmOpDeclare.subst(vcvtFpSHFixedSIop); 1294 decoder_output += VfpRegRegImmOpConstructor.subst(vcvtFpSHFixedSIop); 1295 exec_output += PredOpExecute.subst(vcvtFpSHFixedSIop); 1296 1297 vcvtFpSHFixedDCode = ''' 1298 IntDoubleUnion cOp1; 1299 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 1300 VfpSavedState state = prepVfpFpscr(Fpscr); |
1301 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp)); |
1302 uint64_t result = vfpFpDToFixed(cOp1.fp, true, true, imm); |
1303 __asm__ __volatile__("" :: "m" (result)); |
1304 Fpscr = setVfpFpscr(Fpscr, state); 1305 FpDestP0.uw = result; 1306 FpDestP1.uw = result >> 32; 1307 ''' 1308 vcvtFpSHFixedDIop = InstObjParams("vcvt", "VcvtFpSHFixedD", 1309 "VfpRegRegImmOp", 1310 { "code": vcvtFpSHFixedDCode, 1311 "predicate_test": predicateTest }, []) 1312 header_output += VfpRegRegImmOpDeclare.subst(vcvtFpSHFixedDIop); 1313 decoder_output += VfpRegRegImmOpConstructor.subst(vcvtFpSHFixedDIop); 1314 exec_output += PredOpExecute.subst(vcvtFpSHFixedDIop); 1315 1316 vcvtFpUHFixedSCode = ''' 1317 VfpSavedState state = prepVfpFpscr(Fpscr); |
1318 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); |
1319 FpDest.uh = vfpFpSToFixed(FpOp1, false, true, imm); |
1320 __asm__ __volatile__("" :: "m" (FpDest.uh)); |
1321 Fpscr = setVfpFpscr(Fpscr, state); 1322 ''' 1323 vcvtFpUHFixedSIop = InstObjParams("vcvt", "VcvtFpUHFixedS", 1324 "VfpRegRegImmOp", 1325 { "code": vcvtFpUHFixedSCode, 1326 "predicate_test": predicateTest }, []) 1327 header_output += VfpRegRegImmOpDeclare.subst(vcvtFpUHFixedSIop); 1328 decoder_output += VfpRegRegImmOpConstructor.subst(vcvtFpUHFixedSIop); 1329 exec_output += PredOpExecute.subst(vcvtFpUHFixedSIop); 1330 1331 vcvtFpUHFixedDCode = ''' 1332 IntDoubleUnion cOp1; 1333 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 1334 VfpSavedState state = prepVfpFpscr(Fpscr); |
1335 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp)); |
1336 uint64_t mid = vfpFpDToFixed(cOp1.fp, false, true, imm); |
1337 __asm__ __volatile__("" :: "m" (mid)); |
1338 Fpscr = setVfpFpscr(Fpscr, state); 1339 FpDestP0.uw = mid; 1340 FpDestP1.uw = mid >> 32; 1341 ''' 1342 vcvtFpUHFixedDIop = InstObjParams("vcvt", "VcvtFpUHFixedD", 1343 "VfpRegRegImmOp", 1344 { "code": vcvtFpUHFixedDCode, 1345 "predicate_test": predicateTest }, []) 1346 header_output += VfpRegRegImmOpDeclare.subst(vcvtFpUHFixedDIop); 1347 decoder_output += VfpRegRegImmOpConstructor.subst(vcvtFpUHFixedDIop); 1348 exec_output += PredOpExecute.subst(vcvtFpUHFixedDIop); 1349 1350 vcvtSHFixedFpSCode = ''' 1351 VfpSavedState state = prepVfpFpscr(Fpscr); |
1352 __asm__ __volatile__("" : "=m" (FpOp1.sh) : "m" (FpOp1.sh)); |
1353 FpDest = vfpSFixedToFpS(FpOp1.sh, true, imm); |
1354 __asm__ __volatile__("" :: "m" (FpDest)); |
1355 Fpscr = setVfpFpscr(Fpscr, state); 1356 ''' 1357 vcvtSHFixedFpSIop = InstObjParams("vcvt", "VcvtSHFixedFpS", 1358 "VfpRegRegImmOp", 1359 { "code": vcvtSHFixedFpSCode, 1360 "predicate_test": predicateTest }, []) 1361 header_output += VfpRegRegImmOpDeclare.subst(vcvtSHFixedFpSIop); 1362 decoder_output += VfpRegRegImmOpConstructor.subst(vcvtSHFixedFpSIop); 1363 exec_output += PredOpExecute.subst(vcvtSHFixedFpSIop); 1364 1365 vcvtSHFixedFpDCode = ''' 1366 IntDoubleUnion cDest; 1367 uint64_t mid = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 1368 VfpSavedState state = prepVfpFpscr(Fpscr); |
1369 __asm__ __volatile__("" : "=m" (mid) : "m" (mid)); |
1370 cDest.fp = vfpSFixedToFpD(mid, true, imm); |
1371 __asm__ __volatile__("" :: "m" (cDest.fp)); |
1372 Fpscr = setVfpFpscr(Fpscr, state); 1373 FpDestP0.uw = cDest.bits; 1374 FpDestP1.uw = cDest.bits >> 32; 1375 ''' 1376 vcvtSHFixedFpDIop = InstObjParams("vcvt", "VcvtSHFixedFpD", 1377 "VfpRegRegImmOp", 1378 { "code": vcvtSHFixedFpDCode, 1379 "predicate_test": predicateTest }, []) 1380 header_output += VfpRegRegImmOpDeclare.subst(vcvtSHFixedFpDIop); 1381 decoder_output += VfpRegRegImmOpConstructor.subst(vcvtSHFixedFpDIop); 1382 exec_output += PredOpExecute.subst(vcvtSHFixedFpDIop); 1383 1384 vcvtUHFixedFpSCode = ''' 1385 VfpSavedState state = prepVfpFpscr(Fpscr); |
1386 __asm__ __volatile__("" : "=m" (FpOp1.uh) : "m" (FpOp1.uh)); |
1387 FpDest = vfpUFixedToFpS(FpOp1.uh, true, imm); |
1388 __asm__ __volatile__("" :: "m" (FpDest)); |
1389 Fpscr = setVfpFpscr(Fpscr, state); 1390 ''' 1391 vcvtUHFixedFpSIop = InstObjParams("vcvt", "VcvtUHFixedFpS", 1392 "VfpRegRegImmOp", 1393 { "code": vcvtUHFixedFpSCode, 1394 "predicate_test": predicateTest }, []) 1395 header_output += VfpRegRegImmOpDeclare.subst(vcvtUHFixedFpSIop); 1396 decoder_output += VfpRegRegImmOpConstructor.subst(vcvtUHFixedFpSIop); 1397 exec_output += PredOpExecute.subst(vcvtUHFixedFpSIop); 1398 1399 vcvtUHFixedFpDCode = ''' 1400 IntDoubleUnion cDest; 1401 uint64_t mid = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 1402 VfpSavedState state = prepVfpFpscr(Fpscr); |
1403 __asm__ __volatile__("" : "=m" (mid) : "m" (mid)); |
1404 cDest.fp = vfpUFixedToFpD(mid, true, imm); |
1405 __asm__ __volatile__("" :: "m" (cDest.fp)); |
1406 Fpscr = setVfpFpscr(Fpscr, state); 1407 FpDestP0.uw = cDest.bits; 1408 FpDestP1.uw = cDest.bits >> 32; 1409 ''' 1410 vcvtUHFixedFpDIop = InstObjParams("vcvt", "VcvtUHFixedFpD", 1411 "VfpRegRegImmOp", 1412 { "code": vcvtUHFixedFpDCode, 1413 "predicate_test": predicateTest }, []) 1414 header_output += VfpRegRegImmOpDeclare.subst(vcvtUHFixedFpDIop); 1415 decoder_output += VfpRegRegImmOpConstructor.subst(vcvtUHFixedFpDIop); 1416 exec_output += PredOpExecute.subst(vcvtUHFixedFpDIop); 1417}}; |