238,249d237
< vmrsApsrCode = vmrsEnabledCheckCode + '''
< Dest = (MiscOp1 & imm) | (Dest & ~imm);
< '''
< vmrsApsrIop = InstObjParams("vmrs", "VmrsApsr", "FpRegRegImmOp",
< { "code": vmrsApsrCode,
< "predicate_test": predicateTest,
< "op_class": "SimdFloatMiscOp" },
< ["IsSerializeBefore"])
< header_output += FpRegRegImmOpDeclare.subst(vmrsApsrIop);
< decoder_output += FpRegRegImmOpConstructor.subst(vmrsApsrIop);
< exec_output += PredOpExecute.subst(vmrsApsrIop);
<
251,252c239
< assert((imm & ~FpCondCodesMask) == 0);
< Dest = (FpCondCodes & imm) | (Dest & ~imm);
---
> Dest = FpCondCodes & FpCondCodesMask;