831a832,885
> vcvtFpUIntSRCode = '''
> VfpSavedState state = prepVfpFpscr(Fpscr);
> FpDest.uw = FpOp1;
> Fpscr = setVfpFpscr(Fpscr, state);
> '''
> vcvtFpUIntSRIop = InstObjParams("vcvt", "VcvtFpUIntSR", "VfpRegRegOp",
> { "code": vcvtFpUIntSRCode,
> "predicate_test": predicateTest }, [])
> header_output += VfpRegRegOpDeclare.subst(vcvtFpUIntSRIop);
> decoder_output += VfpRegRegOpConstructor.subst(vcvtFpUIntSRIop);
> exec_output += PredOpExecute.subst(vcvtFpUIntSRIop);
>
> vcvtFpUIntDRCode = '''
> IntDoubleUnion cOp1;
> cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
> VfpSavedState state = prepVfpFpscr(Fpscr);
> uint64_t result = cOp1.fp;
> Fpscr = setVfpFpscr(Fpscr, state);
> FpDestP0.uw = result;
> '''
> vcvtFpUIntDRIop = InstObjParams("vcvtr", "VcvtFpUIntDR", "VfpRegRegOp",
> { "code": vcvtFpUIntDRCode,
> "predicate_test": predicateTest }, [])
> header_output += VfpRegRegOpDeclare.subst(vcvtFpUIntDRIop);
> decoder_output += VfpRegRegOpConstructor.subst(vcvtFpUIntDRIop);
> exec_output += PredOpExecute.subst(vcvtFpUIntDRIop);
>
> vcvtFpSIntSRCode = '''
> VfpSavedState state = prepVfpFpscr(Fpscr);
> FpDest.sw = FpOp1;
> Fpscr = setVfpFpscr(Fpscr, state);
> '''
> vcvtFpSIntSRIop = InstObjParams("vcvtr", "VcvtFpSIntSR", "VfpRegRegOp",
> { "code": vcvtFpSIntSRCode,
> "predicate_test": predicateTest }, [])
> header_output += VfpRegRegOpDeclare.subst(vcvtFpSIntSRIop);
> decoder_output += VfpRegRegOpConstructor.subst(vcvtFpSIntSRIop);
> exec_output += PredOpExecute.subst(vcvtFpSIntSRIop);
>
> vcvtFpSIntDRCode = '''
> IntDoubleUnion cOp1;
> cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
> VfpSavedState state = prepVfpFpscr(Fpscr);
> int64_t result = cOp1.fp;
> Fpscr = setVfpFpscr(Fpscr, state);
> FpDestP0.uw = result;
> '''
> vcvtFpSIntDRIop = InstObjParams("vcvtr", "VcvtFpSIntDR", "VfpRegRegOp",
> { "code": vcvtFpSIntDRCode,
> "predicate_test": predicateTest }, [])
> header_output += VfpRegRegOpDeclare.subst(vcvtFpSIntDRIop);
> decoder_output += VfpRegRegOpConstructor.subst(vcvtFpSIntDRIop);
> exec_output += PredOpExecute.subst(vcvtFpSIntDRIop);
>
833a888
> fesetround(FeRoundZero);
847a903
> fesetround(FeRoundZero);
860a917
> fesetround(FeRoundZero);
874a932
> fesetround(FeRoundZero);
1065c1123
< FpDest = vfpSFixedToFpS(FpOp1.sw, true, imm);
---
> FpDest = vfpSFixedToFpS(FpOp1.sw, false, imm);
1079c1137
< cDest.fp = vfpSFixedToFpD(mid, true, imm);
---
> cDest.fp = vfpSFixedToFpD(mid, false, imm);