3c3
< // Copyright (c) 2010-2013,2016 ARM Limited
---
> // Copyright (c) 2010-2013,2016,2018-2019 ARM Limited
996c996,1023
< vcvtFpUIntSCode = vfpEnabledCheckCode + '''
---
> round_mode_suffix_to_mode = {
> '': 'VfpRoundZero',
> 'a': 'VfpRoundAway',
> 'm': 'VfpRoundDown',
> 'n': 'VfpRoundNearest',
> 'p': 'VfpRoundUpward',
> }
>
> def buildVcvt(code, className, roundModeSuffix):
> global header_output, decoder_output, exec_output, \
> vfpEnabledCheckCode, round_mode_suffix_to_mode
> full_code = vfpEnabledCheckCode + code.format(
> round_mode=round_mode_suffix_to_mode[roundModeSuffix],
> )
> iop = InstObjParams(
> "vcvt{}".format(roundModeSuffix),
> className.format(roundModeSuffix),
> "FpRegRegOp",
> { "code": full_code,
> "predicate_test": predicateTest,
> "op_class": "SimdFloatCvtOp" },
> []
> )
> header_output += FpRegRegOpDeclare.subst(iop);
> decoder_output += FpRegRegOpConstructor.subst(iop);
> exec_output += PredOpExecute.subst(iop);
>
> code = '''
1002c1029,1030
< FpDest_uw = vfpFpToFixed<float>(FpOp1, false, 32, 0);
---
> FpDest_uw = vfpFpToFixed<float>(
> FpOp1, false, 32, 0, true, {round_mode});
1007,1013c1035,1036
< vcvtFpUIntSIop = InstObjParams("vcvt", "VcvtFpUIntS", "FpRegRegOp",
< { "code": vcvtFpUIntSCode,
< "predicate_test": predicateTest,
< "op_class": "SimdFloatCvtOp" }, [])
< header_output += FpRegRegOpDeclare.subst(vcvtFpUIntSIop);
< decoder_output += FpRegRegOpConstructor.subst(vcvtFpUIntSIop);
< exec_output += PredOpExecute.subst(vcvtFpUIntSIop);
---
> for round_mode_suffix in round_mode_suffix_to_mode:
> buildVcvt(code, "Vcvt{}FpUIntS", round_mode_suffix)
1015c1038
< vcvtFpUIntDCode = vfpEnabledCheckCode + '''
---
> code = '''
1022c1045,1046
< uint64_t result = vfpFpToFixed<double>(cOp1, false, 32, 0);
---
> uint64_t result = vfpFpToFixed<double>(
> cOp1, false, 32, 0, true, {round_mode});
1028,1034c1052,1053
< vcvtFpUIntDIop = InstObjParams("vcvt", "VcvtFpUIntD", "FpRegRegOp",
< { "code": vcvtFpUIntDCode,
< "predicate_test": predicateTest,
< "op_class": "SimdFloatCvtOp" }, [])
< header_output += FpRegRegOpDeclare.subst(vcvtFpUIntDIop);
< decoder_output += FpRegRegOpConstructor.subst(vcvtFpUIntDIop);
< exec_output += PredOpExecute.subst(vcvtFpUIntDIop);
---
> for round_mode_suffix in round_mode_suffix_to_mode:
> buildVcvt(code, "Vcvt{}FpUIntD", round_mode_suffix)
1036c1055
< vcvtFpSIntSCode = vfpEnabledCheckCode + '''
---
> code = '''
1042c1061,1062
< FpDest_sw = vfpFpToFixed<float>(FpOp1, true, 32, 0);
---
> FpDest_sw = vfpFpToFixed<float>(
> FpOp1, true, 32, 0, true, {round_mode});
1047,1053c1067,1068
< vcvtFpSIntSIop = InstObjParams("vcvt", "VcvtFpSIntS", "FpRegRegOp",
< { "code": vcvtFpSIntSCode,
< "predicate_test": predicateTest,
< "op_class": "SimdFloatCvtOp" }, [])
< header_output += FpRegRegOpDeclare.subst(vcvtFpSIntSIop);
< decoder_output += FpRegRegOpConstructor.subst(vcvtFpSIntSIop);
< exec_output += PredOpExecute.subst(vcvtFpSIntSIop);
---
> for round_mode_suffix in round_mode_suffix_to_mode:
> buildVcvt(code, "Vcvt{}FpSIntS", round_mode_suffix)
1055c1070
< vcvtFpSIntDCode = vfpEnabledCheckCode + '''
---
> code = '''
1062c1077,1078
< int64_t result = vfpFpToFixed<double>(cOp1, true, 32, 0);
---
> int64_t result = vfpFpToFixed<double>(
> cOp1, true, 32, 0, true, {round_mode});
1068,1074c1084,1085
< vcvtFpSIntDIop = InstObjParams("vcvt", "VcvtFpSIntD", "FpRegRegOp",
< { "code": vcvtFpSIntDCode,
< "predicate_test": predicateTest,
< "op_class": "SimdFloatCvtOp" }, [])
< header_output += FpRegRegOpDeclare.subst(vcvtFpSIntDIop);
< decoder_output += FpRegRegOpConstructor.subst(vcvtFpSIntDIop);
< exec_output += PredOpExecute.subst(vcvtFpSIntDIop);
---
> for round_mode_suffix in round_mode_suffix_to_mode:
> buildVcvt(code, "Vcvt{}FpSIntD", round_mode_suffix)