1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder. You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated
12// unmodified and in its entirety in all distributions of the software,
13// modified or unmodified, in source code or in binary form.
14//
15// Redistribution and use in source and binary forms, with or without
16// modification, are permitted provided that the following conditions are
17// met: redistributions of source code must retain the above copyright
18// notice, this list of conditions and the following disclaimer;
19// redistributions in binary form must reproduce the above copyright
20// notice, this list of conditions and the following disclaimer in the
21// documentation and/or other materials provided with the distribution;
22// neither the name of the copyright holders nor the names of its
23// contributors may be used to endorse or promote products derived from
24// this software without specific prior written permission.
25//
26// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
27// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
28// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
29// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
30// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
31// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
32// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
33// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
34// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
35// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
36// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37//
38// Authors: Gabe Black
39
40let {{
41
42 header_output = ""
43 decoder_output = ""
44 exec_output = ""
45
46 vmsrIop = InstObjParams("vmsr", "Vmsr", "RegRegOp",
47 { "code": "MiscDest = Op1;",
48 "predicate_test": predicateTest }, [])
49 header_output += RegRegOpDeclare.subst(vmsrIop);
50 decoder_output += RegRegOpConstructor.subst(vmsrIop);
51 exec_output += PredOpExecute.subst(vmsrIop);
52
53 vmrsIop = InstObjParams("vmrs", "Vmrs", "RegRegOp",
54 { "code": "Dest = MiscOp1;",
55 "predicate_test": predicateTest }, [])
56 header_output += RegRegOpDeclare.subst(vmrsIop);
57 decoder_output += RegRegOpConstructor.subst(vmrsIop);
58 exec_output += PredOpExecute.subst(vmrsIop);
59
60 vmovImmSCode = '''
61 FpDest.uw = bits(imm, 31, 0);
62 '''
63 vmovImmSIop = InstObjParams("vmov", "VmovImmS", "RegImmOp",
64 { "code": vmovImmSCode,
65 "predicate_test": predicateTest }, [])
66 header_output += RegImmOpDeclare.subst(vmovImmSIop);
67 decoder_output += RegImmOpConstructor.subst(vmovImmSIop);
68 exec_output += PredOpExecute.subst(vmovImmSIop);
69
70 vmovImmDCode = '''
71 FpDestP0.uw = bits(imm, 31, 0);
72 FpDestP1.uw = bits(imm, 63, 32);
73 '''
74 vmovImmDIop = InstObjParams("vmov", "VmovImmD", "RegImmOp",
75 { "code": vmovImmDCode,
76 "predicate_test": predicateTest }, [])
77 header_output += RegImmOpDeclare.subst(vmovImmDIop);
78 decoder_output += RegImmOpConstructor.subst(vmovImmDIop);
79 exec_output += PredOpExecute.subst(vmovImmDIop);
80
81 vmovImmQCode = '''
82 FpDestP0.uw = bits(imm, 31, 0);
83 FpDestP1.uw = bits(imm, 63, 32);
84 FpDestP2.uw = bits(imm, 31, 0);
85 FpDestP3.uw = bits(imm, 63, 32);
86 '''
87 vmovImmQIop = InstObjParams("vmov", "VmovImmQ", "RegImmOp",
88 { "code": vmovImmQCode,
89 "predicate_test": predicateTest }, [])
90 header_output += RegImmOpDeclare.subst(vmovImmQIop);
91 decoder_output += RegImmOpConstructor.subst(vmovImmQIop);
92 exec_output += PredOpExecute.subst(vmovImmQIop);
93
94 vmovRegSCode = '''
95 FpDest.uw = FpOp1.uw;
96 '''
97 vmovRegSIop = InstObjParams("vmov", "VmovRegS", "RegRegOp",
98 { "code": vmovRegSCode,
99 "predicate_test": predicateTest }, [])
100 header_output += RegRegOpDeclare.subst(vmovRegSIop);
101 decoder_output += RegRegOpConstructor.subst(vmovRegSIop);
102 exec_output += PredOpExecute.subst(vmovRegSIop);
103
104 vmovRegDCode = '''
105 FpDestP0.uw = FpOp1P0.uw;
106 FpDestP1.uw = FpOp1P1.uw;
107 '''
108 vmovRegDIop = InstObjParams("vmov", "VmovRegD", "RegRegOp",
109 { "code": vmovRegDCode,
110 "predicate_test": predicateTest }, [])
111 header_output += RegRegOpDeclare.subst(vmovRegDIop);
112 decoder_output += RegRegOpConstructor.subst(vmovRegDIop);
113 exec_output += PredOpExecute.subst(vmovRegDIop);
114
115 vmovRegQCode = '''
116 FpDestP0.uw = FpOp1P0.uw;
117 FpDestP1.uw = FpOp1P1.uw;
118 FpDestP2.uw = FpOp1P2.uw;
119 FpDestP3.uw = FpOp1P3.uw;
120 '''
121 vmovRegQIop = InstObjParams("vmov", "VmovRegQ", "RegRegOp",
122 { "code": vmovRegQCode,
123 "predicate_test": predicateTest }, [])
124 header_output += RegRegOpDeclare.subst(vmovRegQIop);
125 decoder_output += RegRegOpConstructor.subst(vmovRegQIop);
126 exec_output += PredOpExecute.subst(vmovRegQIop);
127
128 vmovCoreRegBCode = '''
129 FpDest.uw = insertBits(FpDest.uw, imm * 8, imm * 8 + 7, Op1.ub);
130 '''
131 vmovCoreRegBIop = InstObjParams("vmov", "VmovCoreRegB", "RegRegImmOp",
132 { "code": vmovCoreRegBCode,
133 "predicate_test": predicateTest }, [])
134 header_output += RegRegImmOpDeclare.subst(vmovCoreRegBIop);
135 decoder_output += RegRegImmOpConstructor.subst(vmovCoreRegBIop);
136 exec_output += PredOpExecute.subst(vmovCoreRegBIop);
137
138 vmovCoreRegHCode = '''
139 FpDest.uw = insertBits(FpDest.uw, imm * 16, imm * 16 + 15, Op1.uh);
140 '''
141 vmovCoreRegHIop = InstObjParams("vmov", "VmovCoreRegH", "RegRegImmOp",
142 { "code": vmovCoreRegHCode,
143 "predicate_test": predicateTest }, [])
144 header_output += RegRegImmOpDeclare.subst(vmovCoreRegHIop);
145 decoder_output += RegRegImmOpConstructor.subst(vmovCoreRegHIop);
146 exec_output += PredOpExecute.subst(vmovCoreRegHIop);
147
148 vmovCoreRegWCode = '''
149 FpDest.uw = Op1.uw;
150 '''
151 vmovCoreRegWIop = InstObjParams("vmov", "VmovCoreRegW", "RegRegOp",
152 { "code": vmovCoreRegWCode,
153 "predicate_test": predicateTest }, [])
154 header_output += RegRegOpDeclare.subst(vmovCoreRegWIop);
155 decoder_output += RegRegOpConstructor.subst(vmovCoreRegWIop);
156 exec_output += PredOpExecute.subst(vmovCoreRegWIop);
157
158 vmovRegCoreUBCode = '''
159 Dest = bits(FpOp1.uw, imm * 8, imm * 8 + 7);
160 '''
161 vmovRegCoreUBIop = InstObjParams("vmov", "VmovRegCoreUB", "RegRegImmOp",
162 { "code": vmovRegCoreUBCode,
163 "predicate_test": predicateTest }, [])
164 header_output += RegRegImmOpDeclare.subst(vmovRegCoreUBIop);
165 decoder_output += RegRegImmOpConstructor.subst(vmovRegCoreUBIop);
166 exec_output += PredOpExecute.subst(vmovRegCoreUBIop);
167
168 vmovRegCoreUHCode = '''
169 Dest = bits(FpOp1.uw, imm * 16, imm * 16 + 15);
170 '''
171 vmovRegCoreUHIop = InstObjParams("vmov", "VmovRegCoreUH", "RegRegImmOp",
172 { "code": vmovRegCoreUHCode,
173 "predicate_test": predicateTest }, [])
174 header_output += RegRegImmOpDeclare.subst(vmovRegCoreUHIop);
175 decoder_output += RegRegImmOpConstructor.subst(vmovRegCoreUHIop);
176 exec_output += PredOpExecute.subst(vmovRegCoreUHIop);
177
178 vmovRegCoreSBCode = '''
179 Dest = sext<8>(bits(FpOp1.uw, imm * 8, imm * 8 + 7));
180 '''
181 vmovRegCoreSBIop = InstObjParams("vmov", "VmovRegCoreSB", "RegRegImmOp",
182 { "code": vmovRegCoreSBCode,
183 "predicate_test": predicateTest }, [])
184 header_output += RegRegImmOpDeclare.subst(vmovRegCoreSBIop);
185 decoder_output += RegRegImmOpConstructor.subst(vmovRegCoreSBIop);
186 exec_output += PredOpExecute.subst(vmovRegCoreSBIop);
187
188 vmovRegCoreSHCode = '''
189 Dest = sext<16>(bits(FpOp1.uw, imm * 16, imm * 16 + 15));
190 '''
191 vmovRegCoreSHIop = InstObjParams("vmov", "VmovRegCoreSH", "RegRegImmOp",
192 { "code": vmovRegCoreSHCode,
193 "predicate_test": predicateTest }, [])
194 header_output += RegRegImmOpDeclare.subst(vmovRegCoreSHIop);
195 decoder_output += RegRegImmOpConstructor.subst(vmovRegCoreSHIop);
196 exec_output += PredOpExecute.subst(vmovRegCoreSHIop);
197
198 vmovRegCoreWCode = '''
199 Dest = FpOp1.uw;
200 '''
201 vmovRegCoreWIop = InstObjParams("vmov", "VmovRegCoreW", "RegRegOp",
202 { "code": vmovRegCoreWCode,
203 "predicate_test": predicateTest }, [])
204 header_output += RegRegOpDeclare.subst(vmovRegCoreWIop);
205 decoder_output += RegRegOpConstructor.subst(vmovRegCoreWIop);
206 exec_output += PredOpExecute.subst(vmovRegCoreWIop);
207
208 vmov2Reg2CoreCode = '''
209 FpDestP0.uw = Op1.uw;
210 FpDestP1.uw = Op2.uw;
211 '''
212 vmov2Reg2CoreIop = InstObjParams("vmov", "Vmov2Reg2Core", "RegRegRegOp",
213 { "code": vmov2Reg2CoreCode,
214 "predicate_test": predicateTest }, [])
215 header_output += RegRegRegOpDeclare.subst(vmov2Reg2CoreIop);
216 decoder_output += RegRegRegOpConstructor.subst(vmov2Reg2CoreIop);
217 exec_output += PredOpExecute.subst(vmov2Reg2CoreIop);
218
219 vmov2Core2RegCode = '''
220 Dest.uw = FpOp2P0.uw;
221 Op1.uw = FpOp2P1.uw;
222 '''
223 vmov2Core2RegIop = InstObjParams("vmov", "Vmov2Core2Reg", "RegRegRegOp",
224 { "code": vmov2Core2RegCode,
225 "predicate_test": predicateTest }, [])
226 header_output += RegRegRegOpDeclare.subst(vmov2Core2RegIop);
227 decoder_output += RegRegRegOpConstructor.subst(vmov2Core2RegIop);
228 exec_output += PredOpExecute.subst(vmov2Core2RegIop);
229
230 vmulSCode = '''
231 FpDest = FpOp1 * FpOp2;
232 if ((isinf(FpOp1) && FpOp2 == 0) || (isinf(FpOp2) && FpOp1 == 0)) {
233 FpDest = NAN;
234 }
235 '''
236 vmulSIop = InstObjParams("vmuls", "VmulS", "RegRegRegOp",
237 { "code": vmulSCode,
238 "predicate_test": predicateTest }, [])
239 header_output += RegRegRegOpDeclare.subst(vmulSIop);
240 decoder_output += RegRegRegOpConstructor.subst(vmulSIop);
241 exec_output += PredOpExecute.subst(vmulSIop);
242
243 vmulDCode = '''
244 IntDoubleUnion cOp1, cOp2, cDest;
245 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
246 cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32));
247 cDest.fp = cOp1.fp * cOp2.fp;
248 if ((isinf(cOp1.fp) && cOp2.fp == 0) ||
249 (isinf(cOp2.fp) && cOp1.fp == 0)) {
250 cDest.fp = NAN;
251 }
252 FpDestP0.uw = cDest.bits;
253 FpDestP1.uw = cDest.bits >> 32;
254 '''
255 vmulDIop = InstObjParams("vmuld", "VmulD", "RegRegRegOp",
256 { "code": vmulDCode,
257 "predicate_test": predicateTest }, [])
258 header_output += RegRegRegOpDeclare.subst(vmulDIop);
259 decoder_output += RegRegRegOpConstructor.subst(vmulDIop);
260 exec_output += PredOpExecute.subst(vmulDIop);
| 1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder. You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated
12// unmodified and in its entirety in all distributions of the software,
13// modified or unmodified, in source code or in binary form.
14//
15// Redistribution and use in source and binary forms, with or without
16// modification, are permitted provided that the following conditions are
17// met: redistributions of source code must retain the above copyright
18// notice, this list of conditions and the following disclaimer;
19// redistributions in binary form must reproduce the above copyright
20// notice, this list of conditions and the following disclaimer in the
21// documentation and/or other materials provided with the distribution;
22// neither the name of the copyright holders nor the names of its
23// contributors may be used to endorse or promote products derived from
24// this software without specific prior written permission.
25//
26// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
27// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
28// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
29// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
30// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
31// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
32// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
33// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
34// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
35// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
36// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37//
38// Authors: Gabe Black
39
40let {{
41
42 header_output = ""
43 decoder_output = ""
44 exec_output = ""
45
46 vmsrIop = InstObjParams("vmsr", "Vmsr", "RegRegOp",
47 { "code": "MiscDest = Op1;",
48 "predicate_test": predicateTest }, [])
49 header_output += RegRegOpDeclare.subst(vmsrIop);
50 decoder_output += RegRegOpConstructor.subst(vmsrIop);
51 exec_output += PredOpExecute.subst(vmsrIop);
52
53 vmrsIop = InstObjParams("vmrs", "Vmrs", "RegRegOp",
54 { "code": "Dest = MiscOp1;",
55 "predicate_test": predicateTest }, [])
56 header_output += RegRegOpDeclare.subst(vmrsIop);
57 decoder_output += RegRegOpConstructor.subst(vmrsIop);
58 exec_output += PredOpExecute.subst(vmrsIop);
59
60 vmovImmSCode = '''
61 FpDest.uw = bits(imm, 31, 0);
62 '''
63 vmovImmSIop = InstObjParams("vmov", "VmovImmS", "RegImmOp",
64 { "code": vmovImmSCode,
65 "predicate_test": predicateTest }, [])
66 header_output += RegImmOpDeclare.subst(vmovImmSIop);
67 decoder_output += RegImmOpConstructor.subst(vmovImmSIop);
68 exec_output += PredOpExecute.subst(vmovImmSIop);
69
70 vmovImmDCode = '''
71 FpDestP0.uw = bits(imm, 31, 0);
72 FpDestP1.uw = bits(imm, 63, 32);
73 '''
74 vmovImmDIop = InstObjParams("vmov", "VmovImmD", "RegImmOp",
75 { "code": vmovImmDCode,
76 "predicate_test": predicateTest }, [])
77 header_output += RegImmOpDeclare.subst(vmovImmDIop);
78 decoder_output += RegImmOpConstructor.subst(vmovImmDIop);
79 exec_output += PredOpExecute.subst(vmovImmDIop);
80
81 vmovImmQCode = '''
82 FpDestP0.uw = bits(imm, 31, 0);
83 FpDestP1.uw = bits(imm, 63, 32);
84 FpDestP2.uw = bits(imm, 31, 0);
85 FpDestP3.uw = bits(imm, 63, 32);
86 '''
87 vmovImmQIop = InstObjParams("vmov", "VmovImmQ", "RegImmOp",
88 { "code": vmovImmQCode,
89 "predicate_test": predicateTest }, [])
90 header_output += RegImmOpDeclare.subst(vmovImmQIop);
91 decoder_output += RegImmOpConstructor.subst(vmovImmQIop);
92 exec_output += PredOpExecute.subst(vmovImmQIop);
93
94 vmovRegSCode = '''
95 FpDest.uw = FpOp1.uw;
96 '''
97 vmovRegSIop = InstObjParams("vmov", "VmovRegS", "RegRegOp",
98 { "code": vmovRegSCode,
99 "predicate_test": predicateTest }, [])
100 header_output += RegRegOpDeclare.subst(vmovRegSIop);
101 decoder_output += RegRegOpConstructor.subst(vmovRegSIop);
102 exec_output += PredOpExecute.subst(vmovRegSIop);
103
104 vmovRegDCode = '''
105 FpDestP0.uw = FpOp1P0.uw;
106 FpDestP1.uw = FpOp1P1.uw;
107 '''
108 vmovRegDIop = InstObjParams("vmov", "VmovRegD", "RegRegOp",
109 { "code": vmovRegDCode,
110 "predicate_test": predicateTest }, [])
111 header_output += RegRegOpDeclare.subst(vmovRegDIop);
112 decoder_output += RegRegOpConstructor.subst(vmovRegDIop);
113 exec_output += PredOpExecute.subst(vmovRegDIop);
114
115 vmovRegQCode = '''
116 FpDestP0.uw = FpOp1P0.uw;
117 FpDestP1.uw = FpOp1P1.uw;
118 FpDestP2.uw = FpOp1P2.uw;
119 FpDestP3.uw = FpOp1P3.uw;
120 '''
121 vmovRegQIop = InstObjParams("vmov", "VmovRegQ", "RegRegOp",
122 { "code": vmovRegQCode,
123 "predicate_test": predicateTest }, [])
124 header_output += RegRegOpDeclare.subst(vmovRegQIop);
125 decoder_output += RegRegOpConstructor.subst(vmovRegQIop);
126 exec_output += PredOpExecute.subst(vmovRegQIop);
127
128 vmovCoreRegBCode = '''
129 FpDest.uw = insertBits(FpDest.uw, imm * 8, imm * 8 + 7, Op1.ub);
130 '''
131 vmovCoreRegBIop = InstObjParams("vmov", "VmovCoreRegB", "RegRegImmOp",
132 { "code": vmovCoreRegBCode,
133 "predicate_test": predicateTest }, [])
134 header_output += RegRegImmOpDeclare.subst(vmovCoreRegBIop);
135 decoder_output += RegRegImmOpConstructor.subst(vmovCoreRegBIop);
136 exec_output += PredOpExecute.subst(vmovCoreRegBIop);
137
138 vmovCoreRegHCode = '''
139 FpDest.uw = insertBits(FpDest.uw, imm * 16, imm * 16 + 15, Op1.uh);
140 '''
141 vmovCoreRegHIop = InstObjParams("vmov", "VmovCoreRegH", "RegRegImmOp",
142 { "code": vmovCoreRegHCode,
143 "predicate_test": predicateTest }, [])
144 header_output += RegRegImmOpDeclare.subst(vmovCoreRegHIop);
145 decoder_output += RegRegImmOpConstructor.subst(vmovCoreRegHIop);
146 exec_output += PredOpExecute.subst(vmovCoreRegHIop);
147
148 vmovCoreRegWCode = '''
149 FpDest.uw = Op1.uw;
150 '''
151 vmovCoreRegWIop = InstObjParams("vmov", "VmovCoreRegW", "RegRegOp",
152 { "code": vmovCoreRegWCode,
153 "predicate_test": predicateTest }, [])
154 header_output += RegRegOpDeclare.subst(vmovCoreRegWIop);
155 decoder_output += RegRegOpConstructor.subst(vmovCoreRegWIop);
156 exec_output += PredOpExecute.subst(vmovCoreRegWIop);
157
158 vmovRegCoreUBCode = '''
159 Dest = bits(FpOp1.uw, imm * 8, imm * 8 + 7);
160 '''
161 vmovRegCoreUBIop = InstObjParams("vmov", "VmovRegCoreUB", "RegRegImmOp",
162 { "code": vmovRegCoreUBCode,
163 "predicate_test": predicateTest }, [])
164 header_output += RegRegImmOpDeclare.subst(vmovRegCoreUBIop);
165 decoder_output += RegRegImmOpConstructor.subst(vmovRegCoreUBIop);
166 exec_output += PredOpExecute.subst(vmovRegCoreUBIop);
167
168 vmovRegCoreUHCode = '''
169 Dest = bits(FpOp1.uw, imm * 16, imm * 16 + 15);
170 '''
171 vmovRegCoreUHIop = InstObjParams("vmov", "VmovRegCoreUH", "RegRegImmOp",
172 { "code": vmovRegCoreUHCode,
173 "predicate_test": predicateTest }, [])
174 header_output += RegRegImmOpDeclare.subst(vmovRegCoreUHIop);
175 decoder_output += RegRegImmOpConstructor.subst(vmovRegCoreUHIop);
176 exec_output += PredOpExecute.subst(vmovRegCoreUHIop);
177
178 vmovRegCoreSBCode = '''
179 Dest = sext<8>(bits(FpOp1.uw, imm * 8, imm * 8 + 7));
180 '''
181 vmovRegCoreSBIop = InstObjParams("vmov", "VmovRegCoreSB", "RegRegImmOp",
182 { "code": vmovRegCoreSBCode,
183 "predicate_test": predicateTest }, [])
184 header_output += RegRegImmOpDeclare.subst(vmovRegCoreSBIop);
185 decoder_output += RegRegImmOpConstructor.subst(vmovRegCoreSBIop);
186 exec_output += PredOpExecute.subst(vmovRegCoreSBIop);
187
188 vmovRegCoreSHCode = '''
189 Dest = sext<16>(bits(FpOp1.uw, imm * 16, imm * 16 + 15));
190 '''
191 vmovRegCoreSHIop = InstObjParams("vmov", "VmovRegCoreSH", "RegRegImmOp",
192 { "code": vmovRegCoreSHCode,
193 "predicate_test": predicateTest }, [])
194 header_output += RegRegImmOpDeclare.subst(vmovRegCoreSHIop);
195 decoder_output += RegRegImmOpConstructor.subst(vmovRegCoreSHIop);
196 exec_output += PredOpExecute.subst(vmovRegCoreSHIop);
197
198 vmovRegCoreWCode = '''
199 Dest = FpOp1.uw;
200 '''
201 vmovRegCoreWIop = InstObjParams("vmov", "VmovRegCoreW", "RegRegOp",
202 { "code": vmovRegCoreWCode,
203 "predicate_test": predicateTest }, [])
204 header_output += RegRegOpDeclare.subst(vmovRegCoreWIop);
205 decoder_output += RegRegOpConstructor.subst(vmovRegCoreWIop);
206 exec_output += PredOpExecute.subst(vmovRegCoreWIop);
207
208 vmov2Reg2CoreCode = '''
209 FpDestP0.uw = Op1.uw;
210 FpDestP1.uw = Op2.uw;
211 '''
212 vmov2Reg2CoreIop = InstObjParams("vmov", "Vmov2Reg2Core", "RegRegRegOp",
213 { "code": vmov2Reg2CoreCode,
214 "predicate_test": predicateTest }, [])
215 header_output += RegRegRegOpDeclare.subst(vmov2Reg2CoreIop);
216 decoder_output += RegRegRegOpConstructor.subst(vmov2Reg2CoreIop);
217 exec_output += PredOpExecute.subst(vmov2Reg2CoreIop);
218
219 vmov2Core2RegCode = '''
220 Dest.uw = FpOp2P0.uw;
221 Op1.uw = FpOp2P1.uw;
222 '''
223 vmov2Core2RegIop = InstObjParams("vmov", "Vmov2Core2Reg", "RegRegRegOp",
224 { "code": vmov2Core2RegCode,
225 "predicate_test": predicateTest }, [])
226 header_output += RegRegRegOpDeclare.subst(vmov2Core2RegIop);
227 decoder_output += RegRegRegOpConstructor.subst(vmov2Core2RegIop);
228 exec_output += PredOpExecute.subst(vmov2Core2RegIop);
229
230 vmulSCode = '''
231 FpDest = FpOp1 * FpOp2;
232 if ((isinf(FpOp1) && FpOp2 == 0) || (isinf(FpOp2) && FpOp1 == 0)) {
233 FpDest = NAN;
234 }
235 '''
236 vmulSIop = InstObjParams("vmuls", "VmulS", "RegRegRegOp",
237 { "code": vmulSCode,
238 "predicate_test": predicateTest }, [])
239 header_output += RegRegRegOpDeclare.subst(vmulSIop);
240 decoder_output += RegRegRegOpConstructor.subst(vmulSIop);
241 exec_output += PredOpExecute.subst(vmulSIop);
242
243 vmulDCode = '''
244 IntDoubleUnion cOp1, cOp2, cDest;
245 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
246 cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32));
247 cDest.fp = cOp1.fp * cOp2.fp;
248 if ((isinf(cOp1.fp) && cOp2.fp == 0) ||
249 (isinf(cOp2.fp) && cOp1.fp == 0)) {
250 cDest.fp = NAN;
251 }
252 FpDestP0.uw = cDest.bits;
253 FpDestP1.uw = cDest.bits >> 32;
254 '''
255 vmulDIop = InstObjParams("vmuld", "VmulD", "RegRegRegOp",
256 { "code": vmulDCode,
257 "predicate_test": predicateTest }, [])
258 header_output += RegRegRegOpDeclare.subst(vmulDIop);
259 decoder_output += RegRegRegOpConstructor.subst(vmulDIop);
260 exec_output += PredOpExecute.subst(vmulDIop);
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