fp.isa (7388:293878a9d220) | fp.isa (7389:714dea5b5298) |
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1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating --- 1087 unchanged lines hidden (view full) --- 1096 vcvtFpDFpSIop = InstObjParams("vcvt", "VcvtFpDFpS", "VfpRegRegOp", 1097 { "code": vcvtFpDFpSCode, 1098 "predicate_test": predicateTest }, []) 1099 header_output += VfpRegRegOpDeclare.subst(vcvtFpDFpSIop); 1100 decoder_output += VfpRegRegOpConstructor.subst(vcvtFpDFpSIop); 1101 exec_output += PredOpExecute.subst(vcvtFpDFpSIop); 1102 1103 vcmpSCode = ''' | 1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating --- 1087 unchanged lines hidden (view full) --- 1096 vcvtFpDFpSIop = InstObjParams("vcvt", "VcvtFpDFpS", "VfpRegRegOp", 1097 { "code": vcvtFpDFpSCode, 1098 "predicate_test": predicateTest }, []) 1099 header_output += VfpRegRegOpDeclare.subst(vcvtFpDFpSIop); 1100 decoder_output += VfpRegRegOpConstructor.subst(vcvtFpDFpSIop); 1101 exec_output += PredOpExecute.subst(vcvtFpDFpSIop); 1102 1103 vcmpSCode = ''' |
1104 FPSCR fpscr = Fpscr; | |
1105 vfpFlushToZero(Fpscr, FpDest, FpOp1); | 1104 vfpFlushToZero(Fpscr, FpDest, FpOp1); |
1105 FPSCR fpscr = Fpscr; |
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1106 if (FpDest == FpOp1) { 1107 fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 1108 } else if (FpDest < FpOp1) { 1109 fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 1110 } else if (FpDest > FpOp1) { 1111 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 1112 } else { | 1106 if (FpDest == FpOp1) { 1107 fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 1108 } else if (FpDest < FpOp1) { 1109 fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 1110 } else if (FpDest > FpOp1) { 1111 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 1112 } else { |
1113 const uint32_t qnan = 0x7fc00000; 1114 union 1115 { 1116 float fp; 1117 uint32_t bits; 1118 } cvtr; 1119 cvtr.fp = FpDest; 1120 const bool nan1 = std::isnan(FpDest); 1121 const bool signal1 = nan1 && ((cvtr.bits & qnan) != qnan); 1122 cvtr.fp = FpOp1; 1123 const bool nan2 = std::isnan(FpOp1); 1124 const bool signal2 = nan2 && ((cvtr.bits & qnan) != qnan); 1125 if (signal1 || signal2) 1126 fpscr.ioc = 1; |
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1113 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 1114 } 1115 Fpscr = fpscr; 1116 ''' 1117 vcmpSIop = InstObjParams("vcmps", "VcmpS", "VfpRegRegOp", 1118 { "code": vcmpSCode, 1119 "predicate_test": predicateTest }, []) 1120 header_output += VfpRegRegOpDeclare.subst(vcmpSIop); --- 8 unchanged lines hidden (view full) --- 1129 FPSCR fpscr = Fpscr; 1130 if (cDest.fp == cOp1.fp) { 1131 fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 1132 } else if (cDest.fp < cOp1.fp) { 1133 fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 1134 } else if (cDest.fp > cOp1.fp) { 1135 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 1136 } else { | 1127 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 1128 } 1129 Fpscr = fpscr; 1130 ''' 1131 vcmpSIop = InstObjParams("vcmps", "VcmpS", "VfpRegRegOp", 1132 { "code": vcmpSCode, 1133 "predicate_test": predicateTest }, []) 1134 header_output += VfpRegRegOpDeclare.subst(vcmpSIop); --- 8 unchanged lines hidden (view full) --- 1143 FPSCR fpscr = Fpscr; 1144 if (cDest.fp == cOp1.fp) { 1145 fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 1146 } else if (cDest.fp < cOp1.fp) { 1147 fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 1148 } else if (cDest.fp > cOp1.fp) { 1149 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 1150 } else { |
1151 const uint64_t qnan = ULL(0x7ff8000000000000); 1152 const bool nan1 = std::isnan(cDest.fp); 1153 const bool signal1 = nan1 && ((cDest.bits & qnan) != qnan); 1154 const bool nan2 = std::isnan(cOp1.fp); 1155 const bool signal2 = nan2 && ((cOp1.bits & qnan) != qnan); 1156 if (signal1 || signal2) 1157 fpscr.ioc = 1; |
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1137 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 1138 } 1139 Fpscr = fpscr; 1140 ''' 1141 vcmpDIop = InstObjParams("vcmpd", "VcmpD", "VfpRegRegOp", 1142 { "code": vcmpDCode, 1143 "predicate_test": predicateTest }, []) 1144 header_output += VfpRegRegOpDeclare.subst(vcmpDIop); 1145 decoder_output += VfpRegRegOpConstructor.subst(vcmpDIop); 1146 exec_output += PredOpExecute.subst(vcmpDIop); 1147 1148 vcmpZeroSCode = ''' | 1158 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 1159 } 1160 Fpscr = fpscr; 1161 ''' 1162 vcmpDIop = InstObjParams("vcmpd", "VcmpD", "VfpRegRegOp", 1163 { "code": vcmpDCode, 1164 "predicate_test": predicateTest }, []) 1165 header_output += VfpRegRegOpDeclare.subst(vcmpDIop); 1166 decoder_output += VfpRegRegOpConstructor.subst(vcmpDIop); 1167 exec_output += PredOpExecute.subst(vcmpDIop); 1168 1169 vcmpZeroSCode = ''' |
1149 FPSCR fpscr = Fpscr; | |
1150 vfpFlushToZero(Fpscr, FpDest); | 1170 vfpFlushToZero(Fpscr, FpDest); |
1171 FPSCR fpscr = Fpscr; 1172 // This only handles imm == 0 for now. 1173 assert(imm == 0); |
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1151 if (FpDest == imm) { 1152 fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 1153 } else if (FpDest < imm) { 1154 fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 1155 } else if (FpDest > imm) { 1156 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 1157 } else { | 1174 if (FpDest == imm) { 1175 fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 1176 } else if (FpDest < imm) { 1177 fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 1178 } else if (FpDest > imm) { 1179 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 1180 } else { |
1181 const uint32_t qnan = 0x7fc00000; 1182 union 1183 { 1184 float fp; 1185 uint32_t bits; 1186 } cvtr; 1187 cvtr.fp = FpDest; 1188 const bool nan = std::isnan(FpDest); 1189 const bool signal = nan && ((cvtr.bits & qnan) != qnan); 1190 if (signal) 1191 fpscr.ioc = 1; |
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1158 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 1159 } 1160 Fpscr = fpscr; 1161 ''' 1162 vcmpZeroSIop = InstObjParams("vcmpZeros", "VcmpZeroS", "VfpRegImmOp", 1163 { "code": vcmpZeroSCode, 1164 "predicate_test": predicateTest }, []) 1165 header_output += VfpRegImmOpDeclare.subst(vcmpZeroSIop); 1166 decoder_output += VfpRegImmOpConstructor.subst(vcmpZeroSIop); 1167 exec_output += PredOpExecute.subst(vcmpZeroSIop); 1168 1169 vcmpZeroDCode = ''' 1170 IntDoubleUnion cDest; | 1192 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 1193 } 1194 Fpscr = fpscr; 1195 ''' 1196 vcmpZeroSIop = InstObjParams("vcmpZeros", "VcmpZeroS", "VfpRegImmOp", 1197 { "code": vcmpZeroSCode, 1198 "predicate_test": predicateTest }, []) 1199 header_output += VfpRegImmOpDeclare.subst(vcmpZeroSIop); 1200 decoder_output += VfpRegImmOpConstructor.subst(vcmpZeroSIop); 1201 exec_output += PredOpExecute.subst(vcmpZeroSIop); 1202 1203 vcmpZeroDCode = ''' 1204 IntDoubleUnion cDest; |
1205 // This only handles imm == 0 for now. 1206 assert(imm == 0); |
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1171 cDest.bits = ((uint64_t)FpDestP0.uw | ((uint64_t)FpDestP1.uw << 32)); 1172 vfpFlushToZero(Fpscr, cDest.fp); 1173 FPSCR fpscr = Fpscr; 1174 if (cDest.fp == imm) { 1175 fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 1176 } else if (cDest.fp < imm) { 1177 fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 1178 } else if (cDest.fp > imm) { 1179 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 1180 } else { | 1207 cDest.bits = ((uint64_t)FpDestP0.uw | ((uint64_t)FpDestP1.uw << 32)); 1208 vfpFlushToZero(Fpscr, cDest.fp); 1209 FPSCR fpscr = Fpscr; 1210 if (cDest.fp == imm) { 1211 fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 1212 } else if (cDest.fp < imm) { 1213 fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 1214 } else if (cDest.fp > imm) { 1215 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 1216 } else { |
1217 const uint64_t qnan = ULL(0x7ff8000000000000); 1218 const bool nan = std::isnan(cDest.fp); 1219 const bool signal = nan && ((cDest.bits & qnan) != qnan); 1220 if (signal) 1221 fpscr.ioc = 1; |
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1181 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 1182 } 1183 Fpscr = fpscr; 1184 ''' 1185 vcmpZeroDIop = InstObjParams("vcmpZerod", "VcmpZeroD", "VfpRegImmOp", 1186 { "code": vcmpZeroDCode, 1187 "predicate_test": predicateTest }, []) 1188 header_output += VfpRegImmOpDeclare.subst(vcmpZeroDIop); 1189 decoder_output += VfpRegImmOpConstructor.subst(vcmpZeroDIop); 1190 exec_output += PredOpExecute.subst(vcmpZeroDIop); | 1222 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 1223 } 1224 Fpscr = fpscr; 1225 ''' 1226 vcmpZeroDIop = InstObjParams("vcmpZerod", "VcmpZeroD", "VfpRegImmOp", 1227 { "code": vcmpZeroDCode, 1228 "predicate_test": predicateTest }, []) 1229 header_output += VfpRegImmOpDeclare.subst(vcmpZeroDIop); 1230 decoder_output += VfpRegImmOpConstructor.subst(vcmpZeroDIop); 1231 exec_output += PredOpExecute.subst(vcmpZeroDIop); |
1232 1233 vcmpeSCode = ''' 1234 vfpFlushToZero(Fpscr, FpDest, FpOp1); 1235 FPSCR fpscr = Fpscr; 1236 if (FpDest == FpOp1) { 1237 fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 1238 } else if (FpDest < FpOp1) { 1239 fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 1240 } else if (FpDest > FpOp1) { 1241 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 1242 } else { 1243 fpscr.ioc = 1; 1244 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 1245 } 1246 Fpscr = fpscr; 1247 ''' 1248 vcmpeSIop = InstObjParams("vcmpes", "VcmpeS", "VfpRegRegOp", 1249 { "code": vcmpeSCode, 1250 "predicate_test": predicateTest }, []) 1251 header_output += VfpRegRegOpDeclare.subst(vcmpeSIop); 1252 decoder_output += VfpRegRegOpConstructor.subst(vcmpeSIop); 1253 exec_output += PredOpExecute.subst(vcmpeSIop); 1254 1255 vcmpeDCode = ''' 1256 IntDoubleUnion cOp1, cDest; 1257 cDest.bits = ((uint64_t)FpDestP0.uw | ((uint64_t)FpDestP1.uw << 32)); 1258 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 1259 vfpFlushToZero(Fpscr, cDest.fp, cOp1.fp); 1260 FPSCR fpscr = Fpscr; 1261 if (cDest.fp == cOp1.fp) { 1262 fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 1263 } else if (cDest.fp < cOp1.fp) { 1264 fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 1265 } else if (cDest.fp > cOp1.fp) { 1266 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 1267 } else { 1268 fpscr.ioc = 1; 1269 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 1270 } 1271 Fpscr = fpscr; 1272 ''' 1273 vcmpeDIop = InstObjParams("vcmped", "VcmpeD", "VfpRegRegOp", 1274 { "code": vcmpeDCode, 1275 "predicate_test": predicateTest }, []) 1276 header_output += VfpRegRegOpDeclare.subst(vcmpeDIop); 1277 decoder_output += VfpRegRegOpConstructor.subst(vcmpeDIop); 1278 exec_output += PredOpExecute.subst(vcmpeDIop); 1279 1280 vcmpeZeroSCode = ''' 1281 vfpFlushToZero(Fpscr, FpDest); 1282 FPSCR fpscr = Fpscr; 1283 if (FpDest == imm) { 1284 fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 1285 } else if (FpDest < imm) { 1286 fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 1287 } else if (FpDest > imm) { 1288 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 1289 } else { 1290 fpscr.ioc = 1; 1291 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 1292 } 1293 Fpscr = fpscr; 1294 ''' 1295 vcmpeZeroSIop = InstObjParams("vcmpeZeros", "VcmpeZeroS", "VfpRegImmOp", 1296 { "code": vcmpeZeroSCode, 1297 "predicate_test": predicateTest }, []) 1298 header_output += VfpRegImmOpDeclare.subst(vcmpeZeroSIop); 1299 decoder_output += VfpRegImmOpConstructor.subst(vcmpeZeroSIop); 1300 exec_output += PredOpExecute.subst(vcmpeZeroSIop); 1301 1302 vcmpeZeroDCode = ''' 1303 IntDoubleUnion cDest; 1304 cDest.bits = ((uint64_t)FpDestP0.uw | ((uint64_t)FpDestP1.uw << 32)); 1305 vfpFlushToZero(Fpscr, cDest.fp); 1306 FPSCR fpscr = Fpscr; 1307 if (cDest.fp == imm) { 1308 fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 1309 } else if (cDest.fp < imm) { 1310 fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 1311 } else if (cDest.fp > imm) { 1312 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 1313 } else { 1314 fpscr.ioc = 1; 1315 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 1316 } 1317 Fpscr = fpscr; 1318 ''' 1319 vcmpeZeroDIop = InstObjParams("vcmpeZerod", "VcmpeZeroD", "VfpRegImmOp", 1320 { "code": vcmpeZeroDCode, 1321 "predicate_test": predicateTest }, []) 1322 header_output += VfpRegImmOpDeclare.subst(vcmpeZeroDIop); 1323 decoder_output += VfpRegImmOpConstructor.subst(vcmpeZeroDIop); 1324 exec_output += PredOpExecute.subst(vcmpeZeroDIop); |
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1191}}; 1192 1193let {{ 1194 1195 header_output = "" 1196 decoder_output = "" 1197 exec_output = "" 1198 --- 272 unchanged lines hidden --- | 1325}}; 1326 1327let {{ 1328 1329 header_output = "" 1330 decoder_output = "" 1331 exec_output = "" 1332 --- 272 unchanged lines hidden --- |