fp.isa (7370:6fa1e296585d) | fp.isa (7371:83612101a826) |
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1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating --- 467 unchanged lines hidden (view full) --- 476 FpDestP1.uw = cDest.bits >> 32; 477 ''' 478 vmlsDIop = InstObjParams("vmlsd", "VmlsD", "RegRegRegOp", 479 { "code": vmlsDCode, 480 "predicate_test": predicateTest }, []) 481 header_output += RegRegRegOpDeclare.subst(vmlsDIop); 482 decoder_output += RegRegRegOpConstructor.subst(vmlsDIop); 483 exec_output += PredOpExecute.subst(vmlsDIop); | 1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating --- 467 unchanged lines hidden (view full) --- 476 FpDestP1.uw = cDest.bits >> 32; 477 ''' 478 vmlsDIop = InstObjParams("vmlsd", "VmlsD", "RegRegRegOp", 479 { "code": vmlsDCode, 480 "predicate_test": predicateTest }, []) 481 header_output += RegRegRegOpDeclare.subst(vmlsDIop); 482 decoder_output += RegRegRegOpConstructor.subst(vmlsDIop); 483 exec_output += PredOpExecute.subst(vmlsDIop); |
484 485 vnmlaSCode = ''' 486 float mid = FpOp1 * FpOp2; 487 if ((isinf(FpOp1) && FpOp2 == 0) || (isinf(FpOp2) && FpOp1 == 0)) { 488 mid = NAN; 489 } 490 FpDest = -FpDest - mid; 491 ''' 492 vnmlaSIop = InstObjParams("vnmlas", "VnmlaS", "RegRegRegOp", 493 { "code": vnmlaSCode, 494 "predicate_test": predicateTest }, []) 495 header_output += RegRegRegOpDeclare.subst(vnmlaSIop); 496 decoder_output += RegRegRegOpConstructor.subst(vnmlaSIop); 497 exec_output += PredOpExecute.subst(vnmlaSIop); 498 499 vnmlaDCode = ''' 500 IntDoubleUnion cOp1, cOp2, cDest; 501 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 502 cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32)); 503 cDest.bits = ((uint64_t)FpDestP0.uw | ((uint64_t)FpDestP1.uw << 32)); 504 double mid = cOp1.fp * cOp2.fp; 505 if ((isinf(cOp1.fp) && cOp2.fp == 0) || 506 (isinf(cOp2.fp) && cOp1.fp == 0)) { 507 mid = NAN; 508 } 509 cDest.fp = -cDest.fp - mid; 510 FpDestP0.uw = cDest.bits; 511 FpDestP1.uw = cDest.bits >> 32; 512 ''' 513 vnmlaDIop = InstObjParams("vnmlad", "VnmlaD", "RegRegRegOp", 514 { "code": vnmlaDCode, 515 "predicate_test": predicateTest }, []) 516 header_output += RegRegRegOpDeclare.subst(vnmlaDIop); 517 decoder_output += RegRegRegOpConstructor.subst(vnmlaDIop); 518 exec_output += PredOpExecute.subst(vnmlaDIop); 519 520 vnmlsSCode = ''' 521 float mid = FpOp1 * FpOp2; 522 if ((isinf(FpOp1) && FpOp2 == 0) || (isinf(FpOp2) && FpOp1 == 0)) { 523 mid = NAN; 524 } 525 FpDest = -FpDest + mid; 526 ''' 527 vnmlsSIop = InstObjParams("vnmlss", "VnmlsS", "RegRegRegOp", 528 { "code": vnmlsSCode, 529 "predicate_test": predicateTest }, []) 530 header_output += RegRegRegOpDeclare.subst(vnmlsSIop); 531 decoder_output += RegRegRegOpConstructor.subst(vnmlsSIop); 532 exec_output += PredOpExecute.subst(vnmlsSIop); 533 534 vnmlsDCode = ''' 535 IntDoubleUnion cOp1, cOp2, cDest; 536 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 537 cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32)); 538 cDest.bits = ((uint64_t)FpDestP0.uw | ((uint64_t)FpDestP1.uw << 32)); 539 double mid = cOp1.fp * cOp2.fp; 540 if ((isinf(cOp1.fp) && cOp2.fp == 0) || 541 (isinf(cOp2.fp) && cOp1.fp == 0)) { 542 mid = NAN; 543 } 544 cDest.fp = -cDest.fp + mid; 545 FpDestP0.uw = cDest.bits; 546 FpDestP1.uw = cDest.bits >> 32; 547 ''' 548 vnmlsDIop = InstObjParams("vnmlsd", "VnmlsD", "RegRegRegOp", 549 { "code": vnmlsDCode, 550 "predicate_test": predicateTest }, []) 551 header_output += RegRegRegOpDeclare.subst(vnmlsDIop); 552 decoder_output += RegRegRegOpConstructor.subst(vnmlsDIop); 553 exec_output += PredOpExecute.subst(vnmlsDIop); 554 555 vnmulSCode = ''' 556 float mid = FpOp1 * FpOp2; 557 if ((isinf(FpOp1) && FpOp2 == 0) || (isinf(FpOp2) && FpOp1 == 0)) { 558 mid = NAN; 559 } 560 FpDest = -mid; 561 ''' 562 vnmulSIop = InstObjParams("vnmuls", "VnmulS", "RegRegRegOp", 563 { "code": vnmulSCode, 564 "predicate_test": predicateTest }, []) 565 header_output += RegRegRegOpDeclare.subst(vnmulSIop); 566 decoder_output += RegRegRegOpConstructor.subst(vnmulSIop); 567 exec_output += PredOpExecute.subst(vnmulSIop); 568 569 vnmulDCode = ''' 570 IntDoubleUnion cOp1, cOp2, cDest; 571 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 572 cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32)); 573 cDest.bits = ((uint64_t)FpDestP0.uw | ((uint64_t)FpDestP1.uw << 32)); 574 double mid = cOp1.fp * cOp2.fp; 575 if ((isinf(cOp1.fp) && cOp2.fp == 0) || 576 (isinf(cOp2.fp) && cOp1.fp == 0)) { 577 mid = NAN; 578 } 579 cDest.fp = -mid; 580 FpDestP0.uw = cDest.bits; 581 FpDestP1.uw = cDest.bits >> 32; 582 ''' 583 vnmulDIop = InstObjParams("vnmuld", "VnmulD", "RegRegRegOp", 584 { "code": vnmulDCode, 585 "predicate_test": predicateTest }, []) 586 header_output += RegRegRegOpDeclare.subst(vnmulDIop); 587 decoder_output += RegRegRegOpConstructor.subst(vnmulDIop); 588 exec_output += PredOpExecute.subst(vnmulDIop); |
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484}}; | 589}}; |