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1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 268 unchanged lines hidden (view full) ---

277 vmovRegQIop = InstObjParams("vmov", "VmovRegQ", "FpRegRegOp",
278 { "code": vmovRegQCode,
279 "predicate_test": predicateTest }, [])
280 header_output += FpRegRegOpDeclare.subst(vmovRegQIop);
281 decoder_output += FpRegRegOpConstructor.subst(vmovRegQIop);
282 exec_output += PredOpExecute.subst(vmovRegQIop);
283
284 vmovCoreRegBCode = '''
285 FpDest.uw = insertBits(FpDest.uw, imm * 8, imm * 8 + 7, Op1.ub);
286 '''
287 vmovCoreRegBIop = InstObjParams("vmov", "VmovCoreRegB", "FpRegRegImmOp",
288 { "code": vmovCoreRegBCode,
289 "predicate_test": predicateTest }, [])
290 header_output += FpRegRegImmOpDeclare.subst(vmovCoreRegBIop);
291 decoder_output += FpRegRegImmOpConstructor.subst(vmovCoreRegBIop);
292 exec_output += PredOpExecute.subst(vmovCoreRegBIop);
293
294 vmovCoreRegHCode = '''
295 FpDest.uw = insertBits(FpDest.uw, imm * 16, imm * 16 + 15, Op1.uh);
296 '''
297 vmovCoreRegHIop = InstObjParams("vmov", "VmovCoreRegH", "FpRegRegImmOp",
298 { "code": vmovCoreRegHCode,
299 "predicate_test": predicateTest }, [])
300 header_output += FpRegRegImmOpDeclare.subst(vmovCoreRegHIop);
301 decoder_output += FpRegRegImmOpConstructor.subst(vmovCoreRegHIop);
302 exec_output += PredOpExecute.subst(vmovCoreRegHIop);
303
304 vmovCoreRegWCode = '''
305 FpDest.uw = Op1.uw;
306 '''
307 vmovCoreRegWIop = InstObjParams("vmov", "VmovCoreRegW", "FpRegRegOp",
308 { "code": vmovCoreRegWCode,
309 "predicate_test": predicateTest }, [])
310 header_output += FpRegRegOpDeclare.subst(vmovCoreRegWIop);
311 decoder_output += FpRegRegOpConstructor.subst(vmovCoreRegWIop);
312 exec_output += PredOpExecute.subst(vmovCoreRegWIop);
313
314 vmovRegCoreUBCode = '''
315 Dest = bits(FpOp1.uw, imm * 8, imm * 8 + 7);
316 '''
317 vmovRegCoreUBIop = InstObjParams("vmov", "VmovRegCoreUB", "FpRegRegImmOp",
318 { "code": vmovRegCoreUBCode,
319 "predicate_test": predicateTest }, [])
320 header_output += FpRegRegImmOpDeclare.subst(vmovRegCoreUBIop);
321 decoder_output += FpRegRegImmOpConstructor.subst(vmovRegCoreUBIop);
322 exec_output += PredOpExecute.subst(vmovRegCoreUBIop);
323
324 vmovRegCoreUHCode = '''
325 Dest = bits(FpOp1.uw, imm * 16, imm * 16 + 15);
326 '''
327 vmovRegCoreUHIop = InstObjParams("vmov", "VmovRegCoreUH", "FpRegRegImmOp",
328 { "code": vmovRegCoreUHCode,
329 "predicate_test": predicateTest }, [])
330 header_output += FpRegRegImmOpDeclare.subst(vmovRegCoreUHIop);
331 decoder_output += FpRegRegImmOpConstructor.subst(vmovRegCoreUHIop);
332 exec_output += PredOpExecute.subst(vmovRegCoreUHIop);
333
334 vmovRegCoreSBCode = '''
335 Dest = sext<8>(bits(FpOp1.uw, imm * 8, imm * 8 + 7));
336 '''
337 vmovRegCoreSBIop = InstObjParams("vmov", "VmovRegCoreSB", "FpRegRegImmOp",
338 { "code": vmovRegCoreSBCode,
339 "predicate_test": predicateTest }, [])
340 header_output += FpRegRegImmOpDeclare.subst(vmovRegCoreSBIop);
341 decoder_output += FpRegRegImmOpConstructor.subst(vmovRegCoreSBIop);
342 exec_output += PredOpExecute.subst(vmovRegCoreSBIop);
343
344 vmovRegCoreSHCode = '''
345 Dest = sext<16>(bits(FpOp1.uw, imm * 16, imm * 16 + 15));
346 '''
347 vmovRegCoreSHIop = InstObjParams("vmov", "VmovRegCoreSH", "FpRegRegImmOp",
348 { "code": vmovRegCoreSHCode,
349 "predicate_test": predicateTest }, [])
350 header_output += FpRegRegImmOpDeclare.subst(vmovRegCoreSHIop);
351 decoder_output += FpRegRegImmOpConstructor.subst(vmovRegCoreSHIop);
352 exec_output += PredOpExecute.subst(vmovRegCoreSHIop);
353

--- 37 unchanged lines hidden (view full) ---

391 exec_output = ""
392
393 singleCode = '''
394 FPSCR fpscr = Fpscr;
395 FpDest = %(op)s;
396 Fpscr = fpscr;
397 '''
398 singleBinOp = "binaryOp(fpscr, FpOp1, FpOp2," + \
399 "%(func)s, fpscr.fz, fpscr.rMode)"
400 singleUnaryOp = "unaryOp(fpscr, FpOp1, %(func)s, fpscr.fz, fpscr.rMode)"
401 doubleCode = '''
402 FPSCR fpscr = Fpscr;
403 double dest = %(op)s;
404 Fpscr = fpscr;
405 FpDestP0.uw = dblLow(dest);
406 FpDestP1.uw = dblHi(dest);
407 '''
408 doubleBinOp = '''
409 binaryOp(fpscr, dbl(FpOp1P0.uw, FpOp1P1.uw),
410 dbl(FpOp2P0.uw, FpOp2P1.uw),
411 %(func)s, fpscr.fz, fpscr.rMode);
412 '''
413 doubleUnaryOp = '''
414 unaryOp(fpscr, dbl(FpOp1P0.uw, FpOp1P1.uw), %(func)s,
415 fpscr.fz, fpscr.rMode)
416 '''
417
418 def buildBinFpOp(name, Name, base, singleOp, doubleOp):
419 global header_output, decoder_output, exec_output

--- 74 unchanged lines hidden (view full) ---

494
495 header_output = ""
496 decoder_output = ""
497 exec_output = ""
498
499 vmlaSCode = '''
500 FPSCR fpscr = Fpscr;
501 float mid = binaryOp(fpscr, FpOp1, FpOp2,
502 fpMulS, fpscr.fz, fpscr.rMode);
503 FpDest = binaryOp(fpscr, FpDest, mid, fpAddS, fpscr.fz, fpscr.rMode);
504 Fpscr = fpscr;
505 '''
506 vmlaSIop = InstObjParams("vmlas", "VmlaS", "FpRegRegRegOp",
507 { "code": vmlaSCode,
508 "predicate_test": predicateTest }, [])
509 header_output += FpRegRegRegOpDeclare.subst(vmlaSIop);
510 decoder_output += FpRegRegRegOpConstructor.subst(vmlaSIop);
511 exec_output += PredOpExecute.subst(vmlaSIop);
512
513 vmlaDCode = '''
514 FPSCR fpscr = Fpscr;
515 double mid = binaryOp(fpscr, dbl(FpOp1P0.uw, FpOp1P1.uw),
516 dbl(FpOp2P0.uw, FpOp2P1.uw),
517 fpMulD, fpscr.fz, fpscr.rMode);
518 double dest = binaryOp(fpscr, dbl(FpDestP0.uw, FpDestP1.uw),
519 mid, fpAddD, fpscr.fz, fpscr.rMode);
520 Fpscr = fpscr;
521 FpDestP0.uw = dblLow(dest);
522 FpDestP1.uw = dblHi(dest);
523 '''
524 vmlaDIop = InstObjParams("vmlad", "VmlaD", "FpRegRegRegOp",
525 { "code": vmlaDCode,
526 "predicate_test": predicateTest }, [])
527 header_output += FpRegRegRegOpDeclare.subst(vmlaDIop);
528 decoder_output += FpRegRegRegOpConstructor.subst(vmlaDIop);
529 exec_output += PredOpExecute.subst(vmlaDIop);
530
531 vmlsSCode = '''
532 FPSCR fpscr = Fpscr;
533 float mid = binaryOp(fpscr, FpOp1, FpOp2,
534 fpMulS, fpscr.fz, fpscr.rMode);
535 FpDest = binaryOp(fpscr, FpDest, -mid, fpAddS, fpscr.fz, fpscr.rMode);
536 Fpscr = fpscr;
537 '''
538 vmlsSIop = InstObjParams("vmlss", "VmlsS", "FpRegRegRegOp",
539 { "code": vmlsSCode,
540 "predicate_test": predicateTest }, [])
541 header_output += FpRegRegRegOpDeclare.subst(vmlsSIop);
542 decoder_output += FpRegRegRegOpConstructor.subst(vmlsSIop);
543 exec_output += PredOpExecute.subst(vmlsSIop);
544
545 vmlsDCode = '''
546 FPSCR fpscr = Fpscr;
547 double mid = binaryOp(fpscr, dbl(FpOp1P0.uw, FpOp1P1.uw),
548 dbl(FpOp2P0.uw, FpOp2P1.uw),
549 fpMulD, fpscr.fz, fpscr.rMode);
550 double dest = binaryOp(fpscr, dbl(FpDestP0.uw, FpDestP1.uw),
551 -mid, fpAddD, fpscr.fz, fpscr.rMode);
552 Fpscr = fpscr;
553 FpDestP0.uw = dblLow(dest);
554 FpDestP1.uw = dblHi(dest);
555 '''
556 vmlsDIop = InstObjParams("vmlsd", "VmlsD", "FpRegRegRegOp",
557 { "code": vmlsDCode,
558 "predicate_test": predicateTest }, [])
559 header_output += FpRegRegRegOpDeclare.subst(vmlsDIop);
560 decoder_output += FpRegRegRegOpConstructor.subst(vmlsDIop);
561 exec_output += PredOpExecute.subst(vmlsDIop);
562
563 vnmlaSCode = '''
564 FPSCR fpscr = Fpscr;
565 float mid = binaryOp(fpscr, FpOp1, FpOp2,
566 fpMulS, fpscr.fz, fpscr.rMode);
567 FpDest = binaryOp(fpscr, -FpDest, -mid, fpAddS, fpscr.fz, fpscr.rMode);
568 Fpscr = fpscr;
569 '''
570 vnmlaSIop = InstObjParams("vnmlas", "VnmlaS", "FpRegRegRegOp",
571 { "code": vnmlaSCode,
572 "predicate_test": predicateTest }, [])
573 header_output += FpRegRegRegOpDeclare.subst(vnmlaSIop);
574 decoder_output += FpRegRegRegOpConstructor.subst(vnmlaSIop);
575 exec_output += PredOpExecute.subst(vnmlaSIop);
576
577 vnmlaDCode = '''
578 FPSCR fpscr = Fpscr;
579 double mid = binaryOp(fpscr, dbl(FpOp1P0.uw, FpOp1P1.uw),
580 dbl(FpOp2P0.uw, FpOp2P1.uw),
581 fpMulD, fpscr.fz, fpscr.rMode);
582 double dest = binaryOp(fpscr, -dbl(FpDestP0.uw, FpDestP1.uw),
583 -mid, fpAddD, fpscr.fz, fpscr.rMode);
584 Fpscr = fpscr;
585 FpDestP0.uw = dblLow(dest);
586 FpDestP1.uw = dblHi(dest);
587 '''
588 vnmlaDIop = InstObjParams("vnmlad", "VnmlaD", "FpRegRegRegOp",
589 { "code": vnmlaDCode,
590 "predicate_test": predicateTest }, [])
591 header_output += FpRegRegRegOpDeclare.subst(vnmlaDIop);
592 decoder_output += FpRegRegRegOpConstructor.subst(vnmlaDIop);
593 exec_output += PredOpExecute.subst(vnmlaDIop);
594
595 vnmlsSCode = '''
596 FPSCR fpscr = Fpscr;
597 float mid = binaryOp(fpscr, FpOp1, FpOp2,
598 fpMulS, fpscr.fz, fpscr.rMode);
599 FpDest = binaryOp(fpscr, -FpDest, mid, fpAddS, fpscr.fz, fpscr.rMode);
600 Fpscr = fpscr;
601 '''
602 vnmlsSIop = InstObjParams("vnmlss", "VnmlsS", "FpRegRegRegOp",
603 { "code": vnmlsSCode,
604 "predicate_test": predicateTest }, [])
605 header_output += FpRegRegRegOpDeclare.subst(vnmlsSIop);
606 decoder_output += FpRegRegRegOpConstructor.subst(vnmlsSIop);
607 exec_output += PredOpExecute.subst(vnmlsSIop);
608
609 vnmlsDCode = '''
610 FPSCR fpscr = Fpscr;
611 double mid = binaryOp(fpscr, dbl(FpOp1P0.uw, FpOp1P1.uw),
612 dbl(FpOp2P0.uw, FpOp2P1.uw),
613 fpMulD, fpscr.fz, fpscr.rMode);
614 double dest = binaryOp(fpscr, -dbl(FpDestP0.uw, FpDestP1.uw),
615 mid, fpAddD, fpscr.fz, fpscr.rMode);
616 Fpscr = fpscr;
617 FpDestP0.uw = dblLow(dest);
618 FpDestP1.uw = dblHi(dest);
619 '''
620 vnmlsDIop = InstObjParams("vnmlsd", "VnmlsD", "FpRegRegRegOp",
621 { "code": vnmlsDCode,
622 "predicate_test": predicateTest }, [])
623 header_output += FpRegRegRegOpDeclare.subst(vnmlsDIop);
624 decoder_output += FpRegRegRegOpConstructor.subst(vnmlsDIop);
625 exec_output += PredOpExecute.subst(vnmlsDIop);
626
627 vnmulSCode = '''
628 FPSCR fpscr = Fpscr;
629 FpDest = -binaryOp(fpscr, FpOp1, FpOp2, fpMulS, fpscr.fz, fpscr.rMode);
630 Fpscr = fpscr;
631 '''
632 vnmulSIop = InstObjParams("vnmuls", "VnmulS", "FpRegRegRegOp",
633 { "code": vnmulSCode,
634 "predicate_test": predicateTest }, [])
635 header_output += FpRegRegRegOpDeclare.subst(vnmulSIop);
636 decoder_output += FpRegRegRegOpConstructor.subst(vnmulSIop);
637 exec_output += PredOpExecute.subst(vnmulSIop);
638
639 vnmulDCode = '''
640 FPSCR fpscr = Fpscr;
641 double dest = -binaryOp(fpscr, dbl(FpOp1P0.uw, FpOp1P1.uw),
642 dbl(FpOp2P0.uw, FpOp2P1.uw),
643 fpMulD, fpscr.fz, fpscr.rMode);
644 Fpscr = fpscr;
645 FpDestP0.uw = dblLow(dest);
646 FpDestP1.uw = dblHi(dest);
647 '''
648 vnmulDIop = InstObjParams("vnmuld", "VnmulD", "FpRegRegRegOp",
649 { "code": vnmulDCode,
650 "predicate_test": predicateTest }, [])
651 header_output += FpRegRegRegOpDeclare.subst(vnmulDIop);

--- 8 unchanged lines hidden (view full) ---

660 exec_output = ""
661
662 vcvtUIntFpSCode = '''
663 FPSCR fpscr = Fpscr;
664 VfpSavedState state = prepFpState(fpscr.rMode);
665 __asm__ __volatile__("" : "=m" (FpOp1.uw) : "m" (FpOp1.uw));
666 FpDest = FpOp1.uw;
667 __asm__ __volatile__("" :: "m" (FpDest));
668 finishVfp(fpscr, state);
669 Fpscr = fpscr;
670 '''
671 vcvtUIntFpSIop = InstObjParams("vcvt", "VcvtUIntFpS", "FpRegRegOp",
672 { "code": vcvtUIntFpSCode,
673 "predicate_test": predicateTest }, [])
674 header_output += FpRegRegOpDeclare.subst(vcvtUIntFpSIop);
675 decoder_output += FpRegRegOpConstructor.subst(vcvtUIntFpSIop);
676 exec_output += PredOpExecute.subst(vcvtUIntFpSIop);
677
678 vcvtUIntFpDCode = '''
679 FPSCR fpscr = Fpscr;
680 VfpSavedState state = prepFpState(fpscr.rMode);
681 __asm__ __volatile__("" : "=m" (FpOp1P0.uw) : "m" (FpOp1P0.uw));
682 double cDest = (uint64_t)FpOp1P0.uw;
683 __asm__ __volatile__("" :: "m" (cDest));
684 finishVfp(fpscr, state);
685 Fpscr = fpscr;
686 FpDestP0.uw = dblLow(cDest);
687 FpDestP1.uw = dblHi(cDest);
688 '''
689 vcvtUIntFpDIop = InstObjParams("vcvt", "VcvtUIntFpD", "FpRegRegOp",
690 { "code": vcvtUIntFpDCode,
691 "predicate_test": predicateTest }, [])
692 header_output += FpRegRegOpDeclare.subst(vcvtUIntFpDIop);
693 decoder_output += FpRegRegOpConstructor.subst(vcvtUIntFpDIop);
694 exec_output += PredOpExecute.subst(vcvtUIntFpDIop);
695
696 vcvtSIntFpSCode = '''
697 FPSCR fpscr = Fpscr;
698 VfpSavedState state = prepFpState(fpscr.rMode);
699 __asm__ __volatile__("" : "=m" (FpOp1.sw) : "m" (FpOp1.sw));
700 FpDest = FpOp1.sw;
701 __asm__ __volatile__("" :: "m" (FpDest));
702 finishVfp(fpscr, state);
703 Fpscr = fpscr;
704 '''
705 vcvtSIntFpSIop = InstObjParams("vcvt", "VcvtSIntFpS", "FpRegRegOp",
706 { "code": vcvtSIntFpSCode,
707 "predicate_test": predicateTest }, [])
708 header_output += FpRegRegOpDeclare.subst(vcvtSIntFpSIop);
709 decoder_output += FpRegRegOpConstructor.subst(vcvtSIntFpSIop);
710 exec_output += PredOpExecute.subst(vcvtSIntFpSIop);
711
712 vcvtSIntFpDCode = '''
713 FPSCR fpscr = Fpscr;
714 VfpSavedState state = prepFpState(fpscr.rMode);
715 __asm__ __volatile__("" : "=m" (FpOp1P0.sw) : "m" (FpOp1P0.sw));
716 double cDest = FpOp1P0.sw;
717 __asm__ __volatile__("" :: "m" (cDest));
718 finishVfp(fpscr, state);
719 Fpscr = fpscr;
720 FpDestP0.uw = dblLow(cDest);
721 FpDestP1.uw = dblHi(cDest);
722 '''
723 vcvtSIntFpDIop = InstObjParams("vcvt", "VcvtSIntFpD", "FpRegRegOp",
724 { "code": vcvtSIntFpDCode,
725 "predicate_test": predicateTest }, [])
726 header_output += FpRegRegOpDeclare.subst(vcvtSIntFpDIop);
727 decoder_output += FpRegRegOpConstructor.subst(vcvtSIntFpDIop);
728 exec_output += PredOpExecute.subst(vcvtSIntFpDIop);
729
730 vcvtFpUIntSRCode = '''
731 FPSCR fpscr = Fpscr;
732 VfpSavedState state = prepFpState(fpscr.rMode);
733 vfpFlushToZero(fpscr, FpOp1);
734 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
735 FpDest.uw = vfpFpSToFixed(FpOp1, false, false, 0, false);
736 __asm__ __volatile__("" :: "m" (FpDest.uw));
737 finishVfp(fpscr, state);
738 Fpscr = fpscr;
739 '''
740 vcvtFpUIntSRIop = InstObjParams("vcvt", "VcvtFpUIntSR", "FpRegRegOp",
741 { "code": vcvtFpUIntSRCode,
742 "predicate_test": predicateTest }, [])
743 header_output += FpRegRegOpDeclare.subst(vcvtFpUIntSRIop);
744 decoder_output += FpRegRegOpConstructor.subst(vcvtFpUIntSRIop);
745 exec_output += PredOpExecute.subst(vcvtFpUIntSRIop);
746
747 vcvtFpUIntDRCode = '''
748 FPSCR fpscr = Fpscr;
749 double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw);
750 vfpFlushToZero(fpscr, cOp1);
751 VfpSavedState state = prepFpState(fpscr.rMode);
752 __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1));
753 uint64_t result = vfpFpDToFixed(cOp1, false, false, 0, false);
754 __asm__ __volatile__("" :: "m" (result));
755 finishVfp(fpscr, state);
756 Fpscr = fpscr;
757 FpDestP0.uw = result;
758 '''
759 vcvtFpUIntDRIop = InstObjParams("vcvtr", "VcvtFpUIntDR", "FpRegRegOp",
760 { "code": vcvtFpUIntDRCode,
761 "predicate_test": predicateTest }, [])
762 header_output += FpRegRegOpDeclare.subst(vcvtFpUIntDRIop);
763 decoder_output += FpRegRegOpConstructor.subst(vcvtFpUIntDRIop);
764 exec_output += PredOpExecute.subst(vcvtFpUIntDRIop);
765
766 vcvtFpSIntSRCode = '''
767 FPSCR fpscr = Fpscr;
768 VfpSavedState state = prepFpState(fpscr.rMode);
769 vfpFlushToZero(fpscr, FpOp1);
770 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
771 FpDest.sw = vfpFpSToFixed(FpOp1, true, false, 0, false);
772 __asm__ __volatile__("" :: "m" (FpDest.sw));
773 finishVfp(fpscr, state);
774 Fpscr = fpscr;
775 '''
776 vcvtFpSIntSRIop = InstObjParams("vcvtr", "VcvtFpSIntSR", "FpRegRegOp",
777 { "code": vcvtFpSIntSRCode,
778 "predicate_test": predicateTest }, [])
779 header_output += FpRegRegOpDeclare.subst(vcvtFpSIntSRIop);
780 decoder_output += FpRegRegOpConstructor.subst(vcvtFpSIntSRIop);
781 exec_output += PredOpExecute.subst(vcvtFpSIntSRIop);
782
783 vcvtFpSIntDRCode = '''
784 FPSCR fpscr = Fpscr;
785 double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw);
786 vfpFlushToZero(fpscr, cOp1);
787 VfpSavedState state = prepFpState(fpscr.rMode);
788 __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1));
789 int64_t result = vfpFpDToFixed(cOp1, true, false, 0, false);
790 __asm__ __volatile__("" :: "m" (result));
791 finishVfp(fpscr, state);
792 Fpscr = fpscr;
793 FpDestP0.uw = result;
794 '''
795 vcvtFpSIntDRIop = InstObjParams("vcvtr", "VcvtFpSIntDR", "FpRegRegOp",
796 { "code": vcvtFpSIntDRCode,
797 "predicate_test": predicateTest }, [])
798 header_output += FpRegRegOpDeclare.subst(vcvtFpSIntDRIop);
799 decoder_output += FpRegRegOpConstructor.subst(vcvtFpSIntDRIop);
800 exec_output += PredOpExecute.subst(vcvtFpSIntDRIop);
801
802 vcvtFpUIntSCode = '''
803 FPSCR fpscr = Fpscr;
804 vfpFlushToZero(fpscr, FpOp1);
805 VfpSavedState state = prepFpState(fpscr.rMode);
806 fesetround(FeRoundZero);
807 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
808 FpDest.uw = vfpFpSToFixed(FpOp1, false, false, 0);
809 __asm__ __volatile__("" :: "m" (FpDest.uw));
810 finishVfp(fpscr, state);
811 Fpscr = fpscr;
812 '''
813 vcvtFpUIntSIop = InstObjParams("vcvt", "VcvtFpUIntS", "FpRegRegOp",
814 { "code": vcvtFpUIntSCode,
815 "predicate_test": predicateTest }, [])
816 header_output += FpRegRegOpDeclare.subst(vcvtFpUIntSIop);
817 decoder_output += FpRegRegOpConstructor.subst(vcvtFpUIntSIop);
818 exec_output += PredOpExecute.subst(vcvtFpUIntSIop);
819
820 vcvtFpUIntDCode = '''
821 FPSCR fpscr = Fpscr;
822 double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw);
823 vfpFlushToZero(fpscr, cOp1);
824 VfpSavedState state = prepFpState(fpscr.rMode);
825 fesetround(FeRoundZero);
826 __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1));
827 uint64_t result = vfpFpDToFixed(cOp1, false, false, 0);
828 __asm__ __volatile__("" :: "m" (result));
829 finishVfp(fpscr, state);
830 Fpscr = fpscr;
831 FpDestP0.uw = result;
832 '''
833 vcvtFpUIntDIop = InstObjParams("vcvt", "VcvtFpUIntD", "FpRegRegOp",
834 { "code": vcvtFpUIntDCode,
835 "predicate_test": predicateTest }, [])
836 header_output += FpRegRegOpDeclare.subst(vcvtFpUIntDIop);
837 decoder_output += FpRegRegOpConstructor.subst(vcvtFpUIntDIop);
838 exec_output += PredOpExecute.subst(vcvtFpUIntDIop);
839
840 vcvtFpSIntSCode = '''
841 FPSCR fpscr = Fpscr;
842 vfpFlushToZero(fpscr, FpOp1);
843 VfpSavedState state = prepFpState(fpscr.rMode);
844 fesetround(FeRoundZero);
845 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
846 FpDest.sw = vfpFpSToFixed(FpOp1, true, false, 0);
847 __asm__ __volatile__("" :: "m" (FpDest.sw));
848 finishVfp(fpscr, state);
849 Fpscr = fpscr;
850 '''
851 vcvtFpSIntSIop = InstObjParams("vcvt", "VcvtFpSIntS", "FpRegRegOp",
852 { "code": vcvtFpSIntSCode,
853 "predicate_test": predicateTest }, [])
854 header_output += FpRegRegOpDeclare.subst(vcvtFpSIntSIop);
855 decoder_output += FpRegRegOpConstructor.subst(vcvtFpSIntSIop);
856 exec_output += PredOpExecute.subst(vcvtFpSIntSIop);
857
858 vcvtFpSIntDCode = '''
859 FPSCR fpscr = Fpscr;
860 double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw);
861 vfpFlushToZero(fpscr, cOp1);
862 VfpSavedState state = prepFpState(fpscr.rMode);
863 fesetround(FeRoundZero);
864 __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1));
865 int64_t result = vfpFpDToFixed(cOp1, true, false, 0);
866 __asm__ __volatile__("" :: "m" (result));
867 finishVfp(fpscr, state);
868 Fpscr = fpscr;
869 FpDestP0.uw = result;
870 '''
871 vcvtFpSIntDIop = InstObjParams("vcvt", "VcvtFpSIntD", "FpRegRegOp",
872 { "code": vcvtFpSIntDCode,
873 "predicate_test": predicateTest }, [])
874 header_output += FpRegRegOpDeclare.subst(vcvtFpSIntDIop);
875 decoder_output += FpRegRegOpConstructor.subst(vcvtFpSIntDIop);
876 exec_output += PredOpExecute.subst(vcvtFpSIntDIop);
877
878 vcvtFpSFpDCode = '''
879 FPSCR fpscr = Fpscr;
880 vfpFlushToZero(fpscr, FpOp1);
881 VfpSavedState state = prepFpState(fpscr.rMode);
882 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
883 double cDest = fixFpSFpDDest(Fpscr, FpOp1);
884 __asm__ __volatile__("" :: "m" (cDest));
885 finishVfp(fpscr, state);
886 Fpscr = fpscr;
887 FpDestP0.uw = dblLow(cDest);
888 FpDestP1.uw = dblHi(cDest);
889 '''
890 vcvtFpSFpDIop = InstObjParams("vcvt", "VcvtFpSFpD", "FpRegRegOp",
891 { "code": vcvtFpSFpDCode,
892 "predicate_test": predicateTest }, [])
893 header_output += FpRegRegOpDeclare.subst(vcvtFpSFpDIop);
894 decoder_output += FpRegRegOpConstructor.subst(vcvtFpSFpDIop);
895 exec_output += PredOpExecute.subst(vcvtFpSFpDIop);
896
897 vcvtFpDFpSCode = '''
898 FPSCR fpscr = Fpscr;
899 double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw);
900 vfpFlushToZero(fpscr, cOp1);
901 VfpSavedState state = prepFpState(fpscr.rMode);
902 __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1));
903 FpDest = fixFpDFpSDest(Fpscr, cOp1);
904 __asm__ __volatile__("" :: "m" (FpDest));
905 finishVfp(fpscr, state);
906 Fpscr = fpscr;
907 '''
908 vcvtFpDFpSIop = InstObjParams("vcvt", "VcvtFpDFpS", "FpRegRegOp",
909 { "code": vcvtFpDFpSCode,
910 "predicate_test": predicateTest }, [])
911 header_output += FpRegRegOpDeclare.subst(vcvtFpDFpSIop);
912 decoder_output += FpRegRegOpConstructor.subst(vcvtFpDFpSIop);
913 exec_output += PredOpExecute.subst(vcvtFpDFpSIop);
914
915 vcvtFpHTFpSCode = '''
916 FPSCR fpscr = Fpscr;
917 vfpFlushToZero(fpscr, FpOp1);
918 VfpSavedState state = prepFpState(fpscr.rMode);
919 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
920 FpDest = vcvtFpHFpS(fpscr, FpOp1, true);
921 __asm__ __volatile__("" :: "m" (FpDest));
922 finishVfp(fpscr, state);
923 Fpscr = fpscr;
924 '''
925 vcvtFpHTFpSIop = InstObjParams("vcvtt", "VcvtFpHTFpS", "FpRegRegOp",
926 { "code": vcvtFpHTFpSCode,
927 "predicate_test": predicateTest }, [])
928 header_output += FpRegRegOpDeclare.subst(vcvtFpHTFpSIop);
929 decoder_output += FpRegRegOpConstructor.subst(vcvtFpHTFpSIop);
930 exec_output += PredOpExecute.subst(vcvtFpHTFpSIop);
931
932 vcvtFpHBFpSCode = '''
933 FPSCR fpscr = Fpscr;
934 VfpSavedState state = prepFpState(fpscr.rMode);
935 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
936 FpDest = vcvtFpHFpS(fpscr, FpOp1, false);
937 __asm__ __volatile__("" :: "m" (FpDest));
938 finishVfp(fpscr, state);
939 Fpscr = fpscr;
940 '''
941 vcvtFpHBFpSIop = InstObjParams("vcvtb", "VcvtFpHBFpS", "FpRegRegOp",
942 { "code": vcvtFpHBFpSCode,
943 "predicate_test": predicateTest }, [])
944 header_output += FpRegRegOpDeclare.subst(vcvtFpHBFpSIop);
945 decoder_output += FpRegRegOpConstructor.subst(vcvtFpHBFpSIop);
946 exec_output += PredOpExecute.subst(vcvtFpHBFpSIop);
947
948 vcvtFpSFpHTCode = '''
949 FPSCR fpscr = Fpscr;
950 vfpFlushToZero(fpscr, FpOp1);
951 VfpSavedState state = prepFpState(fpscr.rMode);
952 __asm__ __volatile__("" : "=m" (FpOp1), "=m" (FpDest)
953 : "m" (FpOp1), "m" (FpDest));
954 FpDest = vcvtFpSFpH(fpscr, FpOp1, FpDest, true);
955 __asm__ __volatile__("" :: "m" (FpDest));
956 finishVfp(fpscr, state);
957 Fpscr = fpscr;
958 '''
959 vcvtFpSFpHTIop = InstObjParams("vcvtt", "VcvtFpSFpHT", "FpRegRegOp",
960 { "code": vcvtFpHTFpSCode,
961 "predicate_test": predicateTest }, [])
962 header_output += FpRegRegOpDeclare.subst(vcvtFpSFpHTIop);
963 decoder_output += FpRegRegOpConstructor.subst(vcvtFpSFpHTIop);
964 exec_output += PredOpExecute.subst(vcvtFpSFpHTIop);
965
966 vcvtFpSFpHBCode = '''
967 FPSCR fpscr = Fpscr;
968 vfpFlushToZero(fpscr, FpOp1);
969 VfpSavedState state = prepFpState(fpscr.rMode);
970 __asm__ __volatile__("" : "=m" (FpOp1), "=m" (FpDest)
971 : "m" (FpOp1), "m" (FpDest));
972 FpDest = vcvtFpSFpH(fpscr, FpOp1, FpDest, false);
973 __asm__ __volatile__("" :: "m" (FpDest));
974 finishVfp(fpscr, state);
975 Fpscr = fpscr;
976 '''
977 vcvtFpSFpHBIop = InstObjParams("vcvtb", "VcvtFpSFpHB", "FpRegRegOp",
978 { "code": vcvtFpSFpHBCode,
979 "predicate_test": predicateTest }, [])
980 header_output += FpRegRegOpDeclare.subst(vcvtFpSFpHBIop);
981 decoder_output += FpRegRegOpConstructor.subst(vcvtFpSFpHBIop);
982 exec_output += PredOpExecute.subst(vcvtFpSFpHBIop);

--- 213 unchanged lines hidden (view full) ---

1196
1197 vcvtFpSFixedSCode = '''
1198 FPSCR fpscr = Fpscr;
1199 vfpFlushToZero(fpscr, FpOp1);
1200 VfpSavedState state = prepFpState(fpscr.rMode);
1201 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
1202 FpDest.sw = vfpFpSToFixed(FpOp1, true, false, imm);
1203 __asm__ __volatile__("" :: "m" (FpDest.sw));
1204 finishVfp(fpscr, state);
1205 Fpscr = fpscr;
1206 '''
1207 vcvtFpSFixedSIop = InstObjParams("vcvt", "VcvtFpSFixedS", "FpRegRegImmOp",
1208 { "code": vcvtFpSFixedSCode,
1209 "predicate_test": predicateTest }, [])
1210 header_output += FpRegRegImmOpDeclare.subst(vcvtFpSFixedSIop);
1211 decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpSFixedSIop);
1212 exec_output += PredOpExecute.subst(vcvtFpSFixedSIop);
1213
1214 vcvtFpSFixedDCode = '''
1215 FPSCR fpscr = Fpscr;
1216 double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw);
1217 vfpFlushToZero(fpscr, cOp1);
1218 VfpSavedState state = prepFpState(fpscr.rMode);
1219 __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1));
1220 uint64_t mid = vfpFpDToFixed(cOp1, true, false, imm);
1221 __asm__ __volatile__("" :: "m" (mid));
1222 finishVfp(fpscr, state);
1223 Fpscr = fpscr;
1224 FpDestP0.uw = mid;
1225 FpDestP1.uw = mid >> 32;
1226 '''
1227 vcvtFpSFixedDIop = InstObjParams("vcvt", "VcvtFpSFixedD", "FpRegRegImmOp",
1228 { "code": vcvtFpSFixedDCode,
1229 "predicate_test": predicateTest }, [])
1230 header_output += FpRegRegImmOpDeclare.subst(vcvtFpSFixedDIop);
1231 decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpSFixedDIop);
1232 exec_output += PredOpExecute.subst(vcvtFpSFixedDIop);
1233
1234 vcvtFpUFixedSCode = '''
1235 FPSCR fpscr = Fpscr;
1236 vfpFlushToZero(fpscr, FpOp1);
1237 VfpSavedState state = prepFpState(fpscr.rMode);
1238 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
1239 FpDest.uw = vfpFpSToFixed(FpOp1, false, false, imm);
1240 __asm__ __volatile__("" :: "m" (FpDest.uw));
1241 finishVfp(fpscr, state);
1242 Fpscr = fpscr;
1243 '''
1244 vcvtFpUFixedSIop = InstObjParams("vcvt", "VcvtFpUFixedS", "FpRegRegImmOp",
1245 { "code": vcvtFpUFixedSCode,
1246 "predicate_test": predicateTest }, [])
1247 header_output += FpRegRegImmOpDeclare.subst(vcvtFpUFixedSIop);
1248 decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpUFixedSIop);
1249 exec_output += PredOpExecute.subst(vcvtFpUFixedSIop);
1250
1251 vcvtFpUFixedDCode = '''
1252 FPSCR fpscr = Fpscr;
1253 double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw);
1254 vfpFlushToZero(fpscr, cOp1);
1255 VfpSavedState state = prepFpState(fpscr.rMode);
1256 __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1));
1257 uint64_t mid = vfpFpDToFixed(cOp1, false, false, imm);
1258 __asm__ __volatile__("" :: "m" (mid));
1259 finishVfp(fpscr, state);
1260 Fpscr = fpscr;
1261 FpDestP0.uw = mid;
1262 FpDestP1.uw = mid >> 32;
1263 '''
1264 vcvtFpUFixedDIop = InstObjParams("vcvt", "VcvtFpUFixedD", "FpRegRegImmOp",
1265 { "code": vcvtFpUFixedDCode,
1266 "predicate_test": predicateTest }, [])
1267 header_output += FpRegRegImmOpDeclare.subst(vcvtFpUFixedDIop);
1268 decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpUFixedDIop);
1269 exec_output += PredOpExecute.subst(vcvtFpUFixedDIop);
1270
1271 vcvtSFixedFpSCode = '''
1272 FPSCR fpscr = Fpscr;
1273 VfpSavedState state = prepFpState(fpscr.rMode);
1274 __asm__ __volatile__("" : "=m" (FpOp1.sw) : "m" (FpOp1.sw));
1275 FpDest = vfpSFixedToFpS(Fpscr, FpOp1.sw, false, imm);
1276 __asm__ __volatile__("" :: "m" (FpDest));
1277 finishVfp(fpscr, state);
1278 Fpscr = fpscr;
1279 '''
1280 vcvtSFixedFpSIop = InstObjParams("vcvt", "VcvtSFixedFpS", "FpRegRegImmOp",
1281 { "code": vcvtSFixedFpSCode,
1282 "predicate_test": predicateTest }, [])
1283 header_output += FpRegRegImmOpDeclare.subst(vcvtSFixedFpSIop);
1284 decoder_output += FpRegRegImmOpConstructor.subst(vcvtSFixedFpSIop);
1285 exec_output += PredOpExecute.subst(vcvtSFixedFpSIop);
1286
1287 vcvtSFixedFpDCode = '''
1288 FPSCR fpscr = Fpscr;
1289 uint64_t mid = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
1290 VfpSavedState state = prepFpState(fpscr.rMode);
1291 __asm__ __volatile__("" : "=m" (mid) : "m" (mid));
1292 double cDest = vfpSFixedToFpD(Fpscr, mid, false, imm);
1293 __asm__ __volatile__("" :: "m" (cDest));
1294 finishVfp(fpscr, state);
1295 Fpscr = fpscr;
1296 FpDestP0.uw = dblLow(cDest);
1297 FpDestP1.uw = dblHi(cDest);
1298 '''
1299 vcvtSFixedFpDIop = InstObjParams("vcvt", "VcvtSFixedFpD", "FpRegRegImmOp",
1300 { "code": vcvtSFixedFpDCode,
1301 "predicate_test": predicateTest }, [])
1302 header_output += FpRegRegImmOpDeclare.subst(vcvtSFixedFpDIop);
1303 decoder_output += FpRegRegImmOpConstructor.subst(vcvtSFixedFpDIop);
1304 exec_output += PredOpExecute.subst(vcvtSFixedFpDIop);
1305
1306 vcvtUFixedFpSCode = '''
1307 FPSCR fpscr = Fpscr;
1308 VfpSavedState state = prepFpState(fpscr.rMode);
1309 __asm__ __volatile__("" : "=m" (FpOp1.uw) : "m" (FpOp1.uw));
1310 FpDest = vfpUFixedToFpS(Fpscr, FpOp1.uw, false, imm);
1311 __asm__ __volatile__("" :: "m" (FpDest));
1312 finishVfp(fpscr, state);
1313 Fpscr = fpscr;
1314 '''
1315 vcvtUFixedFpSIop = InstObjParams("vcvt", "VcvtUFixedFpS", "FpRegRegImmOp",
1316 { "code": vcvtUFixedFpSCode,
1317 "predicate_test": predicateTest }, [])
1318 header_output += FpRegRegImmOpDeclare.subst(vcvtUFixedFpSIop);
1319 decoder_output += FpRegRegImmOpConstructor.subst(vcvtUFixedFpSIop);
1320 exec_output += PredOpExecute.subst(vcvtUFixedFpSIop);
1321
1322 vcvtUFixedFpDCode = '''
1323 FPSCR fpscr = Fpscr;
1324 uint64_t mid = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
1325 VfpSavedState state = prepFpState(fpscr.rMode);
1326 __asm__ __volatile__("" : "=m" (mid) : "m" (mid));
1327 double cDest = vfpUFixedToFpD(Fpscr, mid, false, imm);
1328 __asm__ __volatile__("" :: "m" (cDest));
1329 finishVfp(fpscr, state);
1330 Fpscr = fpscr;
1331 FpDestP0.uw = dblLow(cDest);
1332 FpDestP1.uw = dblHi(cDest);
1333 '''
1334 vcvtUFixedFpDIop = InstObjParams("vcvt", "VcvtUFixedFpD", "FpRegRegImmOp",
1335 { "code": vcvtUFixedFpDCode,
1336 "predicate_test": predicateTest }, [])
1337 header_output += FpRegRegImmOpDeclare.subst(vcvtUFixedFpDIop);
1338 decoder_output += FpRegRegImmOpConstructor.subst(vcvtUFixedFpDIop);
1339 exec_output += PredOpExecute.subst(vcvtUFixedFpDIop);
1340
1341 vcvtFpSHFixedSCode = '''
1342 FPSCR fpscr = Fpscr;
1343 vfpFlushToZero(fpscr, FpOp1);
1344 VfpSavedState state = prepFpState(fpscr.rMode);
1345 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
1346 FpDest.sh = vfpFpSToFixed(FpOp1, true, true, imm);
1347 __asm__ __volatile__("" :: "m" (FpDest.sh));
1348 finishVfp(fpscr, state);
1349 Fpscr = fpscr;
1350 '''
1351 vcvtFpSHFixedSIop = InstObjParams("vcvt", "VcvtFpSHFixedS",
1352 "FpRegRegImmOp",
1353 { "code": vcvtFpSHFixedSCode,
1354 "predicate_test": predicateTest }, [])
1355 header_output += FpRegRegImmOpDeclare.subst(vcvtFpSHFixedSIop);
1356 decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpSHFixedSIop);
1357 exec_output += PredOpExecute.subst(vcvtFpSHFixedSIop);
1358
1359 vcvtFpSHFixedDCode = '''
1360 FPSCR fpscr = Fpscr;
1361 double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw);
1362 vfpFlushToZero(fpscr, cOp1);
1363 VfpSavedState state = prepFpState(fpscr.rMode);
1364 __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1));
1365 uint64_t result = vfpFpDToFixed(cOp1, true, true, imm);
1366 __asm__ __volatile__("" :: "m" (result));
1367 finishVfp(fpscr, state);
1368 Fpscr = fpscr;
1369 FpDestP0.uw = result;
1370 FpDestP1.uw = result >> 32;
1371 '''
1372 vcvtFpSHFixedDIop = InstObjParams("vcvt", "VcvtFpSHFixedD",
1373 "FpRegRegImmOp",
1374 { "code": vcvtFpSHFixedDCode,
1375 "predicate_test": predicateTest }, [])
1376 header_output += FpRegRegImmOpDeclare.subst(vcvtFpSHFixedDIop);
1377 decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpSHFixedDIop);
1378 exec_output += PredOpExecute.subst(vcvtFpSHFixedDIop);
1379
1380 vcvtFpUHFixedSCode = '''
1381 FPSCR fpscr = Fpscr;
1382 vfpFlushToZero(fpscr, FpOp1);
1383 VfpSavedState state = prepFpState(fpscr.rMode);
1384 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
1385 FpDest.uh = vfpFpSToFixed(FpOp1, false, true, imm);
1386 __asm__ __volatile__("" :: "m" (FpDest.uh));
1387 finishVfp(fpscr, state);
1388 Fpscr = fpscr;
1389 '''
1390 vcvtFpUHFixedSIop = InstObjParams("vcvt", "VcvtFpUHFixedS",
1391 "FpRegRegImmOp",
1392 { "code": vcvtFpUHFixedSCode,
1393 "predicate_test": predicateTest }, [])
1394 header_output += FpRegRegImmOpDeclare.subst(vcvtFpUHFixedSIop);
1395 decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpUHFixedSIop);
1396 exec_output += PredOpExecute.subst(vcvtFpUHFixedSIop);
1397
1398 vcvtFpUHFixedDCode = '''
1399 FPSCR fpscr = Fpscr;
1400 double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw);
1401 vfpFlushToZero(fpscr, cOp1);
1402 VfpSavedState state = prepFpState(fpscr.rMode);
1403 __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1));
1404 uint64_t mid = vfpFpDToFixed(cOp1, false, true, imm);
1405 __asm__ __volatile__("" :: "m" (mid));
1406 finishVfp(fpscr, state);
1407 Fpscr = fpscr;
1408 FpDestP0.uw = mid;
1409 FpDestP1.uw = mid >> 32;
1410 '''
1411 vcvtFpUHFixedDIop = InstObjParams("vcvt", "VcvtFpUHFixedD",
1412 "FpRegRegImmOp",
1413 { "code": vcvtFpUHFixedDCode,
1414 "predicate_test": predicateTest }, [])
1415 header_output += FpRegRegImmOpDeclare.subst(vcvtFpUHFixedDIop);
1416 decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpUHFixedDIop);
1417 exec_output += PredOpExecute.subst(vcvtFpUHFixedDIop);
1418
1419 vcvtSHFixedFpSCode = '''
1420 FPSCR fpscr = Fpscr;
1421 VfpSavedState state = prepFpState(fpscr.rMode);
1422 __asm__ __volatile__("" : "=m" (FpOp1.sh) : "m" (FpOp1.sh));
1423 FpDest = vfpSFixedToFpS(Fpscr, FpOp1.sh, true, imm);
1424 __asm__ __volatile__("" :: "m" (FpDest));
1425 finishVfp(fpscr, state);
1426 Fpscr = fpscr;
1427 '''
1428 vcvtSHFixedFpSIop = InstObjParams("vcvt", "VcvtSHFixedFpS",
1429 "FpRegRegImmOp",
1430 { "code": vcvtSHFixedFpSCode,
1431 "predicate_test": predicateTest }, [])
1432 header_output += FpRegRegImmOpDeclare.subst(vcvtSHFixedFpSIop);
1433 decoder_output += FpRegRegImmOpConstructor.subst(vcvtSHFixedFpSIop);
1434 exec_output += PredOpExecute.subst(vcvtSHFixedFpSIop);
1435
1436 vcvtSHFixedFpDCode = '''
1437 FPSCR fpscr = Fpscr;
1438 uint64_t mid = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
1439 VfpSavedState state = prepFpState(fpscr.rMode);
1440 __asm__ __volatile__("" : "=m" (mid) : "m" (mid));
1441 double cDest = vfpSFixedToFpD(Fpscr, mid, true, imm);
1442 __asm__ __volatile__("" :: "m" (cDest));
1443 finishVfp(fpscr, state);
1444 Fpscr = fpscr;
1445 FpDestP0.uw = dblLow(cDest);
1446 FpDestP1.uw = dblHi(cDest);
1447 '''
1448 vcvtSHFixedFpDIop = InstObjParams("vcvt", "VcvtSHFixedFpD",
1449 "FpRegRegImmOp",
1450 { "code": vcvtSHFixedFpDCode,
1451 "predicate_test": predicateTest }, [])
1452 header_output += FpRegRegImmOpDeclare.subst(vcvtSHFixedFpDIop);
1453 decoder_output += FpRegRegImmOpConstructor.subst(vcvtSHFixedFpDIop);
1454 exec_output += PredOpExecute.subst(vcvtSHFixedFpDIop);
1455
1456 vcvtUHFixedFpSCode = '''
1457 FPSCR fpscr = Fpscr;
1458 VfpSavedState state = prepFpState(fpscr.rMode);
1459 __asm__ __volatile__("" : "=m" (FpOp1.uh) : "m" (FpOp1.uh));
1460 FpDest = vfpUFixedToFpS(Fpscr, FpOp1.uh, true, imm);
1461 __asm__ __volatile__("" :: "m" (FpDest));
1462 finishVfp(fpscr, state);
1463 Fpscr = fpscr;
1464 '''
1465 vcvtUHFixedFpSIop = InstObjParams("vcvt", "VcvtUHFixedFpS",
1466 "FpRegRegImmOp",
1467 { "code": vcvtUHFixedFpSCode,
1468 "predicate_test": predicateTest }, [])
1469 header_output += FpRegRegImmOpDeclare.subst(vcvtUHFixedFpSIop);
1470 decoder_output += FpRegRegImmOpConstructor.subst(vcvtUHFixedFpSIop);
1471 exec_output += PredOpExecute.subst(vcvtUHFixedFpSIop);
1472
1473 vcvtUHFixedFpDCode = '''
1474 FPSCR fpscr = Fpscr;
1475 uint64_t mid = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
1476 VfpSavedState state = prepFpState(fpscr.rMode);
1477 __asm__ __volatile__("" : "=m" (mid) : "m" (mid));
1478 double cDest = vfpUFixedToFpD(Fpscr, mid, true, imm);
1479 __asm__ __volatile__("" :: "m" (cDest));
1480 finishVfp(fpscr, state);
1481 Fpscr = fpscr;
1482 FpDestP0.uw = dblLow(cDest);
1483 FpDestP1.uw = dblHi(cDest);
1484 '''
1485 vcvtUHFixedFpDIop = InstObjParams("vcvt", "VcvtUHFixedFpD",
1486 "FpRegRegImmOp",
1487 { "code": vcvtUHFixedFpDCode,
1488 "predicate_test": predicateTest }, [])
1489 header_output += FpRegRegImmOpDeclare.subst(vcvtUHFixedFpDIop);
1490 decoder_output += FpRegRegImmOpConstructor.subst(vcvtUHFixedFpDIop);
1491 exec_output += PredOpExecute.subst(vcvtUHFixedFpDIop);
1492}};