1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
--- 646 unchanged lines hidden (view full) ---
655
656let {{
657
658 header_output = ""
659 decoder_output = ""
660 exec_output = ""
661
662 vcvtUIntFpSCode = '''
663 VfpSavedState state = prepVfpFpscr(Fpscr);
664 __asm__ __volatile__("" : "=m" (FpOp1.uw) : "m" (FpOp1.uw));
665 FpDest = FpOp1.uw;
666 __asm__ __volatile__("" :: "m" (FpDest));
667 Fpscr = setVfpFpscr(Fpscr, state);
668 '''
669 vcvtUIntFpSIop = InstObjParams("vcvt", "VcvtUIntFpS", "FpRegRegOp",
670 { "code": vcvtUIntFpSCode,
671 "predicate_test": predicateTest }, [])
672 header_output += FpRegRegOpDeclare.subst(vcvtUIntFpSIop);
673 decoder_output += FpRegRegOpConstructor.subst(vcvtUIntFpSIop);
674 exec_output += PredOpExecute.subst(vcvtUIntFpSIop);
675
676 vcvtUIntFpDCode = '''
677 IntDoubleUnion cDest;
678 VfpSavedState state = prepVfpFpscr(Fpscr);
679 __asm__ __volatile__("" : "=m" (FpOp1P0.uw) : "m" (FpOp1P0.uw));
680 cDest.fp = (uint64_t)FpOp1P0.uw;
681 __asm__ __volatile__("" :: "m" (cDest.fp));
682 Fpscr = setVfpFpscr(Fpscr, state);
683 FpDestP0.uw = cDest.bits;
684 FpDestP1.uw = cDest.bits >> 32;
685 '''
686 vcvtUIntFpDIop = InstObjParams("vcvt", "VcvtUIntFpD", "FpRegRegOp",
687 { "code": vcvtUIntFpDCode,
688 "predicate_test": predicateTest }, [])
689 header_output += FpRegRegOpDeclare.subst(vcvtUIntFpDIop);
690 decoder_output += FpRegRegOpConstructor.subst(vcvtUIntFpDIop);
691 exec_output += PredOpExecute.subst(vcvtUIntFpDIop);
692
693 vcvtSIntFpSCode = '''
694 VfpSavedState state = prepVfpFpscr(Fpscr);
695 __asm__ __volatile__("" : "=m" (FpOp1.sw) : "m" (FpOp1.sw));
696 FpDest = FpOp1.sw;
697 __asm__ __volatile__("" :: "m" (FpDest));
698 Fpscr = setVfpFpscr(Fpscr, state);
699 '''
700 vcvtSIntFpSIop = InstObjParams("vcvt", "VcvtSIntFpS", "FpRegRegOp",
701 { "code": vcvtSIntFpSCode,
702 "predicate_test": predicateTest }, [])
703 header_output += FpRegRegOpDeclare.subst(vcvtSIntFpSIop);
704 decoder_output += FpRegRegOpConstructor.subst(vcvtSIntFpSIop);
705 exec_output += PredOpExecute.subst(vcvtSIntFpSIop);
706
707 vcvtSIntFpDCode = '''
708 IntDoubleUnion cDest;
709 VfpSavedState state = prepVfpFpscr(Fpscr);
710 __asm__ __volatile__("" : "=m" (FpOp1P0.sw) : "m" (FpOp1P0.sw));
711 cDest.fp = FpOp1P0.sw;
712 __asm__ __volatile__("" :: "m" (cDest.fp));
713 Fpscr = setVfpFpscr(Fpscr, state);
714 FpDestP0.uw = cDest.bits;
715 FpDestP1.uw = cDest.bits >> 32;
716 '''
717 vcvtSIntFpDIop = InstObjParams("vcvt", "VcvtSIntFpD", "FpRegRegOp",
718 { "code": vcvtSIntFpDCode,
719 "predicate_test": predicateTest }, [])
720 header_output += FpRegRegOpDeclare.subst(vcvtSIntFpDIop);
721 decoder_output += FpRegRegOpConstructor.subst(vcvtSIntFpDIop);
722 exec_output += PredOpExecute.subst(vcvtSIntFpDIop);
723
724 vcvtFpUIntSRCode = '''
725 vfpFlushToZero(Fpscr, FpOp1);
726 VfpSavedState state = prepVfpFpscr(Fpscr);
727 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
728 FpDest.uw = vfpFpSToFixed(FpOp1, false, false, 0, false);
729 __asm__ __volatile__("" :: "m" (FpDest.uw));
730 Fpscr = setVfpFpscr(Fpscr, state);
731 '''
732 vcvtFpUIntSRIop = InstObjParams("vcvt", "VcvtFpUIntSR", "FpRegRegOp",
733 { "code": vcvtFpUIntSRCode,
734 "predicate_test": predicateTest }, [])
735 header_output += FpRegRegOpDeclare.subst(vcvtFpUIntSRIop);
736 decoder_output += FpRegRegOpConstructor.subst(vcvtFpUIntSRIop);
737 exec_output += PredOpExecute.subst(vcvtFpUIntSRIop);
738
739 vcvtFpUIntDRCode = '''
740 IntDoubleUnion cOp1;
741 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
742 vfpFlushToZero(Fpscr, cOp1.fp);
743 VfpSavedState state = prepVfpFpscr(Fpscr);
744 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp));
745 uint64_t result = vfpFpDToFixed(cOp1.fp, false, false, 0, false);
746 __asm__ __volatile__("" :: "m" (result));
747 Fpscr = setVfpFpscr(Fpscr, state);
748 FpDestP0.uw = result;
749 '''
750 vcvtFpUIntDRIop = InstObjParams("vcvtr", "VcvtFpUIntDR", "FpRegRegOp",
751 { "code": vcvtFpUIntDRCode,
752 "predicate_test": predicateTest }, [])
753 header_output += FpRegRegOpDeclare.subst(vcvtFpUIntDRIop);
754 decoder_output += FpRegRegOpConstructor.subst(vcvtFpUIntDRIop);
755 exec_output += PredOpExecute.subst(vcvtFpUIntDRIop);
756
757 vcvtFpSIntSRCode = '''
758 vfpFlushToZero(Fpscr, FpOp1);
759 VfpSavedState state = prepVfpFpscr(Fpscr);
760 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
761 FpDest.sw = vfpFpSToFixed(FpOp1, true, false, 0, false);
762 __asm__ __volatile__("" :: "m" (FpDest.sw));
763 Fpscr = setVfpFpscr(Fpscr, state);
764 '''
765 vcvtFpSIntSRIop = InstObjParams("vcvtr", "VcvtFpSIntSR", "FpRegRegOp",
766 { "code": vcvtFpSIntSRCode,
767 "predicate_test": predicateTest }, [])
768 header_output += FpRegRegOpDeclare.subst(vcvtFpSIntSRIop);
769 decoder_output += FpRegRegOpConstructor.subst(vcvtFpSIntSRIop);
770 exec_output += PredOpExecute.subst(vcvtFpSIntSRIop);
771
772 vcvtFpSIntDRCode = '''
773 IntDoubleUnion cOp1;
774 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
775 vfpFlushToZero(Fpscr, cOp1.fp);
776 VfpSavedState state = prepVfpFpscr(Fpscr);
777 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp));
778 int64_t result = vfpFpDToFixed(cOp1.fp, true, false, 0, false);
779 __asm__ __volatile__("" :: "m" (result));
780 Fpscr = setVfpFpscr(Fpscr, state);
781 FpDestP0.uw = result;
782 '''
783 vcvtFpSIntDRIop = InstObjParams("vcvtr", "VcvtFpSIntDR", "FpRegRegOp",
784 { "code": vcvtFpSIntDRCode,
785 "predicate_test": predicateTest }, [])
786 header_output += FpRegRegOpDeclare.subst(vcvtFpSIntDRIop);
787 decoder_output += FpRegRegOpConstructor.subst(vcvtFpSIntDRIop);
788 exec_output += PredOpExecute.subst(vcvtFpSIntDRIop);
789
790 vcvtFpUIntSCode = '''
791 vfpFlushToZero(Fpscr, FpOp1);
792 VfpSavedState state = prepVfpFpscr(Fpscr);
793 fesetround(FeRoundZero);
794 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
795 FpDest.uw = vfpFpSToFixed(FpOp1, false, false, 0);
796 __asm__ __volatile__("" :: "m" (FpDest.uw));
797 Fpscr = setVfpFpscr(Fpscr, state);
798 '''
799 vcvtFpUIntSIop = InstObjParams("vcvt", "VcvtFpUIntS", "FpRegRegOp",
800 { "code": vcvtFpUIntSCode,
801 "predicate_test": predicateTest }, [])
802 header_output += FpRegRegOpDeclare.subst(vcvtFpUIntSIop);
803 decoder_output += FpRegRegOpConstructor.subst(vcvtFpUIntSIop);
804 exec_output += PredOpExecute.subst(vcvtFpUIntSIop);
805
806 vcvtFpUIntDCode = '''
807 IntDoubleUnion cOp1;
808 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
809 vfpFlushToZero(Fpscr, cOp1.fp);
810 VfpSavedState state = prepVfpFpscr(Fpscr);
811 fesetround(FeRoundZero);
812 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp));
813 uint64_t result = vfpFpDToFixed(cOp1.fp, false, false, 0);
814 __asm__ __volatile__("" :: "m" (result));
815 Fpscr = setVfpFpscr(Fpscr, state);
816 FpDestP0.uw = result;
817 '''
818 vcvtFpUIntDIop = InstObjParams("vcvt", "VcvtFpUIntD", "FpRegRegOp",
819 { "code": vcvtFpUIntDCode,
820 "predicate_test": predicateTest }, [])
821 header_output += FpRegRegOpDeclare.subst(vcvtFpUIntDIop);
822 decoder_output += FpRegRegOpConstructor.subst(vcvtFpUIntDIop);
823 exec_output += PredOpExecute.subst(vcvtFpUIntDIop);
824
825 vcvtFpSIntSCode = '''
826 vfpFlushToZero(Fpscr, FpOp1);
827 VfpSavedState state = prepVfpFpscr(Fpscr);
828 fesetround(FeRoundZero);
829 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
830 FpDest.sw = vfpFpSToFixed(FpOp1, true, false, 0);
831 __asm__ __volatile__("" :: "m" (FpDest.sw));
832 Fpscr = setVfpFpscr(Fpscr, state);
833 '''
834 vcvtFpSIntSIop = InstObjParams("vcvt", "VcvtFpSIntS", "FpRegRegOp",
835 { "code": vcvtFpSIntSCode,
836 "predicate_test": predicateTest }, [])
837 header_output += FpRegRegOpDeclare.subst(vcvtFpSIntSIop);
838 decoder_output += FpRegRegOpConstructor.subst(vcvtFpSIntSIop);
839 exec_output += PredOpExecute.subst(vcvtFpSIntSIop);
840
841 vcvtFpSIntDCode = '''
842 IntDoubleUnion cOp1;
843 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
844 vfpFlushToZero(Fpscr, cOp1.fp);
845 VfpSavedState state = prepVfpFpscr(Fpscr);
846 fesetround(FeRoundZero);
847 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp));
848 int64_t result = vfpFpDToFixed(cOp1.fp, true, false, 0);
849 __asm__ __volatile__("" :: "m" (result));
850 Fpscr = setVfpFpscr(Fpscr, state);
851 FpDestP0.uw = result;
852 '''
853 vcvtFpSIntDIop = InstObjParams("vcvt", "VcvtFpSIntD", "FpRegRegOp",
854 { "code": vcvtFpSIntDCode,
855 "predicate_test": predicateTest }, [])
856 header_output += FpRegRegOpDeclare.subst(vcvtFpSIntDIop);
857 decoder_output += FpRegRegOpConstructor.subst(vcvtFpSIntDIop);
858 exec_output += PredOpExecute.subst(vcvtFpSIntDIop);
859
860 vcvtFpSFpDCode = '''
861 IntDoubleUnion cDest;
862 vfpFlushToZero(Fpscr, FpOp1);
863 VfpSavedState state = prepVfpFpscr(Fpscr);
864 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
865 cDest.fp = fixFpSFpDDest(Fpscr, FpOp1);
866 __asm__ __volatile__("" :: "m" (cDest.fp));
867 Fpscr = setVfpFpscr(Fpscr, state);
868 FpDestP0.uw = cDest.bits;
869 FpDestP1.uw = cDest.bits >> 32;
870 '''
871 vcvtFpSFpDIop = InstObjParams("vcvt", "VcvtFpSFpD", "FpRegRegOp",
872 { "code": vcvtFpSFpDCode,
873 "predicate_test": predicateTest }, [])
874 header_output += FpRegRegOpDeclare.subst(vcvtFpSFpDIop);
875 decoder_output += FpRegRegOpConstructor.subst(vcvtFpSFpDIop);
876 exec_output += PredOpExecute.subst(vcvtFpSFpDIop);
877
878 vcvtFpDFpSCode = '''
879 IntDoubleUnion cOp1;
880 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
881 vfpFlushToZero(Fpscr, cOp1.fp);
882 VfpSavedState state = prepVfpFpscr(Fpscr);
883 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp));
884 FpDest = fixFpDFpSDest(Fpscr, cOp1.fp);
885 __asm__ __volatile__("" :: "m" (FpDest));
886 Fpscr = setVfpFpscr(Fpscr, state);
887 '''
888 vcvtFpDFpSIop = InstObjParams("vcvt", "VcvtFpDFpS", "FpRegRegOp",
889 { "code": vcvtFpDFpSCode,
890 "predicate_test": predicateTest }, [])
891 header_output += FpRegRegOpDeclare.subst(vcvtFpDFpSIop);
892 decoder_output += FpRegRegOpConstructor.subst(vcvtFpDFpSIop);
893 exec_output += PredOpExecute.subst(vcvtFpDFpSIop);
894
895 vcmpSCode = '''
896 vfpFlushToZero(Fpscr, FpDest, FpOp1);
897 FPSCR fpscr = Fpscr;
898 if (FpDest == FpOp1) {
899 fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0;
900 } else if (FpDest < FpOp1) {
901 fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0;
902 } else if (FpDest > FpOp1) {
903 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0;
904 } else {
905 const uint32_t qnan = 0x7fc00000;
--- 10 unchanged lines hidden (view full) ---
916 vcmpSIop = InstObjParams("vcmps", "VcmpS", "FpRegRegOp",
917 { "code": vcmpSCode,
918 "predicate_test": predicateTest }, [])
919 header_output += FpRegRegOpDeclare.subst(vcmpSIop);
920 decoder_output += FpRegRegOpConstructor.subst(vcmpSIop);
921 exec_output += PredOpExecute.subst(vcmpSIop);
922
923 vcmpDCode = '''
924 IntDoubleUnion cOp1, cDest;
925 cDest.bits = ((uint64_t)FpDestP0.uw | ((uint64_t)FpDestP1.uw << 32));
926 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
927 vfpFlushToZero(Fpscr, cDest.fp, cOp1.fp);
928 FPSCR fpscr = Fpscr;
929 if (cDest.fp == cOp1.fp) {
930 fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0;
931 } else if (cDest.fp < cOp1.fp) {
932 fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0;
933 } else if (cDest.fp > cOp1.fp) {
934 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0;
935 } else {
936 const uint64_t qnan = ULL(0x7ff8000000000000);
937 const bool nan1 = std::isnan(cDest.fp);
938 const bool signal1 = nan1 && ((cDest.bits & qnan) != qnan);
939 const bool nan2 = std::isnan(cOp1.fp);
940 const bool signal2 = nan2 && ((cOp1.bits & qnan) != qnan);
941 if (signal1 || signal2)
942 fpscr.ioc = 1;
943 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1;
944 }
945 Fpscr = fpscr;
946 '''
947 vcmpDIop = InstObjParams("vcmpd", "VcmpD", "FpRegRegOp",
948 { "code": vcmpDCode,
949 "predicate_test": predicateTest }, [])
950 header_output += FpRegRegOpDeclare.subst(vcmpDIop);
951 decoder_output += FpRegRegOpConstructor.subst(vcmpDIop);
952 exec_output += PredOpExecute.subst(vcmpDIop);
953
954 vcmpZeroSCode = '''
955 vfpFlushToZero(Fpscr, FpDest);
956 FPSCR fpscr = Fpscr;
957 // This only handles imm == 0 for now.
958 assert(imm == 0);
959 if (FpDest == imm) {
960 fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0;
961 } else if (FpDest < imm) {
962 fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0;
963 } else if (FpDest > imm) {
964 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0;
--- 10 unchanged lines hidden (view full) ---
975 vcmpZeroSIop = InstObjParams("vcmpZeros", "VcmpZeroS", "FpRegImmOp",
976 { "code": vcmpZeroSCode,
977 "predicate_test": predicateTest }, [])
978 header_output += FpRegImmOpDeclare.subst(vcmpZeroSIop);
979 decoder_output += FpRegImmOpConstructor.subst(vcmpZeroSIop);
980 exec_output += PredOpExecute.subst(vcmpZeroSIop);
981
982 vcmpZeroDCode = '''
983 IntDoubleUnion cDest;
984 // This only handles imm == 0 for now.
985 assert(imm == 0);
986 cDest.bits = ((uint64_t)FpDestP0.uw | ((uint64_t)FpDestP1.uw << 32));
987 vfpFlushToZero(Fpscr, cDest.fp);
988 FPSCR fpscr = Fpscr;
989 if (cDest.fp == imm) {
990 fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0;
991 } else if (cDest.fp < imm) {
992 fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0;
993 } else if (cDest.fp > imm) {
994 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0;
995 } else {
996 const uint64_t qnan = ULL(0x7ff8000000000000);
997 const bool nan = std::isnan(cDest.fp);
998 const bool signal = nan && ((cDest.bits & qnan) != qnan);
999 if (signal)
1000 fpscr.ioc = 1;
1001 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1;
1002 }
1003 Fpscr = fpscr;
1004 '''
1005 vcmpZeroDIop = InstObjParams("vcmpZerod", "VcmpZeroD", "FpRegImmOp",
1006 { "code": vcmpZeroDCode,
1007 "predicate_test": predicateTest }, [])
1008 header_output += FpRegImmOpDeclare.subst(vcmpZeroDIop);
1009 decoder_output += FpRegImmOpConstructor.subst(vcmpZeroDIop);
1010 exec_output += PredOpExecute.subst(vcmpZeroDIop);
1011
1012 vcmpeSCode = '''
1013 vfpFlushToZero(Fpscr, FpDest, FpOp1);
1014 FPSCR fpscr = Fpscr;
1015 if (FpDest == FpOp1) {
1016 fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0;
1017 } else if (FpDest < FpOp1) {
1018 fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0;
1019 } else if (FpDest > FpOp1) {
1020 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0;
1021 } else {
1022 fpscr.ioc = 1;
--- 4 unchanged lines hidden (view full) ---
1027 vcmpeSIop = InstObjParams("vcmpes", "VcmpeS", "FpRegRegOp",
1028 { "code": vcmpeSCode,
1029 "predicate_test": predicateTest }, [])
1030 header_output += FpRegRegOpDeclare.subst(vcmpeSIop);
1031 decoder_output += FpRegRegOpConstructor.subst(vcmpeSIop);
1032 exec_output += PredOpExecute.subst(vcmpeSIop);
1033
1034 vcmpeDCode = '''
1035 IntDoubleUnion cOp1, cDest;
1036 cDest.bits = ((uint64_t)FpDestP0.uw | ((uint64_t)FpDestP1.uw << 32));
1037 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
1038 vfpFlushToZero(Fpscr, cDest.fp, cOp1.fp);
1039 FPSCR fpscr = Fpscr;
1040 if (cDest.fp == cOp1.fp) {
1041 fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0;
1042 } else if (cDest.fp < cOp1.fp) {
1043 fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0;
1044 } else if (cDest.fp > cOp1.fp) {
1045 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0;
1046 } else {
1047 fpscr.ioc = 1;
1048 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1;
1049 }
1050 Fpscr = fpscr;
1051 '''
1052 vcmpeDIop = InstObjParams("vcmped", "VcmpeD", "FpRegRegOp",
1053 { "code": vcmpeDCode,
1054 "predicate_test": predicateTest }, [])
1055 header_output += FpRegRegOpDeclare.subst(vcmpeDIop);
1056 decoder_output += FpRegRegOpConstructor.subst(vcmpeDIop);
1057 exec_output += PredOpExecute.subst(vcmpeDIop);
1058
1059 vcmpeZeroSCode = '''
1060 vfpFlushToZero(Fpscr, FpDest);
1061 FPSCR fpscr = Fpscr;
1062 if (FpDest == imm) {
1063 fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0;
1064 } else if (FpDest < imm) {
1065 fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0;
1066 } else if (FpDest > imm) {
1067 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0;
1068 } else {
1069 fpscr.ioc = 1;
--- 4 unchanged lines hidden (view full) ---
1074 vcmpeZeroSIop = InstObjParams("vcmpeZeros", "VcmpeZeroS", "FpRegImmOp",
1075 { "code": vcmpeZeroSCode,
1076 "predicate_test": predicateTest }, [])
1077 header_output += FpRegImmOpDeclare.subst(vcmpeZeroSIop);
1078 decoder_output += FpRegImmOpConstructor.subst(vcmpeZeroSIop);
1079 exec_output += PredOpExecute.subst(vcmpeZeroSIop);
1080
1081 vcmpeZeroDCode = '''
1082 IntDoubleUnion cDest;
1083 cDest.bits = ((uint64_t)FpDestP0.uw | ((uint64_t)FpDestP1.uw << 32));
1084 vfpFlushToZero(Fpscr, cDest.fp);
1085 FPSCR fpscr = Fpscr;
1086 if (cDest.fp == imm) {
1087 fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0;
1088 } else if (cDest.fp < imm) {
1089 fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0;
1090 } else if (cDest.fp > imm) {
1091 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0;
1092 } else {
1093 fpscr.ioc = 1;
1094 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1;
1095 }
1096 Fpscr = fpscr;
1097 '''
1098 vcmpeZeroDIop = InstObjParams("vcmpeZerod", "VcmpeZeroD", "FpRegImmOp",
--- 6 unchanged lines hidden (view full) ---
1105
1106let {{
1107
1108 header_output = ""
1109 decoder_output = ""
1110 exec_output = ""
1111
1112 vcvtFpSFixedSCode = '''
1113 vfpFlushToZero(Fpscr, FpOp1);
1114 VfpSavedState state = prepVfpFpscr(Fpscr);
1115 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
1116 FpDest.sw = vfpFpSToFixed(FpOp1, true, false, imm);
1117 __asm__ __volatile__("" :: "m" (FpDest.sw));
1118 Fpscr = setVfpFpscr(Fpscr, state);
1119 '''
1120 vcvtFpSFixedSIop = InstObjParams("vcvt", "VcvtFpSFixedS", "FpRegRegImmOp",
1121 { "code": vcvtFpSFixedSCode,
1122 "predicate_test": predicateTest }, [])
1123 header_output += FpRegRegImmOpDeclare.subst(vcvtFpSFixedSIop);
1124 decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpSFixedSIop);
1125 exec_output += PredOpExecute.subst(vcvtFpSFixedSIop);
1126
1127 vcvtFpSFixedDCode = '''
1128 IntDoubleUnion cOp1;
1129 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
1130 vfpFlushToZero(Fpscr, cOp1.fp);
1131 VfpSavedState state = prepVfpFpscr(Fpscr);
1132 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp));
1133 uint64_t mid = vfpFpDToFixed(cOp1.fp, true, false, imm);
1134 __asm__ __volatile__("" :: "m" (mid));
1135 Fpscr = setVfpFpscr(Fpscr, state);
1136 FpDestP0.uw = mid;
1137 FpDestP1.uw = mid >> 32;
1138 '''
1139 vcvtFpSFixedDIop = InstObjParams("vcvt", "VcvtFpSFixedD", "FpRegRegImmOp",
1140 { "code": vcvtFpSFixedDCode,
1141 "predicate_test": predicateTest }, [])
1142 header_output += FpRegRegImmOpDeclare.subst(vcvtFpSFixedDIop);
1143 decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpSFixedDIop);
1144 exec_output += PredOpExecute.subst(vcvtFpSFixedDIop);
1145
1146 vcvtFpUFixedSCode = '''
1147 vfpFlushToZero(Fpscr, FpOp1);
1148 VfpSavedState state = prepVfpFpscr(Fpscr);
1149 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
1150 FpDest.uw = vfpFpSToFixed(FpOp1, false, false, imm);
1151 __asm__ __volatile__("" :: "m" (FpDest.uw));
1152 Fpscr = setVfpFpscr(Fpscr, state);
1153 '''
1154 vcvtFpUFixedSIop = InstObjParams("vcvt", "VcvtFpUFixedS", "FpRegRegImmOp",
1155 { "code": vcvtFpUFixedSCode,
1156 "predicate_test": predicateTest }, [])
1157 header_output += FpRegRegImmOpDeclare.subst(vcvtFpUFixedSIop);
1158 decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpUFixedSIop);
1159 exec_output += PredOpExecute.subst(vcvtFpUFixedSIop);
1160
1161 vcvtFpUFixedDCode = '''
1162 IntDoubleUnion cOp1;
1163 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
1164 vfpFlushToZero(Fpscr, cOp1.fp);
1165 VfpSavedState state = prepVfpFpscr(Fpscr);
1166 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp));
1167 uint64_t mid = vfpFpDToFixed(cOp1.fp, false, false, imm);
1168 __asm__ __volatile__("" :: "m" (mid));
1169 Fpscr = setVfpFpscr(Fpscr, state);
1170 FpDestP0.uw = mid;
1171 FpDestP1.uw = mid >> 32;
1172 '''
1173 vcvtFpUFixedDIop = InstObjParams("vcvt", "VcvtFpUFixedD", "FpRegRegImmOp",
1174 { "code": vcvtFpUFixedDCode,
1175 "predicate_test": predicateTest }, [])
1176 header_output += FpRegRegImmOpDeclare.subst(vcvtFpUFixedDIop);
1177 decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpUFixedDIop);
1178 exec_output += PredOpExecute.subst(vcvtFpUFixedDIop);
1179
1180 vcvtSFixedFpSCode = '''
1181 VfpSavedState state = prepVfpFpscr(Fpscr);
1182 __asm__ __volatile__("" : "=m" (FpOp1.sw) : "m" (FpOp1.sw));
1183 FpDest = vfpSFixedToFpS(Fpscr, FpOp1.sw, false, imm);
1184 __asm__ __volatile__("" :: "m" (FpDest));
1185 Fpscr = setVfpFpscr(Fpscr, state);
1186 '''
1187 vcvtSFixedFpSIop = InstObjParams("vcvt", "VcvtSFixedFpS", "FpRegRegImmOp",
1188 { "code": vcvtSFixedFpSCode,
1189 "predicate_test": predicateTest }, [])
1190 header_output += FpRegRegImmOpDeclare.subst(vcvtSFixedFpSIop);
1191 decoder_output += FpRegRegImmOpConstructor.subst(vcvtSFixedFpSIop);
1192 exec_output += PredOpExecute.subst(vcvtSFixedFpSIop);
1193
1194 vcvtSFixedFpDCode = '''
1195 IntDoubleUnion cDest;
1196 uint64_t mid = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
1197 VfpSavedState state = prepVfpFpscr(Fpscr);
1198 __asm__ __volatile__("" : "=m" (mid) : "m" (mid));
1199 cDest.fp = vfpSFixedToFpD(Fpscr, mid, false, imm);
1200 __asm__ __volatile__("" :: "m" (cDest.fp));
1201 Fpscr = setVfpFpscr(Fpscr, state);
1202 FpDestP0.uw = cDest.bits;
1203 FpDestP1.uw = cDest.bits >> 32;
1204 '''
1205 vcvtSFixedFpDIop = InstObjParams("vcvt", "VcvtSFixedFpD", "FpRegRegImmOp",
1206 { "code": vcvtSFixedFpDCode,
1207 "predicate_test": predicateTest }, [])
1208 header_output += FpRegRegImmOpDeclare.subst(vcvtSFixedFpDIop);
1209 decoder_output += FpRegRegImmOpConstructor.subst(vcvtSFixedFpDIop);
1210 exec_output += PredOpExecute.subst(vcvtSFixedFpDIop);
1211
1212 vcvtUFixedFpSCode = '''
1213 VfpSavedState state = prepVfpFpscr(Fpscr);
1214 __asm__ __volatile__("" : "=m" (FpOp1.uw) : "m" (FpOp1.uw));
1215 FpDest = vfpUFixedToFpS(Fpscr, FpOp1.uw, false, imm);
1216 __asm__ __volatile__("" :: "m" (FpDest));
1217 Fpscr = setVfpFpscr(Fpscr, state);
1218 '''
1219 vcvtUFixedFpSIop = InstObjParams("vcvt", "VcvtUFixedFpS", "FpRegRegImmOp",
1220 { "code": vcvtUFixedFpSCode,
1221 "predicate_test": predicateTest }, [])
1222 header_output += FpRegRegImmOpDeclare.subst(vcvtUFixedFpSIop);
1223 decoder_output += FpRegRegImmOpConstructor.subst(vcvtUFixedFpSIop);
1224 exec_output += PredOpExecute.subst(vcvtUFixedFpSIop);
1225
1226 vcvtUFixedFpDCode = '''
1227 IntDoubleUnion cDest;
1228 uint64_t mid = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
1229 VfpSavedState state = prepVfpFpscr(Fpscr);
1230 __asm__ __volatile__("" : "=m" (mid) : "m" (mid));
1231 cDest.fp = vfpUFixedToFpD(Fpscr, mid, false, imm);
1232 __asm__ __volatile__("" :: "m" (cDest.fp));
1233 Fpscr = setVfpFpscr(Fpscr, state);
1234 FpDestP0.uw = cDest.bits;
1235 FpDestP1.uw = cDest.bits >> 32;
1236 '''
1237 vcvtUFixedFpDIop = InstObjParams("vcvt", "VcvtUFixedFpD", "FpRegRegImmOp",
1238 { "code": vcvtUFixedFpDCode,
1239 "predicate_test": predicateTest }, [])
1240 header_output += FpRegRegImmOpDeclare.subst(vcvtUFixedFpDIop);
1241 decoder_output += FpRegRegImmOpConstructor.subst(vcvtUFixedFpDIop);
1242 exec_output += PredOpExecute.subst(vcvtUFixedFpDIop);
1243
1244 vcvtFpSHFixedSCode = '''
1245 vfpFlushToZero(Fpscr, FpOp1);
1246 VfpSavedState state = prepVfpFpscr(Fpscr);
1247 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
1248 FpDest.sh = vfpFpSToFixed(FpOp1, true, true, imm);
1249 __asm__ __volatile__("" :: "m" (FpDest.sh));
1250 Fpscr = setVfpFpscr(Fpscr, state);
1251 '''
1252 vcvtFpSHFixedSIop = InstObjParams("vcvt", "VcvtFpSHFixedS",
1253 "FpRegRegImmOp",
1254 { "code": vcvtFpSHFixedSCode,
1255 "predicate_test": predicateTest }, [])
1256 header_output += FpRegRegImmOpDeclare.subst(vcvtFpSHFixedSIop);
1257 decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpSHFixedSIop);
1258 exec_output += PredOpExecute.subst(vcvtFpSHFixedSIop);
1259
1260 vcvtFpSHFixedDCode = '''
1261 IntDoubleUnion cOp1;
1262 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
1263 vfpFlushToZero(Fpscr, cOp1.fp);
1264 VfpSavedState state = prepVfpFpscr(Fpscr);
1265 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp));
1266 uint64_t result = vfpFpDToFixed(cOp1.fp, true, true, imm);
1267 __asm__ __volatile__("" :: "m" (result));
1268 Fpscr = setVfpFpscr(Fpscr, state);
1269 FpDestP0.uw = result;
1270 FpDestP1.uw = result >> 32;
1271 '''
1272 vcvtFpSHFixedDIop = InstObjParams("vcvt", "VcvtFpSHFixedD",
1273 "FpRegRegImmOp",
1274 { "code": vcvtFpSHFixedDCode,
1275 "predicate_test": predicateTest }, [])
1276 header_output += FpRegRegImmOpDeclare.subst(vcvtFpSHFixedDIop);
1277 decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpSHFixedDIop);
1278 exec_output += PredOpExecute.subst(vcvtFpSHFixedDIop);
1279
1280 vcvtFpUHFixedSCode = '''
1281 vfpFlushToZero(Fpscr, FpOp1);
1282 VfpSavedState state = prepVfpFpscr(Fpscr);
1283 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
1284 FpDest.uh = vfpFpSToFixed(FpOp1, false, true, imm);
1285 __asm__ __volatile__("" :: "m" (FpDest.uh));
1286 Fpscr = setVfpFpscr(Fpscr, state);
1287 '''
1288 vcvtFpUHFixedSIop = InstObjParams("vcvt", "VcvtFpUHFixedS",
1289 "FpRegRegImmOp",
1290 { "code": vcvtFpUHFixedSCode,
1291 "predicate_test": predicateTest }, [])
1292 header_output += FpRegRegImmOpDeclare.subst(vcvtFpUHFixedSIop);
1293 decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpUHFixedSIop);
1294 exec_output += PredOpExecute.subst(vcvtFpUHFixedSIop);
1295
1296 vcvtFpUHFixedDCode = '''
1297 IntDoubleUnion cOp1;
1298 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
1299 vfpFlushToZero(Fpscr, cOp1.fp);
1300 VfpSavedState state = prepVfpFpscr(Fpscr);
1301 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp));
1302 uint64_t mid = vfpFpDToFixed(cOp1.fp, false, true, imm);
1303 __asm__ __volatile__("" :: "m" (mid));
1304 Fpscr = setVfpFpscr(Fpscr, state);
1305 FpDestP0.uw = mid;
1306 FpDestP1.uw = mid >> 32;
1307 '''
1308 vcvtFpUHFixedDIop = InstObjParams("vcvt", "VcvtFpUHFixedD",
1309 "FpRegRegImmOp",
1310 { "code": vcvtFpUHFixedDCode,
1311 "predicate_test": predicateTest }, [])
1312 header_output += FpRegRegImmOpDeclare.subst(vcvtFpUHFixedDIop);
1313 decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpUHFixedDIop);
1314 exec_output += PredOpExecute.subst(vcvtFpUHFixedDIop);
1315
1316 vcvtSHFixedFpSCode = '''
1317 VfpSavedState state = prepVfpFpscr(Fpscr);
1318 __asm__ __volatile__("" : "=m" (FpOp1.sh) : "m" (FpOp1.sh));
1319 FpDest = vfpSFixedToFpS(Fpscr, FpOp1.sh, true, imm);
1320 __asm__ __volatile__("" :: "m" (FpDest));
1321 Fpscr = setVfpFpscr(Fpscr, state);
1322 '''
1323 vcvtSHFixedFpSIop = InstObjParams("vcvt", "VcvtSHFixedFpS",
1324 "FpRegRegImmOp",
1325 { "code": vcvtSHFixedFpSCode,
1326 "predicate_test": predicateTest }, [])
1327 header_output += FpRegRegImmOpDeclare.subst(vcvtSHFixedFpSIop);
1328 decoder_output += FpRegRegImmOpConstructor.subst(vcvtSHFixedFpSIop);
1329 exec_output += PredOpExecute.subst(vcvtSHFixedFpSIop);
1330
1331 vcvtSHFixedFpDCode = '''
1332 IntDoubleUnion cDest;
1333 uint64_t mid = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
1334 VfpSavedState state = prepVfpFpscr(Fpscr);
1335 __asm__ __volatile__("" : "=m" (mid) : "m" (mid));
1336 cDest.fp = vfpSFixedToFpD(Fpscr, mid, true, imm);
1337 __asm__ __volatile__("" :: "m" (cDest.fp));
1338 Fpscr = setVfpFpscr(Fpscr, state);
1339 FpDestP0.uw = cDest.bits;
1340 FpDestP1.uw = cDest.bits >> 32;
1341 '''
1342 vcvtSHFixedFpDIop = InstObjParams("vcvt", "VcvtSHFixedFpD",
1343 "FpRegRegImmOp",
1344 { "code": vcvtSHFixedFpDCode,
1345 "predicate_test": predicateTest }, [])
1346 header_output += FpRegRegImmOpDeclare.subst(vcvtSHFixedFpDIop);
1347 decoder_output += FpRegRegImmOpConstructor.subst(vcvtSHFixedFpDIop);
1348 exec_output += PredOpExecute.subst(vcvtSHFixedFpDIop);
1349
1350 vcvtUHFixedFpSCode = '''
1351 VfpSavedState state = prepVfpFpscr(Fpscr);
1352 __asm__ __volatile__("" : "=m" (FpOp1.uh) : "m" (FpOp1.uh));
1353 FpDest = vfpUFixedToFpS(Fpscr, FpOp1.uh, true, imm);
1354 __asm__ __volatile__("" :: "m" (FpDest));
1355 Fpscr = setVfpFpscr(Fpscr, state);
1356 '''
1357 vcvtUHFixedFpSIop = InstObjParams("vcvt", "VcvtUHFixedFpS",
1358 "FpRegRegImmOp",
1359 { "code": vcvtUHFixedFpSCode,
1360 "predicate_test": predicateTest }, [])
1361 header_output += FpRegRegImmOpDeclare.subst(vcvtUHFixedFpSIop);
1362 decoder_output += FpRegRegImmOpConstructor.subst(vcvtUHFixedFpSIop);
1363 exec_output += PredOpExecute.subst(vcvtUHFixedFpSIop);
1364
1365 vcvtUHFixedFpDCode = '''
1366 IntDoubleUnion cDest;
1367 uint64_t mid = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
1368 VfpSavedState state = prepVfpFpscr(Fpscr);
1369 __asm__ __volatile__("" : "=m" (mid) : "m" (mid));
1370 cDest.fp = vfpUFixedToFpD(Fpscr, mid, true, imm);
1371 __asm__ __volatile__("" :: "m" (cDest.fp));
1372 Fpscr = setVfpFpscr(Fpscr, state);
1373 FpDestP0.uw = cDest.bits;
1374 FpDestP1.uw = cDest.bits >> 32;
1375 '''
1376 vcvtUHFixedFpDIop = InstObjParams("vcvt", "VcvtUHFixedFpD",
1377 "FpRegRegImmOp",
1378 { "code": vcvtUHFixedFpDCode,
1379 "predicate_test": predicateTest }, [])
1380 header_output += FpRegRegImmOpDeclare.subst(vcvtUHFixedFpDIop);
1381 decoder_output += FpRegRegImmOpConstructor.subst(vcvtUHFixedFpDIop);
1382 exec_output += PredOpExecute.subst(vcvtUHFixedFpDIop);
1383}};
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
--- 646 unchanged lines hidden (view full) ---
655
656let {{
657
658 header_output = ""
659 decoder_output = ""
660 exec_output = ""
661
662 vcvtUIntFpSCode = '''
663 VfpSavedState state = prepVfpFpscr(Fpscr);
664 __asm__ __volatile__("" : "=m" (FpOp1.uw) : "m" (FpOp1.uw));
665 FpDest = FpOp1.uw;
666 __asm__ __volatile__("" :: "m" (FpDest));
667 Fpscr = setVfpFpscr(Fpscr, state);
668 '''
669 vcvtUIntFpSIop = InstObjParams("vcvt", "VcvtUIntFpS", "FpRegRegOp",
670 { "code": vcvtUIntFpSCode,
671 "predicate_test": predicateTest }, [])
672 header_output += FpRegRegOpDeclare.subst(vcvtUIntFpSIop);
673 decoder_output += FpRegRegOpConstructor.subst(vcvtUIntFpSIop);
674 exec_output += PredOpExecute.subst(vcvtUIntFpSIop);
675
676 vcvtUIntFpDCode = '''
677 IntDoubleUnion cDest;
678 VfpSavedState state = prepVfpFpscr(Fpscr);
679 __asm__ __volatile__("" : "=m" (FpOp1P0.uw) : "m" (FpOp1P0.uw));
680 cDest.fp = (uint64_t)FpOp1P0.uw;
681 __asm__ __volatile__("" :: "m" (cDest.fp));
682 Fpscr = setVfpFpscr(Fpscr, state);
683 FpDestP0.uw = cDest.bits;
684 FpDestP1.uw = cDest.bits >> 32;
685 '''
686 vcvtUIntFpDIop = InstObjParams("vcvt", "VcvtUIntFpD", "FpRegRegOp",
687 { "code": vcvtUIntFpDCode,
688 "predicate_test": predicateTest }, [])
689 header_output += FpRegRegOpDeclare.subst(vcvtUIntFpDIop);
690 decoder_output += FpRegRegOpConstructor.subst(vcvtUIntFpDIop);
691 exec_output += PredOpExecute.subst(vcvtUIntFpDIop);
692
693 vcvtSIntFpSCode = '''
694 VfpSavedState state = prepVfpFpscr(Fpscr);
695 __asm__ __volatile__("" : "=m" (FpOp1.sw) : "m" (FpOp1.sw));
696 FpDest = FpOp1.sw;
697 __asm__ __volatile__("" :: "m" (FpDest));
698 Fpscr = setVfpFpscr(Fpscr, state);
699 '''
700 vcvtSIntFpSIop = InstObjParams("vcvt", "VcvtSIntFpS", "FpRegRegOp",
701 { "code": vcvtSIntFpSCode,
702 "predicate_test": predicateTest }, [])
703 header_output += FpRegRegOpDeclare.subst(vcvtSIntFpSIop);
704 decoder_output += FpRegRegOpConstructor.subst(vcvtSIntFpSIop);
705 exec_output += PredOpExecute.subst(vcvtSIntFpSIop);
706
707 vcvtSIntFpDCode = '''
708 IntDoubleUnion cDest;
709 VfpSavedState state = prepVfpFpscr(Fpscr);
710 __asm__ __volatile__("" : "=m" (FpOp1P0.sw) : "m" (FpOp1P0.sw));
711 cDest.fp = FpOp1P0.sw;
712 __asm__ __volatile__("" :: "m" (cDest.fp));
713 Fpscr = setVfpFpscr(Fpscr, state);
714 FpDestP0.uw = cDest.bits;
715 FpDestP1.uw = cDest.bits >> 32;
716 '''
717 vcvtSIntFpDIop = InstObjParams("vcvt", "VcvtSIntFpD", "FpRegRegOp",
718 { "code": vcvtSIntFpDCode,
719 "predicate_test": predicateTest }, [])
720 header_output += FpRegRegOpDeclare.subst(vcvtSIntFpDIop);
721 decoder_output += FpRegRegOpConstructor.subst(vcvtSIntFpDIop);
722 exec_output += PredOpExecute.subst(vcvtSIntFpDIop);
723
724 vcvtFpUIntSRCode = '''
725 vfpFlushToZero(Fpscr, FpOp1);
726 VfpSavedState state = prepVfpFpscr(Fpscr);
727 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
728 FpDest.uw = vfpFpSToFixed(FpOp1, false, false, 0, false);
729 __asm__ __volatile__("" :: "m" (FpDest.uw));
730 Fpscr = setVfpFpscr(Fpscr, state);
731 '''
732 vcvtFpUIntSRIop = InstObjParams("vcvt", "VcvtFpUIntSR", "FpRegRegOp",
733 { "code": vcvtFpUIntSRCode,
734 "predicate_test": predicateTest }, [])
735 header_output += FpRegRegOpDeclare.subst(vcvtFpUIntSRIop);
736 decoder_output += FpRegRegOpConstructor.subst(vcvtFpUIntSRIop);
737 exec_output += PredOpExecute.subst(vcvtFpUIntSRIop);
738
739 vcvtFpUIntDRCode = '''
740 IntDoubleUnion cOp1;
741 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
742 vfpFlushToZero(Fpscr, cOp1.fp);
743 VfpSavedState state = prepVfpFpscr(Fpscr);
744 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp));
745 uint64_t result = vfpFpDToFixed(cOp1.fp, false, false, 0, false);
746 __asm__ __volatile__("" :: "m" (result));
747 Fpscr = setVfpFpscr(Fpscr, state);
748 FpDestP0.uw = result;
749 '''
750 vcvtFpUIntDRIop = InstObjParams("vcvtr", "VcvtFpUIntDR", "FpRegRegOp",
751 { "code": vcvtFpUIntDRCode,
752 "predicate_test": predicateTest }, [])
753 header_output += FpRegRegOpDeclare.subst(vcvtFpUIntDRIop);
754 decoder_output += FpRegRegOpConstructor.subst(vcvtFpUIntDRIop);
755 exec_output += PredOpExecute.subst(vcvtFpUIntDRIop);
756
757 vcvtFpSIntSRCode = '''
758 vfpFlushToZero(Fpscr, FpOp1);
759 VfpSavedState state = prepVfpFpscr(Fpscr);
760 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
761 FpDest.sw = vfpFpSToFixed(FpOp1, true, false, 0, false);
762 __asm__ __volatile__("" :: "m" (FpDest.sw));
763 Fpscr = setVfpFpscr(Fpscr, state);
764 '''
765 vcvtFpSIntSRIop = InstObjParams("vcvtr", "VcvtFpSIntSR", "FpRegRegOp",
766 { "code": vcvtFpSIntSRCode,
767 "predicate_test": predicateTest }, [])
768 header_output += FpRegRegOpDeclare.subst(vcvtFpSIntSRIop);
769 decoder_output += FpRegRegOpConstructor.subst(vcvtFpSIntSRIop);
770 exec_output += PredOpExecute.subst(vcvtFpSIntSRIop);
771
772 vcvtFpSIntDRCode = '''
773 IntDoubleUnion cOp1;
774 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
775 vfpFlushToZero(Fpscr, cOp1.fp);
776 VfpSavedState state = prepVfpFpscr(Fpscr);
777 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp));
778 int64_t result = vfpFpDToFixed(cOp1.fp, true, false, 0, false);
779 __asm__ __volatile__("" :: "m" (result));
780 Fpscr = setVfpFpscr(Fpscr, state);
781 FpDestP0.uw = result;
782 '''
783 vcvtFpSIntDRIop = InstObjParams("vcvtr", "VcvtFpSIntDR", "FpRegRegOp",
784 { "code": vcvtFpSIntDRCode,
785 "predicate_test": predicateTest }, [])
786 header_output += FpRegRegOpDeclare.subst(vcvtFpSIntDRIop);
787 decoder_output += FpRegRegOpConstructor.subst(vcvtFpSIntDRIop);
788 exec_output += PredOpExecute.subst(vcvtFpSIntDRIop);
789
790 vcvtFpUIntSCode = '''
791 vfpFlushToZero(Fpscr, FpOp1);
792 VfpSavedState state = prepVfpFpscr(Fpscr);
793 fesetround(FeRoundZero);
794 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
795 FpDest.uw = vfpFpSToFixed(FpOp1, false, false, 0);
796 __asm__ __volatile__("" :: "m" (FpDest.uw));
797 Fpscr = setVfpFpscr(Fpscr, state);
798 '''
799 vcvtFpUIntSIop = InstObjParams("vcvt", "VcvtFpUIntS", "FpRegRegOp",
800 { "code": vcvtFpUIntSCode,
801 "predicate_test": predicateTest }, [])
802 header_output += FpRegRegOpDeclare.subst(vcvtFpUIntSIop);
803 decoder_output += FpRegRegOpConstructor.subst(vcvtFpUIntSIop);
804 exec_output += PredOpExecute.subst(vcvtFpUIntSIop);
805
806 vcvtFpUIntDCode = '''
807 IntDoubleUnion cOp1;
808 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
809 vfpFlushToZero(Fpscr, cOp1.fp);
810 VfpSavedState state = prepVfpFpscr(Fpscr);
811 fesetround(FeRoundZero);
812 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp));
813 uint64_t result = vfpFpDToFixed(cOp1.fp, false, false, 0);
814 __asm__ __volatile__("" :: "m" (result));
815 Fpscr = setVfpFpscr(Fpscr, state);
816 FpDestP0.uw = result;
817 '''
818 vcvtFpUIntDIop = InstObjParams("vcvt", "VcvtFpUIntD", "FpRegRegOp",
819 { "code": vcvtFpUIntDCode,
820 "predicate_test": predicateTest }, [])
821 header_output += FpRegRegOpDeclare.subst(vcvtFpUIntDIop);
822 decoder_output += FpRegRegOpConstructor.subst(vcvtFpUIntDIop);
823 exec_output += PredOpExecute.subst(vcvtFpUIntDIop);
824
825 vcvtFpSIntSCode = '''
826 vfpFlushToZero(Fpscr, FpOp1);
827 VfpSavedState state = prepVfpFpscr(Fpscr);
828 fesetround(FeRoundZero);
829 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
830 FpDest.sw = vfpFpSToFixed(FpOp1, true, false, 0);
831 __asm__ __volatile__("" :: "m" (FpDest.sw));
832 Fpscr = setVfpFpscr(Fpscr, state);
833 '''
834 vcvtFpSIntSIop = InstObjParams("vcvt", "VcvtFpSIntS", "FpRegRegOp",
835 { "code": vcvtFpSIntSCode,
836 "predicate_test": predicateTest }, [])
837 header_output += FpRegRegOpDeclare.subst(vcvtFpSIntSIop);
838 decoder_output += FpRegRegOpConstructor.subst(vcvtFpSIntSIop);
839 exec_output += PredOpExecute.subst(vcvtFpSIntSIop);
840
841 vcvtFpSIntDCode = '''
842 IntDoubleUnion cOp1;
843 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
844 vfpFlushToZero(Fpscr, cOp1.fp);
845 VfpSavedState state = prepVfpFpscr(Fpscr);
846 fesetround(FeRoundZero);
847 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp));
848 int64_t result = vfpFpDToFixed(cOp1.fp, true, false, 0);
849 __asm__ __volatile__("" :: "m" (result));
850 Fpscr = setVfpFpscr(Fpscr, state);
851 FpDestP0.uw = result;
852 '''
853 vcvtFpSIntDIop = InstObjParams("vcvt", "VcvtFpSIntD", "FpRegRegOp",
854 { "code": vcvtFpSIntDCode,
855 "predicate_test": predicateTest }, [])
856 header_output += FpRegRegOpDeclare.subst(vcvtFpSIntDIop);
857 decoder_output += FpRegRegOpConstructor.subst(vcvtFpSIntDIop);
858 exec_output += PredOpExecute.subst(vcvtFpSIntDIop);
859
860 vcvtFpSFpDCode = '''
861 IntDoubleUnion cDest;
862 vfpFlushToZero(Fpscr, FpOp1);
863 VfpSavedState state = prepVfpFpscr(Fpscr);
864 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
865 cDest.fp = fixFpSFpDDest(Fpscr, FpOp1);
866 __asm__ __volatile__("" :: "m" (cDest.fp));
867 Fpscr = setVfpFpscr(Fpscr, state);
868 FpDestP0.uw = cDest.bits;
869 FpDestP1.uw = cDest.bits >> 32;
870 '''
871 vcvtFpSFpDIop = InstObjParams("vcvt", "VcvtFpSFpD", "FpRegRegOp",
872 { "code": vcvtFpSFpDCode,
873 "predicate_test": predicateTest }, [])
874 header_output += FpRegRegOpDeclare.subst(vcvtFpSFpDIop);
875 decoder_output += FpRegRegOpConstructor.subst(vcvtFpSFpDIop);
876 exec_output += PredOpExecute.subst(vcvtFpSFpDIop);
877
878 vcvtFpDFpSCode = '''
879 IntDoubleUnion cOp1;
880 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
881 vfpFlushToZero(Fpscr, cOp1.fp);
882 VfpSavedState state = prepVfpFpscr(Fpscr);
883 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp));
884 FpDest = fixFpDFpSDest(Fpscr, cOp1.fp);
885 __asm__ __volatile__("" :: "m" (FpDest));
886 Fpscr = setVfpFpscr(Fpscr, state);
887 '''
888 vcvtFpDFpSIop = InstObjParams("vcvt", "VcvtFpDFpS", "FpRegRegOp",
889 { "code": vcvtFpDFpSCode,
890 "predicate_test": predicateTest }, [])
891 header_output += FpRegRegOpDeclare.subst(vcvtFpDFpSIop);
892 decoder_output += FpRegRegOpConstructor.subst(vcvtFpDFpSIop);
893 exec_output += PredOpExecute.subst(vcvtFpDFpSIop);
894
895 vcmpSCode = '''
896 vfpFlushToZero(Fpscr, FpDest, FpOp1);
897 FPSCR fpscr = Fpscr;
898 if (FpDest == FpOp1) {
899 fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0;
900 } else if (FpDest < FpOp1) {
901 fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0;
902 } else if (FpDest > FpOp1) {
903 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0;
904 } else {
905 const uint32_t qnan = 0x7fc00000;
--- 10 unchanged lines hidden (view full) ---
916 vcmpSIop = InstObjParams("vcmps", "VcmpS", "FpRegRegOp",
917 { "code": vcmpSCode,
918 "predicate_test": predicateTest }, [])
919 header_output += FpRegRegOpDeclare.subst(vcmpSIop);
920 decoder_output += FpRegRegOpConstructor.subst(vcmpSIop);
921 exec_output += PredOpExecute.subst(vcmpSIop);
922
923 vcmpDCode = '''
924 IntDoubleUnion cOp1, cDest;
925 cDest.bits = ((uint64_t)FpDestP0.uw | ((uint64_t)FpDestP1.uw << 32));
926 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
927 vfpFlushToZero(Fpscr, cDest.fp, cOp1.fp);
928 FPSCR fpscr = Fpscr;
929 if (cDest.fp == cOp1.fp) {
930 fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0;
931 } else if (cDest.fp < cOp1.fp) {
932 fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0;
933 } else if (cDest.fp > cOp1.fp) {
934 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0;
935 } else {
936 const uint64_t qnan = ULL(0x7ff8000000000000);
937 const bool nan1 = std::isnan(cDest.fp);
938 const bool signal1 = nan1 && ((cDest.bits & qnan) != qnan);
939 const bool nan2 = std::isnan(cOp1.fp);
940 const bool signal2 = nan2 && ((cOp1.bits & qnan) != qnan);
941 if (signal1 || signal2)
942 fpscr.ioc = 1;
943 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1;
944 }
945 Fpscr = fpscr;
946 '''
947 vcmpDIop = InstObjParams("vcmpd", "VcmpD", "FpRegRegOp",
948 { "code": vcmpDCode,
949 "predicate_test": predicateTest }, [])
950 header_output += FpRegRegOpDeclare.subst(vcmpDIop);
951 decoder_output += FpRegRegOpConstructor.subst(vcmpDIop);
952 exec_output += PredOpExecute.subst(vcmpDIop);
953
954 vcmpZeroSCode = '''
955 vfpFlushToZero(Fpscr, FpDest);
956 FPSCR fpscr = Fpscr;
957 // This only handles imm == 0 for now.
958 assert(imm == 0);
959 if (FpDest == imm) {
960 fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0;
961 } else if (FpDest < imm) {
962 fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0;
963 } else if (FpDest > imm) {
964 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0;
--- 10 unchanged lines hidden (view full) ---
975 vcmpZeroSIop = InstObjParams("vcmpZeros", "VcmpZeroS", "FpRegImmOp",
976 { "code": vcmpZeroSCode,
977 "predicate_test": predicateTest }, [])
978 header_output += FpRegImmOpDeclare.subst(vcmpZeroSIop);
979 decoder_output += FpRegImmOpConstructor.subst(vcmpZeroSIop);
980 exec_output += PredOpExecute.subst(vcmpZeroSIop);
981
982 vcmpZeroDCode = '''
983 IntDoubleUnion cDest;
984 // This only handles imm == 0 for now.
985 assert(imm == 0);
986 cDest.bits = ((uint64_t)FpDestP0.uw | ((uint64_t)FpDestP1.uw << 32));
987 vfpFlushToZero(Fpscr, cDest.fp);
988 FPSCR fpscr = Fpscr;
989 if (cDest.fp == imm) {
990 fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0;
991 } else if (cDest.fp < imm) {
992 fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0;
993 } else if (cDest.fp > imm) {
994 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0;
995 } else {
996 const uint64_t qnan = ULL(0x7ff8000000000000);
997 const bool nan = std::isnan(cDest.fp);
998 const bool signal = nan && ((cDest.bits & qnan) != qnan);
999 if (signal)
1000 fpscr.ioc = 1;
1001 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1;
1002 }
1003 Fpscr = fpscr;
1004 '''
1005 vcmpZeroDIop = InstObjParams("vcmpZerod", "VcmpZeroD", "FpRegImmOp",
1006 { "code": vcmpZeroDCode,
1007 "predicate_test": predicateTest }, [])
1008 header_output += FpRegImmOpDeclare.subst(vcmpZeroDIop);
1009 decoder_output += FpRegImmOpConstructor.subst(vcmpZeroDIop);
1010 exec_output += PredOpExecute.subst(vcmpZeroDIop);
1011
1012 vcmpeSCode = '''
1013 vfpFlushToZero(Fpscr, FpDest, FpOp1);
1014 FPSCR fpscr = Fpscr;
1015 if (FpDest == FpOp1) {
1016 fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0;
1017 } else if (FpDest < FpOp1) {
1018 fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0;
1019 } else if (FpDest > FpOp1) {
1020 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0;
1021 } else {
1022 fpscr.ioc = 1;
--- 4 unchanged lines hidden (view full) ---
1027 vcmpeSIop = InstObjParams("vcmpes", "VcmpeS", "FpRegRegOp",
1028 { "code": vcmpeSCode,
1029 "predicate_test": predicateTest }, [])
1030 header_output += FpRegRegOpDeclare.subst(vcmpeSIop);
1031 decoder_output += FpRegRegOpConstructor.subst(vcmpeSIop);
1032 exec_output += PredOpExecute.subst(vcmpeSIop);
1033
1034 vcmpeDCode = '''
1035 IntDoubleUnion cOp1, cDest;
1036 cDest.bits = ((uint64_t)FpDestP0.uw | ((uint64_t)FpDestP1.uw << 32));
1037 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
1038 vfpFlushToZero(Fpscr, cDest.fp, cOp1.fp);
1039 FPSCR fpscr = Fpscr;
1040 if (cDest.fp == cOp1.fp) {
1041 fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0;
1042 } else if (cDest.fp < cOp1.fp) {
1043 fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0;
1044 } else if (cDest.fp > cOp1.fp) {
1045 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0;
1046 } else {
1047 fpscr.ioc = 1;
1048 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1;
1049 }
1050 Fpscr = fpscr;
1051 '''
1052 vcmpeDIop = InstObjParams("vcmped", "VcmpeD", "FpRegRegOp",
1053 { "code": vcmpeDCode,
1054 "predicate_test": predicateTest }, [])
1055 header_output += FpRegRegOpDeclare.subst(vcmpeDIop);
1056 decoder_output += FpRegRegOpConstructor.subst(vcmpeDIop);
1057 exec_output += PredOpExecute.subst(vcmpeDIop);
1058
1059 vcmpeZeroSCode = '''
1060 vfpFlushToZero(Fpscr, FpDest);
1061 FPSCR fpscr = Fpscr;
1062 if (FpDest == imm) {
1063 fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0;
1064 } else if (FpDest < imm) {
1065 fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0;
1066 } else if (FpDest > imm) {
1067 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0;
1068 } else {
1069 fpscr.ioc = 1;
--- 4 unchanged lines hidden (view full) ---
1074 vcmpeZeroSIop = InstObjParams("vcmpeZeros", "VcmpeZeroS", "FpRegImmOp",
1075 { "code": vcmpeZeroSCode,
1076 "predicate_test": predicateTest }, [])
1077 header_output += FpRegImmOpDeclare.subst(vcmpeZeroSIop);
1078 decoder_output += FpRegImmOpConstructor.subst(vcmpeZeroSIop);
1079 exec_output += PredOpExecute.subst(vcmpeZeroSIop);
1080
1081 vcmpeZeroDCode = '''
1082 IntDoubleUnion cDest;
1083 cDest.bits = ((uint64_t)FpDestP0.uw | ((uint64_t)FpDestP1.uw << 32));
1084 vfpFlushToZero(Fpscr, cDest.fp);
1085 FPSCR fpscr = Fpscr;
1086 if (cDest.fp == imm) {
1087 fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0;
1088 } else if (cDest.fp < imm) {
1089 fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0;
1090 } else if (cDest.fp > imm) {
1091 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0;
1092 } else {
1093 fpscr.ioc = 1;
1094 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1;
1095 }
1096 Fpscr = fpscr;
1097 '''
1098 vcmpeZeroDIop = InstObjParams("vcmpeZerod", "VcmpeZeroD", "FpRegImmOp",
--- 6 unchanged lines hidden (view full) ---
1105
1106let {{
1107
1108 header_output = ""
1109 decoder_output = ""
1110 exec_output = ""
1111
1112 vcvtFpSFixedSCode = '''
1113 vfpFlushToZero(Fpscr, FpOp1);
1114 VfpSavedState state = prepVfpFpscr(Fpscr);
1115 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
1116 FpDest.sw = vfpFpSToFixed(FpOp1, true, false, imm);
1117 __asm__ __volatile__("" :: "m" (FpDest.sw));
1118 Fpscr = setVfpFpscr(Fpscr, state);
1119 '''
1120 vcvtFpSFixedSIop = InstObjParams("vcvt", "VcvtFpSFixedS", "FpRegRegImmOp",
1121 { "code": vcvtFpSFixedSCode,
1122 "predicate_test": predicateTest }, [])
1123 header_output += FpRegRegImmOpDeclare.subst(vcvtFpSFixedSIop);
1124 decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpSFixedSIop);
1125 exec_output += PredOpExecute.subst(vcvtFpSFixedSIop);
1126
1127 vcvtFpSFixedDCode = '''
1128 IntDoubleUnion cOp1;
1129 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
1130 vfpFlushToZero(Fpscr, cOp1.fp);
1131 VfpSavedState state = prepVfpFpscr(Fpscr);
1132 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp));
1133 uint64_t mid = vfpFpDToFixed(cOp1.fp, true, false, imm);
1134 __asm__ __volatile__("" :: "m" (mid));
1135 Fpscr = setVfpFpscr(Fpscr, state);
1136 FpDestP0.uw = mid;
1137 FpDestP1.uw = mid >> 32;
1138 '''
1139 vcvtFpSFixedDIop = InstObjParams("vcvt", "VcvtFpSFixedD", "FpRegRegImmOp",
1140 { "code": vcvtFpSFixedDCode,
1141 "predicate_test": predicateTest }, [])
1142 header_output += FpRegRegImmOpDeclare.subst(vcvtFpSFixedDIop);
1143 decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpSFixedDIop);
1144 exec_output += PredOpExecute.subst(vcvtFpSFixedDIop);
1145
1146 vcvtFpUFixedSCode = '''
1147 vfpFlushToZero(Fpscr, FpOp1);
1148 VfpSavedState state = prepVfpFpscr(Fpscr);
1149 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
1150 FpDest.uw = vfpFpSToFixed(FpOp1, false, false, imm);
1151 __asm__ __volatile__("" :: "m" (FpDest.uw));
1152 Fpscr = setVfpFpscr(Fpscr, state);
1153 '''
1154 vcvtFpUFixedSIop = InstObjParams("vcvt", "VcvtFpUFixedS", "FpRegRegImmOp",
1155 { "code": vcvtFpUFixedSCode,
1156 "predicate_test": predicateTest }, [])
1157 header_output += FpRegRegImmOpDeclare.subst(vcvtFpUFixedSIop);
1158 decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpUFixedSIop);
1159 exec_output += PredOpExecute.subst(vcvtFpUFixedSIop);
1160
1161 vcvtFpUFixedDCode = '''
1162 IntDoubleUnion cOp1;
1163 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
1164 vfpFlushToZero(Fpscr, cOp1.fp);
1165 VfpSavedState state = prepVfpFpscr(Fpscr);
1166 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp));
1167 uint64_t mid = vfpFpDToFixed(cOp1.fp, false, false, imm);
1168 __asm__ __volatile__("" :: "m" (mid));
1169 Fpscr = setVfpFpscr(Fpscr, state);
1170 FpDestP0.uw = mid;
1171 FpDestP1.uw = mid >> 32;
1172 '''
1173 vcvtFpUFixedDIop = InstObjParams("vcvt", "VcvtFpUFixedD", "FpRegRegImmOp",
1174 { "code": vcvtFpUFixedDCode,
1175 "predicate_test": predicateTest }, [])
1176 header_output += FpRegRegImmOpDeclare.subst(vcvtFpUFixedDIop);
1177 decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpUFixedDIop);
1178 exec_output += PredOpExecute.subst(vcvtFpUFixedDIop);
1179
1180 vcvtSFixedFpSCode = '''
1181 VfpSavedState state = prepVfpFpscr(Fpscr);
1182 __asm__ __volatile__("" : "=m" (FpOp1.sw) : "m" (FpOp1.sw));
1183 FpDest = vfpSFixedToFpS(Fpscr, FpOp1.sw, false, imm);
1184 __asm__ __volatile__("" :: "m" (FpDest));
1185 Fpscr = setVfpFpscr(Fpscr, state);
1186 '''
1187 vcvtSFixedFpSIop = InstObjParams("vcvt", "VcvtSFixedFpS", "FpRegRegImmOp",
1188 { "code": vcvtSFixedFpSCode,
1189 "predicate_test": predicateTest }, [])
1190 header_output += FpRegRegImmOpDeclare.subst(vcvtSFixedFpSIop);
1191 decoder_output += FpRegRegImmOpConstructor.subst(vcvtSFixedFpSIop);
1192 exec_output += PredOpExecute.subst(vcvtSFixedFpSIop);
1193
1194 vcvtSFixedFpDCode = '''
1195 IntDoubleUnion cDest;
1196 uint64_t mid = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
1197 VfpSavedState state = prepVfpFpscr(Fpscr);
1198 __asm__ __volatile__("" : "=m" (mid) : "m" (mid));
1199 cDest.fp = vfpSFixedToFpD(Fpscr, mid, false, imm);
1200 __asm__ __volatile__("" :: "m" (cDest.fp));
1201 Fpscr = setVfpFpscr(Fpscr, state);
1202 FpDestP0.uw = cDest.bits;
1203 FpDestP1.uw = cDest.bits >> 32;
1204 '''
1205 vcvtSFixedFpDIop = InstObjParams("vcvt", "VcvtSFixedFpD", "FpRegRegImmOp",
1206 { "code": vcvtSFixedFpDCode,
1207 "predicate_test": predicateTest }, [])
1208 header_output += FpRegRegImmOpDeclare.subst(vcvtSFixedFpDIop);
1209 decoder_output += FpRegRegImmOpConstructor.subst(vcvtSFixedFpDIop);
1210 exec_output += PredOpExecute.subst(vcvtSFixedFpDIop);
1211
1212 vcvtUFixedFpSCode = '''
1213 VfpSavedState state = prepVfpFpscr(Fpscr);
1214 __asm__ __volatile__("" : "=m" (FpOp1.uw) : "m" (FpOp1.uw));
1215 FpDest = vfpUFixedToFpS(Fpscr, FpOp1.uw, false, imm);
1216 __asm__ __volatile__("" :: "m" (FpDest));
1217 Fpscr = setVfpFpscr(Fpscr, state);
1218 '''
1219 vcvtUFixedFpSIop = InstObjParams("vcvt", "VcvtUFixedFpS", "FpRegRegImmOp",
1220 { "code": vcvtUFixedFpSCode,
1221 "predicate_test": predicateTest }, [])
1222 header_output += FpRegRegImmOpDeclare.subst(vcvtUFixedFpSIop);
1223 decoder_output += FpRegRegImmOpConstructor.subst(vcvtUFixedFpSIop);
1224 exec_output += PredOpExecute.subst(vcvtUFixedFpSIop);
1225
1226 vcvtUFixedFpDCode = '''
1227 IntDoubleUnion cDest;
1228 uint64_t mid = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
1229 VfpSavedState state = prepVfpFpscr(Fpscr);
1230 __asm__ __volatile__("" : "=m" (mid) : "m" (mid));
1231 cDest.fp = vfpUFixedToFpD(Fpscr, mid, false, imm);
1232 __asm__ __volatile__("" :: "m" (cDest.fp));
1233 Fpscr = setVfpFpscr(Fpscr, state);
1234 FpDestP0.uw = cDest.bits;
1235 FpDestP1.uw = cDest.bits >> 32;
1236 '''
1237 vcvtUFixedFpDIop = InstObjParams("vcvt", "VcvtUFixedFpD", "FpRegRegImmOp",
1238 { "code": vcvtUFixedFpDCode,
1239 "predicate_test": predicateTest }, [])
1240 header_output += FpRegRegImmOpDeclare.subst(vcvtUFixedFpDIop);
1241 decoder_output += FpRegRegImmOpConstructor.subst(vcvtUFixedFpDIop);
1242 exec_output += PredOpExecute.subst(vcvtUFixedFpDIop);
1243
1244 vcvtFpSHFixedSCode = '''
1245 vfpFlushToZero(Fpscr, FpOp1);
1246 VfpSavedState state = prepVfpFpscr(Fpscr);
1247 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
1248 FpDest.sh = vfpFpSToFixed(FpOp1, true, true, imm);
1249 __asm__ __volatile__("" :: "m" (FpDest.sh));
1250 Fpscr = setVfpFpscr(Fpscr, state);
1251 '''
1252 vcvtFpSHFixedSIop = InstObjParams("vcvt", "VcvtFpSHFixedS",
1253 "FpRegRegImmOp",
1254 { "code": vcvtFpSHFixedSCode,
1255 "predicate_test": predicateTest }, [])
1256 header_output += FpRegRegImmOpDeclare.subst(vcvtFpSHFixedSIop);
1257 decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpSHFixedSIop);
1258 exec_output += PredOpExecute.subst(vcvtFpSHFixedSIop);
1259
1260 vcvtFpSHFixedDCode = '''
1261 IntDoubleUnion cOp1;
1262 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
1263 vfpFlushToZero(Fpscr, cOp1.fp);
1264 VfpSavedState state = prepVfpFpscr(Fpscr);
1265 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp));
1266 uint64_t result = vfpFpDToFixed(cOp1.fp, true, true, imm);
1267 __asm__ __volatile__("" :: "m" (result));
1268 Fpscr = setVfpFpscr(Fpscr, state);
1269 FpDestP0.uw = result;
1270 FpDestP1.uw = result >> 32;
1271 '''
1272 vcvtFpSHFixedDIop = InstObjParams("vcvt", "VcvtFpSHFixedD",
1273 "FpRegRegImmOp",
1274 { "code": vcvtFpSHFixedDCode,
1275 "predicate_test": predicateTest }, [])
1276 header_output += FpRegRegImmOpDeclare.subst(vcvtFpSHFixedDIop);
1277 decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpSHFixedDIop);
1278 exec_output += PredOpExecute.subst(vcvtFpSHFixedDIop);
1279
1280 vcvtFpUHFixedSCode = '''
1281 vfpFlushToZero(Fpscr, FpOp1);
1282 VfpSavedState state = prepVfpFpscr(Fpscr);
1283 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
1284 FpDest.uh = vfpFpSToFixed(FpOp1, false, true, imm);
1285 __asm__ __volatile__("" :: "m" (FpDest.uh));
1286 Fpscr = setVfpFpscr(Fpscr, state);
1287 '''
1288 vcvtFpUHFixedSIop = InstObjParams("vcvt", "VcvtFpUHFixedS",
1289 "FpRegRegImmOp",
1290 { "code": vcvtFpUHFixedSCode,
1291 "predicate_test": predicateTest }, [])
1292 header_output += FpRegRegImmOpDeclare.subst(vcvtFpUHFixedSIop);
1293 decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpUHFixedSIop);
1294 exec_output += PredOpExecute.subst(vcvtFpUHFixedSIop);
1295
1296 vcvtFpUHFixedDCode = '''
1297 IntDoubleUnion cOp1;
1298 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
1299 vfpFlushToZero(Fpscr, cOp1.fp);
1300 VfpSavedState state = prepVfpFpscr(Fpscr);
1301 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp));
1302 uint64_t mid = vfpFpDToFixed(cOp1.fp, false, true, imm);
1303 __asm__ __volatile__("" :: "m" (mid));
1304 Fpscr = setVfpFpscr(Fpscr, state);
1305 FpDestP0.uw = mid;
1306 FpDestP1.uw = mid >> 32;
1307 '''
1308 vcvtFpUHFixedDIop = InstObjParams("vcvt", "VcvtFpUHFixedD",
1309 "FpRegRegImmOp",
1310 { "code": vcvtFpUHFixedDCode,
1311 "predicate_test": predicateTest }, [])
1312 header_output += FpRegRegImmOpDeclare.subst(vcvtFpUHFixedDIop);
1313 decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpUHFixedDIop);
1314 exec_output += PredOpExecute.subst(vcvtFpUHFixedDIop);
1315
1316 vcvtSHFixedFpSCode = '''
1317 VfpSavedState state = prepVfpFpscr(Fpscr);
1318 __asm__ __volatile__("" : "=m" (FpOp1.sh) : "m" (FpOp1.sh));
1319 FpDest = vfpSFixedToFpS(Fpscr, FpOp1.sh, true, imm);
1320 __asm__ __volatile__("" :: "m" (FpDest));
1321 Fpscr = setVfpFpscr(Fpscr, state);
1322 '''
1323 vcvtSHFixedFpSIop = InstObjParams("vcvt", "VcvtSHFixedFpS",
1324 "FpRegRegImmOp",
1325 { "code": vcvtSHFixedFpSCode,
1326 "predicate_test": predicateTest }, [])
1327 header_output += FpRegRegImmOpDeclare.subst(vcvtSHFixedFpSIop);
1328 decoder_output += FpRegRegImmOpConstructor.subst(vcvtSHFixedFpSIop);
1329 exec_output += PredOpExecute.subst(vcvtSHFixedFpSIop);
1330
1331 vcvtSHFixedFpDCode = '''
1332 IntDoubleUnion cDest;
1333 uint64_t mid = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
1334 VfpSavedState state = prepVfpFpscr(Fpscr);
1335 __asm__ __volatile__("" : "=m" (mid) : "m" (mid));
1336 cDest.fp = vfpSFixedToFpD(Fpscr, mid, true, imm);
1337 __asm__ __volatile__("" :: "m" (cDest.fp));
1338 Fpscr = setVfpFpscr(Fpscr, state);
1339 FpDestP0.uw = cDest.bits;
1340 FpDestP1.uw = cDest.bits >> 32;
1341 '''
1342 vcvtSHFixedFpDIop = InstObjParams("vcvt", "VcvtSHFixedFpD",
1343 "FpRegRegImmOp",
1344 { "code": vcvtSHFixedFpDCode,
1345 "predicate_test": predicateTest }, [])
1346 header_output += FpRegRegImmOpDeclare.subst(vcvtSHFixedFpDIop);
1347 decoder_output += FpRegRegImmOpConstructor.subst(vcvtSHFixedFpDIop);
1348 exec_output += PredOpExecute.subst(vcvtSHFixedFpDIop);
1349
1350 vcvtUHFixedFpSCode = '''
1351 VfpSavedState state = prepVfpFpscr(Fpscr);
1352 __asm__ __volatile__("" : "=m" (FpOp1.uh) : "m" (FpOp1.uh));
1353 FpDest = vfpUFixedToFpS(Fpscr, FpOp1.uh, true, imm);
1354 __asm__ __volatile__("" :: "m" (FpDest));
1355 Fpscr = setVfpFpscr(Fpscr, state);
1356 '''
1357 vcvtUHFixedFpSIop = InstObjParams("vcvt", "VcvtUHFixedFpS",
1358 "FpRegRegImmOp",
1359 { "code": vcvtUHFixedFpSCode,
1360 "predicate_test": predicateTest }, [])
1361 header_output += FpRegRegImmOpDeclare.subst(vcvtUHFixedFpSIop);
1362 decoder_output += FpRegRegImmOpConstructor.subst(vcvtUHFixedFpSIop);
1363 exec_output += PredOpExecute.subst(vcvtUHFixedFpSIop);
1364
1365 vcvtUHFixedFpDCode = '''
1366 IntDoubleUnion cDest;
1367 uint64_t mid = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
1368 VfpSavedState state = prepVfpFpscr(Fpscr);
1369 __asm__ __volatile__("" : "=m" (mid) : "m" (mid));
1370 cDest.fp = vfpUFixedToFpD(Fpscr, mid, true, imm);
1371 __asm__ __volatile__("" :: "m" (cDest.fp));
1372 Fpscr = setVfpFpscr(Fpscr, state);
1373 FpDestP0.uw = cDest.bits;
1374 FpDestP1.uw = cDest.bits >> 32;
1375 '''
1376 vcvtUHFixedFpDIop = InstObjParams("vcvt", "VcvtUHFixedFpD",
1377 "FpRegRegImmOp",
1378 { "code": vcvtUHFixedFpDCode,
1379 "predicate_test": predicateTest }, [])
1380 header_output += FpRegRegImmOpDeclare.subst(vcvtUHFixedFpDIop);
1381 decoder_output += FpRegRegImmOpConstructor.subst(vcvtUHFixedFpDIop);
1382 exec_output += PredOpExecute.subst(vcvtUHFixedFpDIop);
1383}};