1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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1096 vcvtFpDFpSIop = InstObjParams("vcvt", "VcvtFpDFpS", "VfpRegRegOp",
1097 { "code": vcvtFpDFpSCode,
1098 "predicate_test": predicateTest }, [])
1099 header_output += VfpRegRegOpDeclare.subst(vcvtFpDFpSIop);
1100 decoder_output += VfpRegRegOpConstructor.subst(vcvtFpDFpSIop);
1101 exec_output += PredOpExecute.subst(vcvtFpDFpSIop);
1102
1103 vcmpSCode = '''
1104 FPSCR fpscr = Fpscr;
1105 vfpFlushToZero(Fpscr, FpDest, FpOp1);
1106 if (FpDest == FpOp1) {
1107 fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0;
1108 } else if (FpDest < FpOp1) {
1109 fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0;
1110 } else if (FpDest > FpOp1) {
1111 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0;
1112 } else {
1113 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1;
1114 }
1115 Fpscr = fpscr;
1116 '''
1117 vcmpSIop = InstObjParams("vcmps", "VcmpS", "VfpRegRegOp",
1118 { "code": vcmpSCode,
1119 "predicate_test": predicateTest }, [])
1120 header_output += VfpRegRegOpDeclare.subst(vcmpSIop);

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1129 FPSCR fpscr = Fpscr;
1130 if (cDest.fp == cOp1.fp) {
1131 fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0;
1132 } else if (cDest.fp < cOp1.fp) {
1133 fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0;
1134 } else if (cDest.fp > cOp1.fp) {
1135 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0;
1136 } else {
1137 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1;
1138 }
1139 Fpscr = fpscr;
1140 '''
1141 vcmpDIop = InstObjParams("vcmpd", "VcmpD", "VfpRegRegOp",
1142 { "code": vcmpDCode,
1143 "predicate_test": predicateTest }, [])
1144 header_output += VfpRegRegOpDeclare.subst(vcmpDIop);
1145 decoder_output += VfpRegRegOpConstructor.subst(vcmpDIop);
1146 exec_output += PredOpExecute.subst(vcmpDIop);
1147
1148 vcmpZeroSCode = '''
1149 FPSCR fpscr = Fpscr;
1150 vfpFlushToZero(Fpscr, FpDest);
1151 if (FpDest == imm) {
1152 fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0;
1153 } else if (FpDest < imm) {
1154 fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0;
1155 } else if (FpDest > imm) {
1156 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0;
1157 } else {
1158 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1;
1159 }
1160 Fpscr = fpscr;
1161 '''
1162 vcmpZeroSIop = InstObjParams("vcmpZeros", "VcmpZeroS", "VfpRegImmOp",
1163 { "code": vcmpZeroSCode,
1164 "predicate_test": predicateTest }, [])
1165 header_output += VfpRegImmOpDeclare.subst(vcmpZeroSIop);
1166 decoder_output += VfpRegImmOpConstructor.subst(vcmpZeroSIop);
1167 exec_output += PredOpExecute.subst(vcmpZeroSIop);
1168
1169 vcmpZeroDCode = '''
1170 IntDoubleUnion cDest;
1171 cDest.bits = ((uint64_t)FpDestP0.uw | ((uint64_t)FpDestP1.uw << 32));
1172 vfpFlushToZero(Fpscr, cDest.fp);
1173 FPSCR fpscr = Fpscr;
1174 if (cDest.fp == imm) {
1175 fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0;
1176 } else if (cDest.fp < imm) {
1177 fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0;
1178 } else if (cDest.fp > imm) {
1179 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0;
1180 } else {
1181 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1;
1182 }
1183 Fpscr = fpscr;
1184 '''
1185 vcmpZeroDIop = InstObjParams("vcmpZerod", "VcmpZeroD", "VfpRegImmOp",
1186 { "code": vcmpZeroDCode,
1187 "predicate_test": predicateTest }, [])
1188 header_output += VfpRegImmOpDeclare.subst(vcmpZeroDIop);
1189 decoder_output += VfpRegImmOpConstructor.subst(vcmpZeroDIop);
1190 exec_output += PredOpExecute.subst(vcmpZeroDIop);
1191}};
1192
1193let {{
1194
1195 header_output = ""
1196 decoder_output = ""
1197 exec_output = ""
1198

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