1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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369 Op1.uw = FpOp2P1.uw;
370 '''
371 vmov2Core2RegIop = InstObjParams("vmov", "Vmov2Core2Reg", "VfpRegRegRegOp",
372 { "code": vmov2Core2RegCode,
373 "predicate_test": predicateTest }, [])
374 header_output += VfpRegRegRegOpDeclare.subst(vmov2Core2RegIop);
375 decoder_output += VfpRegRegRegOpConstructor.subst(vmov2Core2RegIop);
376 exec_output += PredOpExecute.subst(vmov2Core2RegIop);
377
378 vmulSCode = '''
379 VfpSavedState state = prepVfpFpscr(Fpscr);
380 FpDest = FpOp1 * FpOp2;
381 Fpscr = setVfpFpscr(Fpscr, state);
382 if ((isinf(FpOp1) && FpOp2 == 0) || (isinf(FpOp2) && FpOp1 == 0)) {
383 FpDest = NAN;
384 }
385 '''
386 vmulSIop = InstObjParams("vmuls", "VmulS", "VfpRegRegRegOp",
387 { "code": vmulSCode,
388 "predicate_test": predicateTest }, [])
389 header_output += VfpRegRegRegOpDeclare.subst(vmulSIop);
390 decoder_output += VfpRegRegRegOpConstructor.subst(vmulSIop);
391 exec_output += PredOpExecute.subst(vmulSIop);
392
393 vmulDCode = '''
394 IntDoubleUnion cOp1, cOp2, cDest;
395 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
396 cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32));
397 VfpSavedState state = prepVfpFpscr(Fpscr);
398 cDest.fp = cOp1.fp * cOp2.fp;
399 Fpscr = setVfpFpscr(Fpscr, state);
400 if ((isinf(cOp1.fp) && cOp2.fp == 0) ||
401 (isinf(cOp2.fp) && cOp1.fp == 0)) {
402 cDest.fp = NAN;
403 }
404 FpDestP0.uw = cDest.bits;
405 FpDestP1.uw = cDest.bits >> 32;
406 '''

--- 49 unchanged lines hidden (view full) ---

456 { "code": vabsDCode,
457 "predicate_test": predicateTest }, [])
458 header_output += VfpRegRegOpDeclare.subst(vabsDIop);
459 decoder_output += VfpRegRegOpConstructor.subst(vabsDIop);
460 exec_output += PredOpExecute.subst(vabsDIop);
461
462 vaddSCode = '''
463 VfpSavedState state = prepVfpFpscr(Fpscr);
464 FpDest = FpOp1 + FpOp2;
465 Fpscr = setVfpFpscr(Fpscr, state);
466 '''
467 vaddSIop = InstObjParams("vadds", "VaddS", "VfpRegRegRegOp",
468 { "code": vaddSCode,
469 "predicate_test": predicateTest }, [])
470 header_output += VfpRegRegRegOpDeclare.subst(vaddSIop);
471 decoder_output += VfpRegRegRegOpConstructor.subst(vaddSIop);
472 exec_output += PredOpExecute.subst(vaddSIop);
473
474 vaddDCode = '''
475 IntDoubleUnion cOp1, cOp2, cDest;
476 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
477 cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32));
478 VfpSavedState state = prepVfpFpscr(Fpscr);
479 cDest.fp = cOp1.fp + cOp2.fp;
480 Fpscr = setVfpFpscr(Fpscr, state);
481 FpDestP0.uw = cDest.bits;
482 FpDestP1.uw = cDest.bits >> 32;
483 '''
484 vaddDIop = InstObjParams("vaddd", "VaddD", "VfpRegRegRegOp",
485 { "code": vaddDCode,
486 "predicate_test": predicateTest }, [])
487 header_output += VfpRegRegRegOpDeclare.subst(vaddDIop);
488 decoder_output += VfpRegRegRegOpConstructor.subst(vaddDIop);
489 exec_output += PredOpExecute.subst(vaddDIop);
490
491 vsubSCode = '''
492 VfpSavedState state = prepVfpFpscr(Fpscr);
493 FpDest = FpOp1 - FpOp2;
494 Fpscr = setVfpFpscr(Fpscr, state)
495 '''
496 vsubSIop = InstObjParams("vsubs", "VsubS", "VfpRegRegRegOp",
497 { "code": vsubSCode,
498 "predicate_test": predicateTest }, [])
499 header_output += VfpRegRegRegOpDeclare.subst(vsubSIop);
500 decoder_output += VfpRegRegRegOpConstructor.subst(vsubSIop);
501 exec_output += PredOpExecute.subst(vsubSIop);
502
503 vsubDCode = '''
504 IntDoubleUnion cOp1, cOp2, cDest;
505 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
506 cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32));
507 VfpSavedState state = prepVfpFpscr(Fpscr);
508 cDest.fp = cOp1.fp - cOp2.fp;
509 Fpscr = setVfpFpscr(Fpscr, state);
510 FpDestP0.uw = cDest.bits;
511 FpDestP1.uw = cDest.bits >> 32;
512 '''
513 vsubDIop = InstObjParams("vsubd", "VsubD", "VfpRegRegRegOp",
514 { "code": vsubDCode,
515 "predicate_test": predicateTest }, [])
516 header_output += VfpRegRegRegOpDeclare.subst(vsubDIop);
517 decoder_output += VfpRegRegRegOpConstructor.subst(vsubDIop);
518 exec_output += PredOpExecute.subst(vsubDIop);
519
520 vdivSCode = '''
521 VfpSavedState state = prepVfpFpscr(Fpscr);
522 FpDest = FpOp1 / FpOp2;
523 Fpscr = setVfpFpscr(Fpscr, state);
524 '''
525 vdivSIop = InstObjParams("vdivs", "VdivS", "VfpRegRegRegOp",
526 { "code": vdivSCode,
527 "predicate_test": predicateTest }, [])
528 header_output += VfpRegRegRegOpDeclare.subst(vdivSIop);
529 decoder_output += VfpRegRegRegOpConstructor.subst(vdivSIop);
530 exec_output += PredOpExecute.subst(vdivSIop);
531
532 vdivDCode = '''
533 IntDoubleUnion cOp1, cOp2, cDest;
534 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
535 cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32));
536 VfpSavedState state = prepVfpFpscr(Fpscr);
537 cDest.fp = cOp1.fp / cOp2.fp;
538 Fpscr = setVfpFpscr(Fpscr, state);
539 FpDestP0.uw = cDest.bits;
540 FpDestP1.uw = cDest.bits >> 32;
541 '''
542 vdivDIop = InstObjParams("vdivd", "VdivD", "VfpRegRegRegOp",
543 { "code": vdivDCode,
544 "predicate_test": predicateTest }, [])
545 header_output += VfpRegRegRegOpDeclare.subst(vdivDIop);
546 decoder_output += VfpRegRegRegOpConstructor.subst(vdivDIop);
547 exec_output += PredOpExecute.subst(vdivDIop);
548
549 vsqrtSCode = '''
550 VfpSavedState state = prepVfpFpscr(Fpscr);
551 FpDest = sqrtf(FpOp1);
552 Fpscr = setVfpFpscr(Fpscr, state);
553 if (FpOp1 < 0) {
554 FpDest = NAN;
555 }
556 '''
557 vsqrtSIop = InstObjParams("vsqrts", "VsqrtS", "VfpRegRegOp",
558 { "code": vsqrtSCode,
559 "predicate_test": predicateTest }, [])
560 header_output += VfpRegRegOpDeclare.subst(vsqrtSIop);
561 decoder_output += VfpRegRegOpConstructor.subst(vsqrtSIop);
562 exec_output += PredOpExecute.subst(vsqrtSIop);
563
564 vsqrtDCode = '''
565 IntDoubleUnion cOp1, cDest;
566 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
567 VfpSavedState state = prepVfpFpscr(Fpscr);
568 cDest.fp = sqrt(cOp1.fp);
569 Fpscr = setVfpFpscr(Fpscr, state);
570 if (cOp1.fp < 0) {
571 cDest.fp = NAN;
572 }
573 FpDestP0.uw = cDest.bits;
574 FpDestP1.uw = cDest.bits >> 32;
575 '''
576 vsqrtDIop = InstObjParams("vsqrtd", "VsqrtD", "VfpRegRegOp",
577 { "code": vsqrtDCode,
578 "predicate_test": predicateTest }, [])
579 header_output += VfpRegRegOpDeclare.subst(vsqrtDIop);
580 decoder_output += VfpRegRegOpConstructor.subst(vsqrtDIop);
581 exec_output += PredOpExecute.subst(vsqrtDIop);
582
583 vmlaSCode = '''
584 VfpSavedState state = prepVfpFpscr(Fpscr);
585 float mid = FpOp1 * FpOp2;
586 if ((isinf(FpOp1) && FpOp2 == 0) || (isinf(FpOp2) && FpOp1 == 0)) {
587 mid = NAN;
588 }
589 FpDest = FpDest + mid;
590 Fpscr = setVfpFpscr(Fpscr, state);
591 '''
592 vmlaSIop = InstObjParams("vmlas", "VmlaS", "VfpRegRegRegOp",
593 { "code": vmlaSCode,
594 "predicate_test": predicateTest }, [])
595 header_output += VfpRegRegRegOpDeclare.subst(vmlaSIop);
596 decoder_output += VfpRegRegRegOpConstructor.subst(vmlaSIop);
597 exec_output += PredOpExecute.subst(vmlaSIop);
598
599 vmlaDCode = '''
600 IntDoubleUnion cOp1, cOp2, cDest;
601 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
602 cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32));
603 cDest.bits = ((uint64_t)FpDestP0.uw | ((uint64_t)FpDestP1.uw << 32));
604 VfpSavedState state = prepVfpFpscr(Fpscr);
605 double mid = cOp1.fp * cOp2.fp;
606 if ((isinf(cOp1.fp) && cOp2.fp == 0) ||
607 (isinf(cOp2.fp) && cOp1.fp == 0)) {
608 mid = NAN;
609 }
610 cDest.fp = cDest.fp + mid;
611 Fpscr = setVfpFpscr(Fpscr, state);
612 FpDestP0.uw = cDest.bits;
613 FpDestP1.uw = cDest.bits >> 32;
614 '''
615 vmlaDIop = InstObjParams("vmlad", "VmlaD", "VfpRegRegRegOp",
616 { "code": vmlaDCode,
617 "predicate_test": predicateTest }, [])
618 header_output += VfpRegRegRegOpDeclare.subst(vmlaDIop);
619 decoder_output += VfpRegRegRegOpConstructor.subst(vmlaDIop);
620 exec_output += PredOpExecute.subst(vmlaDIop);
621
622 vmlsSCode = '''
623 VfpSavedState state = prepVfpFpscr(Fpscr);
624 float mid = FpOp1 * FpOp2;
625 if ((isinf(FpOp1) && FpOp2 == 0) || (isinf(FpOp2) && FpOp1 == 0)) {
626 mid = NAN;
627 }
628 FpDest = FpDest - mid;
629 Fpscr = setVfpFpscr(Fpscr, state);
630 '''
631 vmlsSIop = InstObjParams("vmlss", "VmlsS", "VfpRegRegRegOp",
632 { "code": vmlsSCode,
633 "predicate_test": predicateTest }, [])
634 header_output += VfpRegRegRegOpDeclare.subst(vmlsSIop);
635 decoder_output += VfpRegRegRegOpConstructor.subst(vmlsSIop);
636 exec_output += PredOpExecute.subst(vmlsSIop);
637
638 vmlsDCode = '''
639 IntDoubleUnion cOp1, cOp2, cDest;
640 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
641 cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32));
642 cDest.bits = ((uint64_t)FpDestP0.uw | ((uint64_t)FpDestP1.uw << 32));
643 VfpSavedState state = prepVfpFpscr(Fpscr);
644 double mid = cOp1.fp * cOp2.fp;
645 if ((isinf(cOp1.fp) && cOp2.fp == 0) ||
646 (isinf(cOp2.fp) && cOp1.fp == 0)) {
647 mid = NAN;
648 }
649 cDest.fp = cDest.fp - mid;
650 Fpscr = setVfpFpscr(Fpscr, state);
651 FpDestP0.uw = cDest.bits;
652 FpDestP1.uw = cDest.bits >> 32;
653 '''
654 vmlsDIop = InstObjParams("vmlsd", "VmlsD", "VfpRegRegRegOp",
655 { "code": vmlsDCode,
656 "predicate_test": predicateTest }, [])
657 header_output += VfpRegRegRegOpDeclare.subst(vmlsDIop);
658 decoder_output += VfpRegRegRegOpConstructor.subst(vmlsDIop);
659 exec_output += PredOpExecute.subst(vmlsDIop);
660
661 vnmlaSCode = '''
662 VfpSavedState state = prepVfpFpscr(Fpscr);
663 float mid = FpOp1 * FpOp2;
664 if ((isinf(FpOp1) && FpOp2 == 0) || (isinf(FpOp2) && FpOp1 == 0)) {
665 mid = NAN;
666 }
667 FpDest = -FpDest - mid;
668 Fpscr = setVfpFpscr(Fpscr, state);
669 '''
670 vnmlaSIop = InstObjParams("vnmlas", "VnmlaS", "VfpRegRegRegOp",
671 { "code": vnmlaSCode,
672 "predicate_test": predicateTest }, [])
673 header_output += VfpRegRegRegOpDeclare.subst(vnmlaSIop);
674 decoder_output += VfpRegRegRegOpConstructor.subst(vnmlaSIop);
675 exec_output += PredOpExecute.subst(vnmlaSIop);
676
677 vnmlaDCode = '''
678 IntDoubleUnion cOp1, cOp2, cDest;
679 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
680 cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32));
681 cDest.bits = ((uint64_t)FpDestP0.uw | ((uint64_t)FpDestP1.uw << 32));
682 VfpSavedState state = prepVfpFpscr(Fpscr);
683 double mid = cOp1.fp * cOp2.fp;
684 if ((isinf(cOp1.fp) && cOp2.fp == 0) ||
685 (isinf(cOp2.fp) && cOp1.fp == 0)) {
686 mid = NAN;
687 }
688 cDest.fp = -cDest.fp - mid;
689 Fpscr = setVfpFpscr(Fpscr, state);
690 FpDestP0.uw = cDest.bits;
691 FpDestP1.uw = cDest.bits >> 32;
692 '''
693 vnmlaDIop = InstObjParams("vnmlad", "VnmlaD", "VfpRegRegRegOp",
694 { "code": vnmlaDCode,
695 "predicate_test": predicateTest }, [])
696 header_output += VfpRegRegRegOpDeclare.subst(vnmlaDIop);
697 decoder_output += VfpRegRegRegOpConstructor.subst(vnmlaDIop);
698 exec_output += PredOpExecute.subst(vnmlaDIop);
699
700 vnmlsSCode = '''
701 VfpSavedState state = prepVfpFpscr(Fpscr);
702 float mid = FpOp1 * FpOp2;
703 if ((isinf(FpOp1) && FpOp2 == 0) || (isinf(FpOp2) && FpOp1 == 0)) {
704 mid = NAN;
705 }
706 FpDest = -FpDest + mid;
707 Fpscr = setVfpFpscr(Fpscr, state);
708 '''
709 vnmlsSIop = InstObjParams("vnmlss", "VnmlsS", "VfpRegRegRegOp",
710 { "code": vnmlsSCode,
711 "predicate_test": predicateTest }, [])
712 header_output += VfpRegRegRegOpDeclare.subst(vnmlsSIop);
713 decoder_output += VfpRegRegRegOpConstructor.subst(vnmlsSIop);
714 exec_output += PredOpExecute.subst(vnmlsSIop);
715
716 vnmlsDCode = '''
717 IntDoubleUnion cOp1, cOp2, cDest;
718 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
719 cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32));
720 cDest.bits = ((uint64_t)FpDestP0.uw | ((uint64_t)FpDestP1.uw << 32));
721 VfpSavedState state = prepVfpFpscr(Fpscr);
722 double mid = cOp1.fp * cOp2.fp;
723 if ((isinf(cOp1.fp) && cOp2.fp == 0) ||
724 (isinf(cOp2.fp) && cOp1.fp == 0)) {
725 mid = NAN;
726 }
727 cDest.fp = -cDest.fp + mid;
728 Fpscr = setVfpFpscr(Fpscr, state);
729 FpDestP0.uw = cDest.bits;
730 FpDestP1.uw = cDest.bits >> 32;
731 '''
732 vnmlsDIop = InstObjParams("vnmlsd", "VnmlsD", "VfpRegRegRegOp",
733 { "code": vnmlsDCode,
734 "predicate_test": predicateTest }, [])
735 header_output += VfpRegRegRegOpDeclare.subst(vnmlsDIop);
736 decoder_output += VfpRegRegRegOpConstructor.subst(vnmlsDIop);
737 exec_output += PredOpExecute.subst(vnmlsDIop);
738
739 vnmulSCode = '''
740 VfpSavedState state = prepVfpFpscr(Fpscr);
741 float mid = FpOp1 * FpOp2;
742 if ((isinf(FpOp1) && FpOp2 == 0) || (isinf(FpOp2) && FpOp1 == 0)) {
743 mid = NAN;
744 }
745 FpDest = -mid;
746 Fpscr = setVfpFpscr(Fpscr, state);
747 '''
748 vnmulSIop = InstObjParams("vnmuls", "VnmulS", "VfpRegRegRegOp",
749 { "code": vnmulSCode,
750 "predicate_test": predicateTest }, [])
751 header_output += VfpRegRegRegOpDeclare.subst(vnmulSIop);
752 decoder_output += VfpRegRegRegOpConstructor.subst(vnmulSIop);
753 exec_output += PredOpExecute.subst(vnmulSIop);
754
755 vnmulDCode = '''
756 IntDoubleUnion cOp1, cOp2, cDest;
757 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
758 cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32));
759 cDest.bits = ((uint64_t)FpDestP0.uw | ((uint64_t)FpDestP1.uw << 32));
760 VfpSavedState state = prepVfpFpscr(Fpscr);
761 double mid = cOp1.fp * cOp2.fp;
762 if ((isinf(cOp1.fp) && cOp2.fp == 0) ||
763 (isinf(cOp2.fp) && cOp1.fp == 0)) {
764 mid = NAN;
765 }
766 cDest.fp = -mid;
767 Fpscr = setVfpFpscr(Fpscr, state);
768 FpDestP0.uw = cDest.bits;
769 FpDestP1.uw = cDest.bits >> 32;
770 '''
771 vnmulDIop = InstObjParams("vnmuld", "VnmulD", "VfpRegRegRegOp",
772 { "code": vnmulDCode,
773 "predicate_test": predicateTest }, [])
774 header_output += VfpRegRegRegOpDeclare.subst(vnmulDIop);
775 decoder_output += VfpRegRegRegOpConstructor.subst(vnmulDIop);
776 exec_output += PredOpExecute.subst(vnmulDIop);
777
778 vcvtUIntFpSCode = '''
779 VfpSavedState state = prepVfpFpscr(Fpscr);
780 FpDest = FpOp1.uw;
781 Fpscr = setVfpFpscr(Fpscr, state);
782 '''
783 vcvtUIntFpSIop = InstObjParams("vcvt", "VcvtUIntFpS", "VfpRegRegOp",
784 { "code": vcvtUIntFpSCode,
785 "predicate_test": predicateTest }, [])
786 header_output += VfpRegRegOpDeclare.subst(vcvtUIntFpSIop);
787 decoder_output += VfpRegRegOpConstructor.subst(vcvtUIntFpSIop);
788 exec_output += PredOpExecute.subst(vcvtUIntFpSIop);
789
790 vcvtUIntFpDCode = '''
791 IntDoubleUnion cDest;
792 VfpSavedState state = prepVfpFpscr(Fpscr);
793 cDest.fp = (uint64_t)FpOp1P0.uw;
794 Fpscr = setVfpFpscr(Fpscr, state);
795 FpDestP0.uw = cDest.bits;
796 FpDestP1.uw = cDest.bits >> 32;
797 '''
798 vcvtUIntFpDIop = InstObjParams("vcvt", "VcvtUIntFpD", "VfpRegRegOp",
799 { "code": vcvtUIntFpDCode,
800 "predicate_test": predicateTest }, [])
801 header_output += VfpRegRegOpDeclare.subst(vcvtUIntFpDIop);
802 decoder_output += VfpRegRegOpConstructor.subst(vcvtUIntFpDIop);
803 exec_output += PredOpExecute.subst(vcvtUIntFpDIop);
804
805 vcvtSIntFpSCode = '''
806 VfpSavedState state = prepVfpFpscr(Fpscr);
807 FpDest = FpOp1.sw;
808 Fpscr = setVfpFpscr(Fpscr, state);
809 '''
810 vcvtSIntFpSIop = InstObjParams("vcvt", "VcvtSIntFpS", "VfpRegRegOp",
811 { "code": vcvtSIntFpSCode,
812 "predicate_test": predicateTest }, [])
813 header_output += VfpRegRegOpDeclare.subst(vcvtSIntFpSIop);
814 decoder_output += VfpRegRegOpConstructor.subst(vcvtSIntFpSIop);
815 exec_output += PredOpExecute.subst(vcvtSIntFpSIop);
816
817 vcvtSIntFpDCode = '''
818 IntDoubleUnion cDest;
819 VfpSavedState state = prepVfpFpscr(Fpscr);
820 cDest.fp = FpOp1P0.sw;
821 Fpscr = setVfpFpscr(Fpscr, state);
822 FpDestP0.uw = cDest.bits;
823 FpDestP1.uw = cDest.bits >> 32;
824 '''
825 vcvtSIntFpDIop = InstObjParams("vcvt", "VcvtSIntFpD", "VfpRegRegOp",
826 { "code": vcvtSIntFpDCode,
827 "predicate_test": predicateTest }, [])
828 header_output += VfpRegRegOpDeclare.subst(vcvtSIntFpDIop);
829 decoder_output += VfpRegRegOpConstructor.subst(vcvtSIntFpDIop);
830 exec_output += PredOpExecute.subst(vcvtSIntFpDIop);
831
832 vcvtFpUIntSRCode = '''
833 VfpSavedState state = prepVfpFpscr(Fpscr);
834 FpDest.uw = FpOp1;
835 Fpscr = setVfpFpscr(Fpscr, state);
836 '''
837 vcvtFpUIntSRIop = InstObjParams("vcvt", "VcvtFpUIntSR", "VfpRegRegOp",
838 { "code": vcvtFpUIntSRCode,
839 "predicate_test": predicateTest }, [])
840 header_output += VfpRegRegOpDeclare.subst(vcvtFpUIntSRIop);
841 decoder_output += VfpRegRegOpConstructor.subst(vcvtFpUIntSRIop);
842 exec_output += PredOpExecute.subst(vcvtFpUIntSRIop);
843
844 vcvtFpUIntDRCode = '''
845 IntDoubleUnion cOp1;
846 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
847 VfpSavedState state = prepVfpFpscr(Fpscr);
848 uint64_t result = cOp1.fp;
849 Fpscr = setVfpFpscr(Fpscr, state);
850 FpDestP0.uw = result;
851 '''
852 vcvtFpUIntDRIop = InstObjParams("vcvtr", "VcvtFpUIntDR", "VfpRegRegOp",
853 { "code": vcvtFpUIntDRCode,
854 "predicate_test": predicateTest }, [])
855 header_output += VfpRegRegOpDeclare.subst(vcvtFpUIntDRIop);
856 decoder_output += VfpRegRegOpConstructor.subst(vcvtFpUIntDRIop);
857 exec_output += PredOpExecute.subst(vcvtFpUIntDRIop);
858
859 vcvtFpSIntSRCode = '''
860 VfpSavedState state = prepVfpFpscr(Fpscr);
861 FpDest.sw = FpOp1;
862 Fpscr = setVfpFpscr(Fpscr, state);
863 '''
864 vcvtFpSIntSRIop = InstObjParams("vcvtr", "VcvtFpSIntSR", "VfpRegRegOp",
865 { "code": vcvtFpSIntSRCode,
866 "predicate_test": predicateTest }, [])
867 header_output += VfpRegRegOpDeclare.subst(vcvtFpSIntSRIop);
868 decoder_output += VfpRegRegOpConstructor.subst(vcvtFpSIntSRIop);
869 exec_output += PredOpExecute.subst(vcvtFpSIntSRIop);
870
871 vcvtFpSIntDRCode = '''
872 IntDoubleUnion cOp1;
873 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
874 VfpSavedState state = prepVfpFpscr(Fpscr);
875 int64_t result = cOp1.fp;
876 Fpscr = setVfpFpscr(Fpscr, state);
877 FpDestP0.uw = result;
878 '''
879 vcvtFpSIntDRIop = InstObjParams("vcvtr", "VcvtFpSIntDR", "VfpRegRegOp",
880 { "code": vcvtFpSIntDRCode,
881 "predicate_test": predicateTest }, [])
882 header_output += VfpRegRegOpDeclare.subst(vcvtFpSIntDRIop);
883 decoder_output += VfpRegRegOpConstructor.subst(vcvtFpSIntDRIop);
884 exec_output += PredOpExecute.subst(vcvtFpSIntDRIop);
885
886 vcvtFpUIntSCode = '''
887 VfpSavedState state = prepVfpFpscr(Fpscr);
888 fesetround(FeRoundZero);
889 FpDest.uw = FpOp1;
890 Fpscr = setVfpFpscr(Fpscr, state);
891 '''
892 vcvtFpUIntSIop = InstObjParams("vcvt", "VcvtFpUIntS", "VfpRegRegOp",
893 { "code": vcvtFpUIntSCode,
894 "predicate_test": predicateTest }, [])
895 header_output += VfpRegRegOpDeclare.subst(vcvtFpUIntSIop);
896 decoder_output += VfpRegRegOpConstructor.subst(vcvtFpUIntSIop);
897 exec_output += PredOpExecute.subst(vcvtFpUIntSIop);
898
899 vcvtFpUIntDCode = '''
900 IntDoubleUnion cOp1;
901 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
902 VfpSavedState state = prepVfpFpscr(Fpscr);
903 fesetround(FeRoundZero);
904 uint64_t result = cOp1.fp;
905 Fpscr = setVfpFpscr(Fpscr, state);
906 FpDestP0.uw = result;
907 '''
908 vcvtFpUIntDIop = InstObjParams("vcvt", "VcvtFpUIntD", "VfpRegRegOp",
909 { "code": vcvtFpUIntDCode,
910 "predicate_test": predicateTest }, [])
911 header_output += VfpRegRegOpDeclare.subst(vcvtFpUIntDIop);
912 decoder_output += VfpRegRegOpConstructor.subst(vcvtFpUIntDIop);
913 exec_output += PredOpExecute.subst(vcvtFpUIntDIop);
914
915 vcvtFpSIntSCode = '''
916 VfpSavedState state = prepVfpFpscr(Fpscr);
917 fesetround(FeRoundZero);
918 FpDest.sw = FpOp1;
919 Fpscr = setVfpFpscr(Fpscr, state);
920 '''
921 vcvtFpSIntSIop = InstObjParams("vcvt", "VcvtFpSIntS", "VfpRegRegOp",
922 { "code": vcvtFpSIntSCode,
923 "predicate_test": predicateTest }, [])
924 header_output += VfpRegRegOpDeclare.subst(vcvtFpSIntSIop);
925 decoder_output += VfpRegRegOpConstructor.subst(vcvtFpSIntSIop);
926 exec_output += PredOpExecute.subst(vcvtFpSIntSIop);
927
928 vcvtFpSIntDCode = '''
929 IntDoubleUnion cOp1;
930 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
931 VfpSavedState state = prepVfpFpscr(Fpscr);
932 fesetround(FeRoundZero);
933 int64_t result = cOp1.fp;
934 Fpscr = setVfpFpscr(Fpscr, state);
935 FpDestP0.uw = result;
936 '''
937 vcvtFpSIntDIop = InstObjParams("vcvt", "VcvtFpSIntD", "VfpRegRegOp",
938 { "code": vcvtFpSIntDCode,
939 "predicate_test": predicateTest }, [])
940 header_output += VfpRegRegOpDeclare.subst(vcvtFpSIntDIop);
941 decoder_output += VfpRegRegOpConstructor.subst(vcvtFpSIntDIop);
942 exec_output += PredOpExecute.subst(vcvtFpSIntDIop);
943
944 vcvtFpSFpDCode = '''
945 IntDoubleUnion cDest;
946 VfpSavedState state = prepVfpFpscr(Fpscr);
947 cDest.fp = FpOp1;
948 Fpscr = setVfpFpscr(Fpscr, state);
949 FpDestP0.uw = cDest.bits;
950 FpDestP1.uw = cDest.bits >> 32;
951 '''
952 vcvtFpSFpDIop = InstObjParams("vcvt", "VcvtFpSFpD", "VfpRegRegOp",
953 { "code": vcvtFpSFpDCode,
954 "predicate_test": predicateTest }, [])
955 header_output += VfpRegRegOpDeclare.subst(vcvtFpSFpDIop);
956 decoder_output += VfpRegRegOpConstructor.subst(vcvtFpSFpDIop);
957 exec_output += PredOpExecute.subst(vcvtFpSFpDIop);
958
959 vcvtFpDFpSCode = '''
960 IntDoubleUnion cOp1;
961 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
962 VfpSavedState state = prepVfpFpscr(Fpscr);
963 FpDest = cOp1.fp;
964 Fpscr = setVfpFpscr(Fpscr, state);
965 '''
966 vcvtFpDFpSIop = InstObjParams("vcvt", "VcvtFpDFpS", "VfpRegRegOp",
967 { "code": vcvtFpDFpSCode,
968 "predicate_test": predicateTest }, [])
969 header_output += VfpRegRegOpDeclare.subst(vcvtFpDFpSIop);
970 decoder_output += VfpRegRegOpConstructor.subst(vcvtFpDFpSIop);
971 exec_output += PredOpExecute.subst(vcvtFpDFpSIop);

--- 87 unchanged lines hidden (view full) ---

1059let {{
1060
1061 header_output = ""
1062 decoder_output = ""
1063 exec_output = ""
1064
1065 vcvtFpSFixedSCode = '''
1066 VfpSavedState state = prepVfpFpscr(Fpscr);
1067 FpDest.sw = vfpFpSToFixed(FpOp1, true, false, imm);
1068 Fpscr = setVfpFpscr(Fpscr, state);
1069 '''
1070 vcvtFpSFixedSIop = InstObjParams("vcvt", "VcvtFpSFixedS", "VfpRegRegImmOp",
1071 { "code": vcvtFpSFixedSCode,
1072 "predicate_test": predicateTest }, [])
1073 header_output += VfpRegRegImmOpDeclare.subst(vcvtFpSFixedSIop);
1074 decoder_output += VfpRegRegImmOpConstructor.subst(vcvtFpSFixedSIop);
1075 exec_output += PredOpExecute.subst(vcvtFpSFixedSIop);
1076
1077 vcvtFpSFixedDCode = '''
1078 IntDoubleUnion cOp1;
1079 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
1080 VfpSavedState state = prepVfpFpscr(Fpscr);
1081 uint64_t mid = vfpFpDToFixed(cOp1.fp, true, false, imm);
1082 Fpscr = setVfpFpscr(Fpscr, state);
1083 FpDestP0.uw = mid;
1084 FpDestP1.uw = mid >> 32;
1085 '''
1086 vcvtFpSFixedDIop = InstObjParams("vcvt", "VcvtFpSFixedD", "VfpRegRegImmOp",
1087 { "code": vcvtFpSFixedDCode,
1088 "predicate_test": predicateTest }, [])
1089 header_output += VfpRegRegImmOpDeclare.subst(vcvtFpSFixedDIop);
1090 decoder_output += VfpRegRegImmOpConstructor.subst(vcvtFpSFixedDIop);
1091 exec_output += PredOpExecute.subst(vcvtFpSFixedDIop);
1092
1093 vcvtFpUFixedSCode = '''
1094 VfpSavedState state = prepVfpFpscr(Fpscr);
1095 FpDest.uw = vfpFpSToFixed(FpOp1, false, false, imm);
1096 Fpscr = setVfpFpscr(Fpscr, state);
1097 '''
1098 vcvtFpUFixedSIop = InstObjParams("vcvt", "VcvtFpUFixedS", "VfpRegRegImmOp",
1099 { "code": vcvtFpUFixedSCode,
1100 "predicate_test": predicateTest }, [])
1101 header_output += VfpRegRegImmOpDeclare.subst(vcvtFpUFixedSIop);
1102 decoder_output += VfpRegRegImmOpConstructor.subst(vcvtFpUFixedSIop);
1103 exec_output += PredOpExecute.subst(vcvtFpUFixedSIop);
1104
1105 vcvtFpUFixedDCode = '''
1106 IntDoubleUnion cOp1;
1107 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
1108 VfpSavedState state = prepVfpFpscr(Fpscr);
1109 uint64_t mid = vfpFpDToFixed(cOp1.fp, false, false, imm);
1110 Fpscr = setVfpFpscr(Fpscr, state);
1111 FpDestP0.uw = mid;
1112 FpDestP1.uw = mid >> 32;
1113 '''
1114 vcvtFpUFixedDIop = InstObjParams("vcvt", "VcvtFpUFixedD", "VfpRegRegImmOp",
1115 { "code": vcvtFpUFixedDCode,
1116 "predicate_test": predicateTest }, [])
1117 header_output += VfpRegRegImmOpDeclare.subst(vcvtFpUFixedDIop);
1118 decoder_output += VfpRegRegImmOpConstructor.subst(vcvtFpUFixedDIop);
1119 exec_output += PredOpExecute.subst(vcvtFpUFixedDIop);
1120
1121 vcvtSFixedFpSCode = '''
1122 VfpSavedState state = prepVfpFpscr(Fpscr);
1123 FpDest = vfpSFixedToFpS(FpOp1.sw, false, imm);
1124 Fpscr = setVfpFpscr(Fpscr, state);
1125 '''
1126 vcvtSFixedFpSIop = InstObjParams("vcvt", "VcvtSFixedFpS", "VfpRegRegImmOp",
1127 { "code": vcvtSFixedFpSCode,
1128 "predicate_test": predicateTest }, [])
1129 header_output += VfpRegRegImmOpDeclare.subst(vcvtSFixedFpSIop);
1130 decoder_output += VfpRegRegImmOpConstructor.subst(vcvtSFixedFpSIop);
1131 exec_output += PredOpExecute.subst(vcvtSFixedFpSIop);
1132
1133 vcvtSFixedFpDCode = '''
1134 IntDoubleUnion cDest;
1135 uint64_t mid = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
1136 VfpSavedState state = prepVfpFpscr(Fpscr);
1137 cDest.fp = vfpSFixedToFpD(mid, false, imm);
1138 Fpscr = setVfpFpscr(Fpscr, state);
1139 FpDestP0.uw = cDest.bits;
1140 FpDestP1.uw = cDest.bits >> 32;
1141 '''
1142 vcvtSFixedFpDIop = InstObjParams("vcvt", "VcvtSFixedFpD", "VfpRegRegImmOp",
1143 { "code": vcvtSFixedFpDCode,
1144 "predicate_test": predicateTest }, [])
1145 header_output += VfpRegRegImmOpDeclare.subst(vcvtSFixedFpDIop);
1146 decoder_output += VfpRegRegImmOpConstructor.subst(vcvtSFixedFpDIop);
1147 exec_output += PredOpExecute.subst(vcvtSFixedFpDIop);
1148
1149 vcvtUFixedFpSCode = '''
1150 VfpSavedState state = prepVfpFpscr(Fpscr);
1151 FpDest = vfpUFixedToFpS(FpOp1.uw, false, imm);
1152 Fpscr = setVfpFpscr(Fpscr, state);
1153 '''
1154 vcvtUFixedFpSIop = InstObjParams("vcvt", "VcvtUFixedFpS", "VfpRegRegImmOp",
1155 { "code": vcvtUFixedFpSCode,
1156 "predicate_test": predicateTest }, [])
1157 header_output += VfpRegRegImmOpDeclare.subst(vcvtUFixedFpSIop);
1158 decoder_output += VfpRegRegImmOpConstructor.subst(vcvtUFixedFpSIop);
1159 exec_output += PredOpExecute.subst(vcvtUFixedFpSIop);
1160
1161 vcvtUFixedFpDCode = '''
1162 IntDoubleUnion cDest;
1163 uint64_t mid = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
1164 VfpSavedState state = prepVfpFpscr(Fpscr);
1165 cDest.fp = vfpUFixedToFpD(mid, false, imm);
1166 Fpscr = setVfpFpscr(Fpscr, state);
1167 FpDestP0.uw = cDest.bits;
1168 FpDestP1.uw = cDest.bits >> 32;
1169 '''
1170 vcvtUFixedFpDIop = InstObjParams("vcvt", "VcvtUFixedFpD", "VfpRegRegImmOp",
1171 { "code": vcvtUFixedFpDCode,
1172 "predicate_test": predicateTest }, [])
1173 header_output += VfpRegRegImmOpDeclare.subst(vcvtUFixedFpDIop);
1174 decoder_output += VfpRegRegImmOpConstructor.subst(vcvtUFixedFpDIop);
1175 exec_output += PredOpExecute.subst(vcvtUFixedFpDIop);
1176
1177 vcvtFpSHFixedSCode = '''
1178 VfpSavedState state = prepVfpFpscr(Fpscr);
1179 FpDest.sh = vfpFpSToFixed(FpOp1, true, true, imm);
1180 Fpscr = setVfpFpscr(Fpscr, state);
1181 '''
1182 vcvtFpSHFixedSIop = InstObjParams("vcvt", "VcvtFpSHFixedS",
1183 "VfpRegRegImmOp",
1184 { "code": vcvtFpSHFixedSCode,
1185 "predicate_test": predicateTest }, [])
1186 header_output += VfpRegRegImmOpDeclare.subst(vcvtFpSHFixedSIop);
1187 decoder_output += VfpRegRegImmOpConstructor.subst(vcvtFpSHFixedSIop);
1188 exec_output += PredOpExecute.subst(vcvtFpSHFixedSIop);
1189
1190 vcvtFpSHFixedDCode = '''
1191 IntDoubleUnion cOp1;
1192 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
1193 VfpSavedState state = prepVfpFpscr(Fpscr);
1194 uint64_t result = vfpFpDToFixed(cOp1.fp, true, true, imm);
1195 Fpscr = setVfpFpscr(Fpscr, state);
1196 FpDestP0.uw = result;
1197 FpDestP1.uw = result >> 32;
1198 '''
1199 vcvtFpSHFixedDIop = InstObjParams("vcvt", "VcvtFpSHFixedD",
1200 "VfpRegRegImmOp",
1201 { "code": vcvtFpSHFixedDCode,
1202 "predicate_test": predicateTest }, [])
1203 header_output += VfpRegRegImmOpDeclare.subst(vcvtFpSHFixedDIop);
1204 decoder_output += VfpRegRegImmOpConstructor.subst(vcvtFpSHFixedDIop);
1205 exec_output += PredOpExecute.subst(vcvtFpSHFixedDIop);
1206
1207 vcvtFpUHFixedSCode = '''
1208 VfpSavedState state = prepVfpFpscr(Fpscr);
1209 FpDest.uh = vfpFpSToFixed(FpOp1, false, true, imm);
1210 Fpscr = setVfpFpscr(Fpscr, state);
1211 '''
1212 vcvtFpUHFixedSIop = InstObjParams("vcvt", "VcvtFpUHFixedS",
1213 "VfpRegRegImmOp",
1214 { "code": vcvtFpUHFixedSCode,
1215 "predicate_test": predicateTest }, [])
1216 header_output += VfpRegRegImmOpDeclare.subst(vcvtFpUHFixedSIop);
1217 decoder_output += VfpRegRegImmOpConstructor.subst(vcvtFpUHFixedSIop);
1218 exec_output += PredOpExecute.subst(vcvtFpUHFixedSIop);
1219
1220 vcvtFpUHFixedDCode = '''
1221 IntDoubleUnion cOp1;
1222 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
1223 VfpSavedState state = prepVfpFpscr(Fpscr);
1224 uint64_t mid = vfpFpDToFixed(cOp1.fp, false, true, imm);
1225 Fpscr = setVfpFpscr(Fpscr, state);
1226 FpDestP0.uw = mid;
1227 FpDestP1.uw = mid >> 32;
1228 '''
1229 vcvtFpUHFixedDIop = InstObjParams("vcvt", "VcvtFpUHFixedD",
1230 "VfpRegRegImmOp",
1231 { "code": vcvtFpUHFixedDCode,
1232 "predicate_test": predicateTest }, [])
1233 header_output += VfpRegRegImmOpDeclare.subst(vcvtFpUHFixedDIop);
1234 decoder_output += VfpRegRegImmOpConstructor.subst(vcvtFpUHFixedDIop);
1235 exec_output += PredOpExecute.subst(vcvtFpUHFixedDIop);
1236
1237 vcvtSHFixedFpSCode = '''
1238 VfpSavedState state = prepVfpFpscr(Fpscr);
1239 FpDest = vfpSFixedToFpS(FpOp1.sh, true, imm);
1240 Fpscr = setVfpFpscr(Fpscr, state);
1241 '''
1242 vcvtSHFixedFpSIop = InstObjParams("vcvt", "VcvtSHFixedFpS",
1243 "VfpRegRegImmOp",
1244 { "code": vcvtSHFixedFpSCode,
1245 "predicate_test": predicateTest }, [])
1246 header_output += VfpRegRegImmOpDeclare.subst(vcvtSHFixedFpSIop);
1247 decoder_output += VfpRegRegImmOpConstructor.subst(vcvtSHFixedFpSIop);
1248 exec_output += PredOpExecute.subst(vcvtSHFixedFpSIop);
1249
1250 vcvtSHFixedFpDCode = '''
1251 IntDoubleUnion cDest;
1252 uint64_t mid = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
1253 VfpSavedState state = prepVfpFpscr(Fpscr);
1254 cDest.fp = vfpSFixedToFpD(mid, true, imm);
1255 Fpscr = setVfpFpscr(Fpscr, state);
1256 FpDestP0.uw = cDest.bits;
1257 FpDestP1.uw = cDest.bits >> 32;
1258 '''
1259 vcvtSHFixedFpDIop = InstObjParams("vcvt", "VcvtSHFixedFpD",
1260 "VfpRegRegImmOp",
1261 { "code": vcvtSHFixedFpDCode,
1262 "predicate_test": predicateTest }, [])
1263 header_output += VfpRegRegImmOpDeclare.subst(vcvtSHFixedFpDIop);
1264 decoder_output += VfpRegRegImmOpConstructor.subst(vcvtSHFixedFpDIop);
1265 exec_output += PredOpExecute.subst(vcvtSHFixedFpDIop);
1266
1267 vcvtUHFixedFpSCode = '''
1268 VfpSavedState state = prepVfpFpscr(Fpscr);
1269 FpDest = vfpUFixedToFpS(FpOp1.uh, true, imm);
1270 Fpscr = setVfpFpscr(Fpscr, state);
1271 '''
1272 vcvtUHFixedFpSIop = InstObjParams("vcvt", "VcvtUHFixedFpS",
1273 "VfpRegRegImmOp",
1274 { "code": vcvtUHFixedFpSCode,
1275 "predicate_test": predicateTest }, [])
1276 header_output += VfpRegRegImmOpDeclare.subst(vcvtUHFixedFpSIop);
1277 decoder_output += VfpRegRegImmOpConstructor.subst(vcvtUHFixedFpSIop);
1278 exec_output += PredOpExecute.subst(vcvtUHFixedFpSIop);
1279
1280 vcvtUHFixedFpDCode = '''
1281 IntDoubleUnion cDest;
1282 uint64_t mid = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
1283 VfpSavedState state = prepVfpFpscr(Fpscr);
1284 cDest.fp = vfpUFixedToFpD(mid, true, imm);
1285 Fpscr = setVfpFpscr(Fpscr, state);
1286 FpDestP0.uw = cDest.bits;
1287 FpDestP1.uw = cDest.bits >> 32;
1288 '''
1289 vcvtUHFixedFpDIop = InstObjParams("vcvt", "VcvtUHFixedFpD",
1290 "VfpRegRegImmOp",
1291 { "code": vcvtUHFixedFpDCode,
1292 "predicate_test": predicateTest }, [])
1293 header_output += VfpRegRegImmOpDeclare.subst(vcvtUHFixedFpDIop);
1294 decoder_output += VfpRegRegImmOpConstructor.subst(vcvtUHFixedFpDIop);
1295 exec_output += PredOpExecute.subst(vcvtUHFixedFpDIop);
1296}};