1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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824 '''
825 vcvtSIntFpDIop = InstObjParams("vcvt", "VcvtSIntFpD", "VfpRegRegOp",
826 { "code": vcvtSIntFpDCode,
827 "predicate_test": predicateTest }, [])
828 header_output += VfpRegRegOpDeclare.subst(vcvtSIntFpDIop);
829 decoder_output += VfpRegRegOpConstructor.subst(vcvtSIntFpDIop);
830 exec_output += PredOpExecute.subst(vcvtSIntFpDIop);
831
832 vcvtFpUIntSCode = '''
833 VfpSavedState state = prepVfpFpscr(Fpscr);
834 FpDest.uw = FpOp1;
835 Fpscr = setVfpFpscr(Fpscr, state);
836 '''
837 vcvtFpUIntSIop = InstObjParams("vcvt", "VcvtFpUIntS", "VfpRegRegOp",
838 { "code": vcvtFpUIntSCode,
839 "predicate_test": predicateTest }, [])
840 header_output += VfpRegRegOpDeclare.subst(vcvtFpUIntSIop);
841 decoder_output += VfpRegRegOpConstructor.subst(vcvtFpUIntSIop);
842 exec_output += PredOpExecute.subst(vcvtFpUIntSIop);
843
844 vcvtFpUIntDCode = '''
845 IntDoubleUnion cOp1;
846 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
847 VfpSavedState state = prepVfpFpscr(Fpscr);
848 uint64_t result = cOp1.fp;
849 Fpscr = setVfpFpscr(Fpscr, state);
850 FpDestP0.uw = result;
851 '''
852 vcvtFpUIntDIop = InstObjParams("vcvt", "VcvtFpUIntD", "VfpRegRegOp",
853 { "code": vcvtFpUIntDCode,
854 "predicate_test": predicateTest }, [])
855 header_output += VfpRegRegOpDeclare.subst(vcvtFpUIntDIop);
856 decoder_output += VfpRegRegOpConstructor.subst(vcvtFpUIntDIop);
857 exec_output += PredOpExecute.subst(vcvtFpUIntDIop);
858
859 vcvtFpSIntSCode = '''
860 VfpSavedState state = prepVfpFpscr(Fpscr);
861 FpDest.sw = FpOp1;
862 Fpscr = setVfpFpscr(Fpscr, state);
863 '''
864 vcvtFpSIntSIop = InstObjParams("vcvt", "VcvtFpSIntS", "VfpRegRegOp",
865 { "code": vcvtFpSIntSCode,
866 "predicate_test": predicateTest }, [])
867 header_output += VfpRegRegOpDeclare.subst(vcvtFpSIntSIop);
868 decoder_output += VfpRegRegOpConstructor.subst(vcvtFpSIntSIop);
869 exec_output += PredOpExecute.subst(vcvtFpSIntSIop);
870
871 vcvtFpSIntDCode = '''
872 IntDoubleUnion cOp1;
873 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
874 VfpSavedState state = prepVfpFpscr(Fpscr);
875 int64_t result = cOp1.fp;
876 Fpscr = setVfpFpscr(Fpscr, state);
877 FpDestP0.uw = result;
878 '''
879 vcvtFpSIntDIop = InstObjParams("vcvt", "VcvtFpSIntD", "VfpRegRegOp",
880 { "code": vcvtFpSIntDCode,
881 "predicate_test": predicateTest }, [])
882 header_output += VfpRegRegOpDeclare.subst(vcvtFpSIntDIop);

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1057 { "code": vcvtFpUFixedDCode,
1058 "predicate_test": predicateTest }, [])
1059 header_output += VfpRegRegImmOpDeclare.subst(vcvtFpUFixedDIop);
1060 decoder_output += VfpRegRegImmOpConstructor.subst(vcvtFpUFixedDIop);
1061 exec_output += PredOpExecute.subst(vcvtFpUFixedDIop);
1062
1063 vcvtSFixedFpSCode = '''
1064 VfpSavedState state = prepVfpFpscr(Fpscr);
1065 FpDest = vfpSFixedToFpS(FpOp1.sw, true, imm);
1066 Fpscr = setVfpFpscr(Fpscr, state);
1067 '''
1068 vcvtSFixedFpSIop = InstObjParams("vcvt", "VcvtSFixedFpS", "VfpRegRegImmOp",
1069 { "code": vcvtSFixedFpSCode,
1070 "predicate_test": predicateTest }, [])
1071 header_output += VfpRegRegImmOpDeclare.subst(vcvtSFixedFpSIop);
1072 decoder_output += VfpRegRegImmOpConstructor.subst(vcvtSFixedFpSIop);
1073 exec_output += PredOpExecute.subst(vcvtSFixedFpSIop);
1074
1075 vcvtSFixedFpDCode = '''
1076 IntDoubleUnion cDest;
1077 uint64_t mid = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
1078 VfpSavedState state = prepVfpFpscr(Fpscr);
1079 cDest.fp = vfpSFixedToFpD(mid, true, imm);
1080 Fpscr = setVfpFpscr(Fpscr, state);
1081 FpDestP0.uw = cDest.bits;
1082 FpDestP1.uw = cDest.bits >> 32;
1083 '''
1084 vcvtSFixedFpDIop = InstObjParams("vcvt", "VcvtSFixedFpD", "VfpRegRegImmOp",
1085 { "code": vcvtSFixedFpDCode,
1086 "predicate_test": predicateTest }, [])
1087 header_output += VfpRegRegImmOpDeclare.subst(vcvtSFixedFpDIop);

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