1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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381 header_output = ""
382 decoder_output = ""
383 exec_output = ""
384
385 vmulSCode = '''
386 vfpFlushToZero(Fpscr, FpOp1, FpOp2);
387 VfpSavedState state = prepVfpFpscr(Fpscr);
388 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
389 FpDest = fixDest(Fpscr, FpOp1 * FpOp2, FpOp1, FpOp2);
390 __asm__ __volatile__("" :: "m" (FpDest));
391 Fpscr = setVfpFpscr(Fpscr, state);
392 if ((isinf(FpOp1) && FpOp2 == 0) || (isinf(FpOp2) && FpOp1 == 0)) {
393 FpDest = NAN;
394 }
395 '''
396 vmulSIop = InstObjParams("vmuls", "VmulS", "VfpRegRegRegOp",
397 { "code": vmulSCode,

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402
403 vmulDCode = '''
404 IntDoubleUnion cOp1, cOp2, cDest;
405 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
406 cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32));
407 vfpFlushToZero(Fpscr, cOp1.fp, cOp2.fp);
408 VfpSavedState state = prepVfpFpscr(Fpscr);
409 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp));
410 cDest.fp = fixDest(Fpscr, cOp1.fp * cOp2.fp, cOp1.fp, cOp2.fp);
411 __asm__ __volatile__("" :: "m" (cDest.fp));
412 Fpscr = setVfpFpscr(Fpscr, state);
413 if ((isinf(cOp1.fp) && cOp2.fp == 0) ||
414 (isinf(cOp2.fp) && cOp1.fp == 0)) {
415 cDest.fp = NAN;
416 }
417 FpDestP0.uw = cDest.bits;
418 FpDestP1.uw = cDest.bits >> 32;

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471 header_output += VfpRegRegOpDeclare.subst(vabsDIop);
472 decoder_output += VfpRegRegOpConstructor.subst(vabsDIop);
473 exec_output += PredOpExecute.subst(vabsDIop);
474
475 vaddSCode = '''
476 vfpFlushToZero(Fpscr, FpOp1, FpOp2);
477 VfpSavedState state = prepVfpFpscr(Fpscr);
478 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
479 FpDest = fixDest(Fpscr, FpOp1 + FpOp2, FpOp1, FpOp2);
480 __asm__ __volatile__("" :: "m" (FpDest));
481 Fpscr = setVfpFpscr(Fpscr, state);
482 '''
483 vaddSIop = InstObjParams("vadds", "VaddS", "VfpRegRegRegOp",
484 { "code": vaddSCode,
485 "predicate_test": predicateTest }, [])
486 header_output += VfpRegRegRegOpDeclare.subst(vaddSIop);
487 decoder_output += VfpRegRegRegOpConstructor.subst(vaddSIop);
488 exec_output += PredOpExecute.subst(vaddSIop);
489
490 vaddDCode = '''
491 IntDoubleUnion cOp1, cOp2, cDest;
492 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
493 cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32));
494 DPRINTFN("cOp1.bits = %#x, cOp1.fp = %f.\\n", cOp1.bits, cOp1.fp);
495 DPRINTFN("cOp2.bits = %#x, cOp2.fp = %f.\\n", cOp2.bits, cOp2.fp);
496 vfpFlushToZero(Fpscr, cOp1.fp, cOp2.fp);
497 VfpSavedState state = prepVfpFpscr(Fpscr);
498 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp));
499 cDest.fp = fixDest(Fpscr, cOp1.fp + cOp2.fp, cOp1.fp, cOp2.fp);
500 DPRINTFN("cDest.bits = %#x, cDest.fp = %f.\\n", cDest.bits, cDest.fp);
501 __asm__ __volatile__("" :: "m" (cDest.fp));
502 Fpscr = setVfpFpscr(Fpscr, state);
503 FpDestP0.uw = cDest.bits;
504 FpDestP1.uw = cDest.bits >> 32;
505 '''
506 vaddDIop = InstObjParams("vaddd", "VaddD", "VfpRegRegRegOp",
507 { "code": vaddDCode,
508 "predicate_test": predicateTest }, [])
509 header_output += VfpRegRegRegOpDeclare.subst(vaddDIop);
510 decoder_output += VfpRegRegRegOpConstructor.subst(vaddDIop);
511 exec_output += PredOpExecute.subst(vaddDIop);
512
513 vsubSCode = '''
514 vfpFlushToZero(Fpscr, FpOp1, FpOp2);
515 VfpSavedState state = prepVfpFpscr(Fpscr);
516 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
517 FpDest = fixDest(Fpscr, FpOp1 - FpOp2, FpOp1, FpOp2);
518 __asm__ __volatile__("" :: "m" (FpDest));
519 Fpscr = setVfpFpscr(Fpscr, state)
520 '''
521 vsubSIop = InstObjParams("vsubs", "VsubS", "VfpRegRegRegOp",
522 { "code": vsubSCode,
523 "predicate_test": predicateTest }, [])
524 header_output += VfpRegRegRegOpDeclare.subst(vsubSIop);
525 decoder_output += VfpRegRegRegOpConstructor.subst(vsubSIop);
526 exec_output += PredOpExecute.subst(vsubSIop);
527
528 vsubDCode = '''
529 IntDoubleUnion cOp1, cOp2, cDest;
530 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
531 cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32));
532 vfpFlushToZero(Fpscr, cOp1.fp, cOp2.fp);
533 VfpSavedState state = prepVfpFpscr(Fpscr);
534 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp));
535 cDest.fp = fixDest(Fpscr, cOp1.fp - cOp2.fp, cOp1.fp, cOp2.fp);
536 __asm__ __volatile__("" :: "m" (cDest.fp));
537 Fpscr = setVfpFpscr(Fpscr, state);
538 FpDestP0.uw = cDest.bits;
539 FpDestP1.uw = cDest.bits >> 32;
540 '''
541 vsubDIop = InstObjParams("vsubd", "VsubD", "VfpRegRegRegOp",
542 { "code": vsubDCode,
543 "predicate_test": predicateTest }, [])
544 header_output += VfpRegRegRegOpDeclare.subst(vsubDIop);
545 decoder_output += VfpRegRegRegOpConstructor.subst(vsubDIop);
546 exec_output += PredOpExecute.subst(vsubDIop);
547
548 vdivSCode = '''
549 vfpFlushToZero(Fpscr, FpOp1, FpOp2);
550 VfpSavedState state = prepVfpFpscr(Fpscr);
551 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
552 FpDest = fixDest(Fpscr, FpOp1 / FpOp2, FpOp1, FpOp2);
553 __asm__ __volatile__("" :: "m" (FpDest));
554 Fpscr = setVfpFpscr(Fpscr, state);
555 '''
556 vdivSIop = InstObjParams("vdivs", "VdivS", "VfpRegRegRegOp",
557 { "code": vdivSCode,
558 "predicate_test": predicateTest }, [])
559 header_output += VfpRegRegRegOpDeclare.subst(vdivSIop);
560 decoder_output += VfpRegRegRegOpConstructor.subst(vdivSIop);
561 exec_output += PredOpExecute.subst(vdivSIop);
562
563 vdivDCode = '''
564 IntDoubleUnion cOp1, cOp2, cDest;
565 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
566 cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32));
567 vfpFlushToZero(Fpscr, cOp1.fp, cOp2.fp);
568 VfpSavedState state = prepVfpFpscr(Fpscr);
569 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cDest.fp));
570 cDest.fp = fixDest(Fpscr, cOp1.fp / cOp2.fp, cOp1.fp, cOp2.fp);
571 __asm__ __volatile__("" :: "m" (cDest.fp));
572 Fpscr = setVfpFpscr(Fpscr, state);
573 FpDestP0.uw = cDest.bits;
574 FpDestP1.uw = cDest.bits >> 32;
575 '''
576 vdivDIop = InstObjParams("vdivd", "VdivD", "VfpRegRegRegOp",
577 { "code": vdivDCode,
578 "predicate_test": predicateTest }, [])

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626 header_output = ""
627 decoder_output = ""
628 exec_output = ""
629
630 vmlaSCode = '''
631 vfpFlushToZero(Fpscr, FpOp1, FpOp2);
632 VfpSavedState state = prepVfpFpscr(Fpscr);
633 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
634 float mid = fixDest(Fpscr, FpOp1 * FpOp2, FpOp1, FpOp2);
635 if ((isinf(FpOp1) && FpOp2 == 0) || (isinf(FpOp2) && FpOp1 == 0)) {
636 mid = NAN;
637 }
638 vfpFlushToZero(Fpscr, FpDest, mid);
639 FpDest = fixDest(Fpscr, FpDest + mid, FpDest, mid);
640 __asm__ __volatile__("" :: "m" (FpDest));
641 Fpscr = setVfpFpscr(Fpscr, state);
642 '''
643 vmlaSIop = InstObjParams("vmlas", "VmlaS", "VfpRegRegRegOp",
644 { "code": vmlaSCode,
645 "predicate_test": predicateTest }, [])
646 header_output += VfpRegRegRegOpDeclare.subst(vmlaSIop);
647 decoder_output += VfpRegRegRegOpConstructor.subst(vmlaSIop);
648 exec_output += PredOpExecute.subst(vmlaSIop);
649
650 vmlaDCode = '''
651 IntDoubleUnion cOp1, cOp2, cDest;
652 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
653 cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32));
654 cDest.bits = ((uint64_t)FpDestP0.uw | ((uint64_t)FpDestP1.uw << 32));
655 vfpFlushToZero(Fpscr, cOp1.fp, cOp2.fp);
656 VfpSavedState state = prepVfpFpscr(Fpscr);
657 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp));
658 double mid = fixDest(Fpscr, cOp1.fp * cOp2.fp, cOp1.fp, cOp2.fp);
659 if ((isinf(cOp1.fp) && cOp2.fp == 0) ||
660 (isinf(cOp2.fp) && cOp1.fp == 0)) {
661 mid = NAN;
662 }
663 vfpFlushToZero(Fpscr, cDest.fp, mid);
664 cDest.fp = fixDest(Fpscr, cDest.fp + mid, cDest.fp, mid);
665 __asm__ __volatile__("" :: "m" (cDest.fp));
666 Fpscr = setVfpFpscr(Fpscr, state);
667 FpDestP0.uw = cDest.bits;
668 FpDestP1.uw = cDest.bits >> 32;
669 '''
670 vmlaDIop = InstObjParams("vmlad", "VmlaD", "VfpRegRegRegOp",
671 { "code": vmlaDCode,
672 "predicate_test": predicateTest }, [])
673 header_output += VfpRegRegRegOpDeclare.subst(vmlaDIop);
674 decoder_output += VfpRegRegRegOpConstructor.subst(vmlaDIop);
675 exec_output += PredOpExecute.subst(vmlaDIop);
676
677 vmlsSCode = '''
678 vfpFlushToZero(Fpscr, FpOp1, FpOp2);
679 VfpSavedState state = prepVfpFpscr(Fpscr);
680 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
681 float mid = fixDest(Fpscr, FpOp1 * FpOp2, FpOp1, FpOp2);
682 if ((isinf(FpOp1) && FpOp2 == 0) || (isinf(FpOp2) && FpOp1 == 0)) {
683 mid = NAN;
684 }
685 vfpFlushToZero(Fpscr, FpDest, mid);
686 FpDest = fixDest(Fpscr, FpDest - mid, FpDest, mid);
687 __asm__ __volatile__("" :: "m" (FpDest));
688 Fpscr = setVfpFpscr(Fpscr, state);
689 '''
690 vmlsSIop = InstObjParams("vmlss", "VmlsS", "VfpRegRegRegOp",
691 { "code": vmlsSCode,
692 "predicate_test": predicateTest }, [])
693 header_output += VfpRegRegRegOpDeclare.subst(vmlsSIop);
694 decoder_output += VfpRegRegRegOpConstructor.subst(vmlsSIop);
695 exec_output += PredOpExecute.subst(vmlsSIop);
696
697 vmlsDCode = '''
698 IntDoubleUnion cOp1, cOp2, cDest;
699 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
700 cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32));
701 cDest.bits = ((uint64_t)FpDestP0.uw | ((uint64_t)FpDestP1.uw << 32));
702 vfpFlushToZero(Fpscr, cOp1.fp, cOp2.fp);
703 VfpSavedState state = prepVfpFpscr(Fpscr);
704 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp));
705 double mid = fixDest(Fpscr, cOp1.fp * cOp2.fp, cOp1.fp, cOp2.fp);
706 if ((isinf(cOp1.fp) && cOp2.fp == 0) ||
707 (isinf(cOp2.fp) && cOp1.fp == 0)) {
708 mid = NAN;
709 }
710 cDest.fp = fixDest(Fpscr, cDest.fp - mid, cDest.fp, mid);
711 vfpFlushToZero(Fpscr, cDest.fp, mid);
712 __asm__ __volatile__("" :: "m" (cDest.fp));
713 Fpscr = setVfpFpscr(Fpscr, state);
714 FpDestP0.uw = cDest.bits;
715 FpDestP1.uw = cDest.bits >> 32;
716 '''
717 vmlsDIop = InstObjParams("vmlsd", "VmlsD", "VfpRegRegRegOp",
718 { "code": vmlsDCode,
719 "predicate_test": predicateTest }, [])
720 header_output += VfpRegRegRegOpDeclare.subst(vmlsDIop);
721 decoder_output += VfpRegRegRegOpConstructor.subst(vmlsDIop);
722 exec_output += PredOpExecute.subst(vmlsDIop);
723
724 vnmlaSCode = '''
725 vfpFlushToZero(Fpscr, FpOp1, FpOp2);
726 VfpSavedState state = prepVfpFpscr(Fpscr);
727 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
728 float mid = fixDest(Fpscr, FpOp1 * FpOp2, FpOp1, FpOp2);
729 if ((isinf(FpOp1) && FpOp2 == 0) || (isinf(FpOp2) && FpOp1 == 0)) {
730 mid = NAN;
731 }
732 vfpFlushToZero(Fpscr, FpDest, mid);
733 FpDest = fixDest(Fpscr, -FpDest - mid, FpDest, mid);
734 __asm__ __volatile__("" :: "m" (FpDest));
735 Fpscr = setVfpFpscr(Fpscr, state);
736 '''
737 vnmlaSIop = InstObjParams("vnmlas", "VnmlaS", "VfpRegRegRegOp",
738 { "code": vnmlaSCode,
739 "predicate_test": predicateTest }, [])
740 header_output += VfpRegRegRegOpDeclare.subst(vnmlaSIop);
741 decoder_output += VfpRegRegRegOpConstructor.subst(vnmlaSIop);
742 exec_output += PredOpExecute.subst(vnmlaSIop);
743
744 vnmlaDCode = '''
745 IntDoubleUnion cOp1, cOp2, cDest;
746 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
747 cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32));
748 cDest.bits = ((uint64_t)FpDestP0.uw | ((uint64_t)FpDestP1.uw << 32));
749 vfpFlushToZero(Fpscr, cOp1.fp, cOp2.fp);
750 VfpSavedState state = prepVfpFpscr(Fpscr);
751 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp));
752 double mid = fixDest(Fpscr, cOp1.fp * cOp2.fp, cOp1.fp, cOp2.fp);
753 if ((isinf(cOp1.fp) && cOp2.fp == 0) ||
754 (isinf(cOp2.fp) && cOp1.fp == 0)) {
755 mid = NAN;
756 }
757 vfpFlushToZero(Fpscr, cDest.fp, mid);
758 cDest.fp = fixDest(Fpscr, -cDest.fp - mid, cDest.fp, mid);
759 __asm__ __volatile__("" :: "m" (cDest.fp));
760 Fpscr = setVfpFpscr(Fpscr, state);
761 FpDestP0.uw = cDest.bits;
762 FpDestP1.uw = cDest.bits >> 32;
763 '''
764 vnmlaDIop = InstObjParams("vnmlad", "VnmlaD", "VfpRegRegRegOp",
765 { "code": vnmlaDCode,
766 "predicate_test": predicateTest }, [])
767 header_output += VfpRegRegRegOpDeclare.subst(vnmlaDIop);
768 decoder_output += VfpRegRegRegOpConstructor.subst(vnmlaDIop);
769 exec_output += PredOpExecute.subst(vnmlaDIop);
770
771 vnmlsSCode = '''
772 vfpFlushToZero(Fpscr, FpOp1, FpOp2);
773 VfpSavedState state = prepVfpFpscr(Fpscr);
774 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
775 float mid = fixDest(Fpscr, FpOp1 * FpOp2, FpOp1, FpOp2);
776 if ((isinf(FpOp1) && FpOp2 == 0) || (isinf(FpOp2) && FpOp1 == 0)) {
777 mid = NAN;
778 }
779 vfpFlushToZero(Fpscr, FpDest, mid);
780 FpDest = fixDest(Fpscr, -FpDest + mid, FpDest, mid);
781 __asm__ __volatile__("" :: "m" (FpDest));
782 Fpscr = setVfpFpscr(Fpscr, state);
783 '''
784 vnmlsSIop = InstObjParams("vnmlss", "VnmlsS", "VfpRegRegRegOp",
785 { "code": vnmlsSCode,
786 "predicate_test": predicateTest }, [])
787 header_output += VfpRegRegRegOpDeclare.subst(vnmlsSIop);
788 decoder_output += VfpRegRegRegOpConstructor.subst(vnmlsSIop);
789 exec_output += PredOpExecute.subst(vnmlsSIop);
790
791 vnmlsDCode = '''
792 IntDoubleUnion cOp1, cOp2, cDest;
793 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
794 cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32));
795 cDest.bits = ((uint64_t)FpDestP0.uw | ((uint64_t)FpDestP1.uw << 32));
796 vfpFlushToZero(Fpscr, cOp1.fp, cOp2.fp);
797 VfpSavedState state = prepVfpFpscr(Fpscr);
798 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp));
799 double mid = fixDest(Fpscr, cOp1.fp * cOp2.fp, cOp1.fp, cOp2.fp);
800 if ((isinf(cOp1.fp) && cOp2.fp == 0) ||
801 (isinf(cOp2.fp) && cOp1.fp == 0)) {
802 mid = NAN;
803 }
804 vfpFlushToZero(Fpscr, cDest.fp, mid);
805 cDest.fp = fixDest(Fpscr, -cDest.fp + mid, cDest.fp, mid);
806 __asm__ __volatile__("" :: "m" (cDest.fp));
807 Fpscr = setVfpFpscr(Fpscr, state);
808 FpDestP0.uw = cDest.bits;
809 FpDestP1.uw = cDest.bits >> 32;
810 '''
811 vnmlsDIop = InstObjParams("vnmlsd", "VnmlsD", "VfpRegRegRegOp",
812 { "code": vnmlsDCode,
813 "predicate_test": predicateTest }, [])
814 header_output += VfpRegRegRegOpDeclare.subst(vnmlsDIop);
815 decoder_output += VfpRegRegRegOpConstructor.subst(vnmlsDIop);
816 exec_output += PredOpExecute.subst(vnmlsDIop);
817
818 vnmulSCode = '''
819 vfpFlushToZero(Fpscr, FpOp1, FpOp2);
820 VfpSavedState state = prepVfpFpscr(Fpscr);
821 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
822 float mid = fixDest(Fpscr, FpOp1 * FpOp2, FpOp1, FpOp2);
823 if ((isinf(FpOp1) && FpOp2 == 0) || (isinf(FpOp2) && FpOp1 == 0)) {
824 mid = NAN;
825 }
826 FpDest = -mid;
827 __asm__ __volatile__("" :: "m" (FpDest));
828 Fpscr = setVfpFpscr(Fpscr, state);
829 '''
830 vnmulSIop = InstObjParams("vnmuls", "VnmulS", "VfpRegRegRegOp",

--- 6 unchanged lines hidden (view full) ---

837 vnmulDCode = '''
838 IntDoubleUnion cOp1, cOp2, cDest;
839 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
840 cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32));
841 cDest.bits = ((uint64_t)FpDestP0.uw | ((uint64_t)FpDestP1.uw << 32));
842 vfpFlushToZero(Fpscr, cOp1.fp, cOp2.fp);
843 VfpSavedState state = prepVfpFpscr(Fpscr);
844 __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp));
845 double mid = fixDest(Fpscr, cOp1.fp * cOp2.fp, cOp1.fp, cOp2.fp);
846 if ((isinf(cOp1.fp) && cOp2.fp == 0) ||
847 (isinf(cOp2.fp) && cOp1.fp == 0)) {
848 mid = NAN;
849 }
850 cDest.fp = -mid;
851 __asm__ __volatile__("" :: "m" (cDest.fp));
852 Fpscr = setVfpFpscr(Fpscr, state);
853 FpDestP0.uw = cDest.bits;

--- 617 unchanged lines hidden ---