div.isa (8782:10c9297e14d5) | div.isa (10037:5cac77888310) |
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1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating --- 26 unchanged lines hidden (view full) --- 35// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 36// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 37// 38// Authors: Gabe Black 39 40let {{ 41 sdivCode = ''' 42 if (Op2_sw == 0) { | 1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating --- 26 unchanged lines hidden (view full) --- 35// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 36// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 37// 38// Authors: Gabe Black 39 40let {{ 41 sdivCode = ''' 42 if (Op2_sw == 0) { |
43 if (((SCTLR)Sctlr).dz) { 44 if (FullSystem) 45 return new UndefinedInstruction; 46 else 47 return new UndefinedInstruction(false, mnemonic); 48 } | |
49 Dest_sw = 0; 50 } else if (Op1_sw == INT_MIN && Op2_sw == -1) { 51 Dest_sw = INT_MIN; 52 } else { 53 Dest_sw = Op1_sw / Op2_sw; 54 } 55 ''' 56 sdivIop = InstObjParams("sdiv", "Sdiv", "RegRegRegOp", 57 { "code": sdivCode, 58 "predicate_test": predicateTest, 59 "op_class": "IntDivOp"}, []) 60 header_output = RegRegRegOpDeclare.subst(sdivIop) 61 decoder_output = RegRegRegOpConstructor.subst(sdivIop) 62 exec_output = PredOpExecute.subst(sdivIop) 63 64 udivCode = ''' 65 if (Op2_uw == 0) { | 43 Dest_sw = 0; 44 } else if (Op1_sw == INT_MIN && Op2_sw == -1) { 45 Dest_sw = INT_MIN; 46 } else { 47 Dest_sw = Op1_sw / Op2_sw; 48 } 49 ''' 50 sdivIop = InstObjParams("sdiv", "Sdiv", "RegRegRegOp", 51 { "code": sdivCode, 52 "predicate_test": predicateTest, 53 "op_class": "IntDivOp"}, []) 54 header_output = RegRegRegOpDeclare.subst(sdivIop) 55 decoder_output = RegRegRegOpConstructor.subst(sdivIop) 56 exec_output = PredOpExecute.subst(sdivIop) 57 58 udivCode = ''' 59 if (Op2_uw == 0) { |
66 if (((SCTLR)Sctlr).dz) { 67 if (FullSystem) 68 return new UndefinedInstruction; 69 else 70 return new UndefinedInstruction(false, mnemonic); 71 } | |
72 Dest_uw = 0; 73 } else { 74 Dest_uw = Op1_uw / Op2_uw; 75 } 76 ''' 77 udivIop = InstObjParams("udiv", "Udiv", "RegRegRegOp", 78 { "code": udivCode, 79 "predicate_test": predicateTest, 80 "op_class": "IntDivOp"}, []) 81 header_output += RegRegRegOpDeclare.subst(udivIop) 82 decoder_output += RegRegRegOpConstructor.subst(udivIop) 83 exec_output += PredOpExecute.subst(udivIop) 84}}; | 60 Dest_uw = 0; 61 } else { 62 Dest_uw = Op1_uw / Op2_uw; 63 } 64 ''' 65 udivIop = InstObjParams("udiv", "Udiv", "RegRegRegOp", 66 { "code": udivCode, 67 "predicate_test": predicateTest, 68 "op_class": "IntDivOp"}, []) 69 header_output += RegRegRegOpDeclare.subst(udivIop) 70 decoder_output += RegRegRegOpConstructor.subst(udivIop) 71 exec_output += PredOpExecute.subst(udivIop) 72}}; |