div.isa (8588:ef28ed90449d) | div.isa (8782:10c9297e14d5) |
---|---|
1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating --- 27 unchanged lines hidden (view full) --- 36// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 37// 38// Authors: Gabe Black 39 40let {{ 41 sdivCode = ''' 42 if (Op2_sw == 0) { 43 if (((SCTLR)Sctlr).dz) { | 1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating --- 27 unchanged lines hidden (view full) --- 36// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 37// 38// Authors: Gabe Black 39 40let {{ 41 sdivCode = ''' 42 if (Op2_sw == 0) { 43 if (((SCTLR)Sctlr).dz) { |
44#if FULL_SYSTEM 45 return new UndefinedInstruction; 46#else 47 return new UndefinedInstruction(false, mnemonic); 48#endif | 44 if (FullSystem) 45 return new UndefinedInstruction; 46 else 47 return new UndefinedInstruction(false, mnemonic); |
49 } 50 Dest_sw = 0; 51 } else if (Op1_sw == INT_MIN && Op2_sw == -1) { 52 Dest_sw = INT_MIN; 53 } else { 54 Dest_sw = Op1_sw / Op2_sw; 55 } 56 ''' 57 sdivIop = InstObjParams("sdiv", "Sdiv", "RegRegRegOp", 58 { "code": sdivCode, 59 "predicate_test": predicateTest, 60 "op_class": "IntDivOp"}, []) 61 header_output = RegRegRegOpDeclare.subst(sdivIop) 62 decoder_output = RegRegRegOpConstructor.subst(sdivIop) 63 exec_output = PredOpExecute.subst(sdivIop) 64 65 udivCode = ''' 66 if (Op2_uw == 0) { 67 if (((SCTLR)Sctlr).dz) { | 48 } 49 Dest_sw = 0; 50 } else if (Op1_sw == INT_MIN && Op2_sw == -1) { 51 Dest_sw = INT_MIN; 52 } else { 53 Dest_sw = Op1_sw / Op2_sw; 54 } 55 ''' 56 sdivIop = InstObjParams("sdiv", "Sdiv", "RegRegRegOp", 57 { "code": sdivCode, 58 "predicate_test": predicateTest, 59 "op_class": "IntDivOp"}, []) 60 header_output = RegRegRegOpDeclare.subst(sdivIop) 61 decoder_output = RegRegRegOpConstructor.subst(sdivIop) 62 exec_output = PredOpExecute.subst(sdivIop) 63 64 udivCode = ''' 65 if (Op2_uw == 0) { 66 if (((SCTLR)Sctlr).dz) { |
68#if FULL_SYSTEM 69 return new UndefinedInstruction; 70#else 71 return new UndefinedInstruction(false, mnemonic); 72#endif | 67 if (FullSystem) 68 return new UndefinedInstruction; 69 else 70 return new UndefinedInstruction(false, mnemonic); |
73 } 74 Dest_uw = 0; 75 } else { 76 Dest_uw = Op1_uw / Op2_uw; 77 } 78 ''' 79 udivIop = InstObjParams("udiv", "Udiv", "RegRegRegOp", 80 { "code": udivCode, 81 "predicate_test": predicateTest, 82 "op_class": "IntDivOp"}, []) 83 header_output += RegRegRegOpDeclare.subst(udivIop) 84 decoder_output += RegRegRegOpConstructor.subst(udivIop) 85 exec_output += PredOpExecute.subst(udivIop) 86}}; | 71 } 72 Dest_uw = 0; 73 } else { 74 Dest_uw = Op1_uw / Op2_uw; 75 } 76 ''' 77 udivIop = InstObjParams("udiv", "Udiv", "RegRegRegOp", 78 { "code": udivCode, 79 "predicate_test": predicateTest, 80 "op_class": "IntDivOp"}, []) 81 header_output += RegRegRegOpDeclare.subst(udivIop) 82 decoder_output += RegRegRegOpConstructor.subst(udivIop) 83 exec_output += PredOpExecute.subst(udivIop) 84}}; |