div.isa (7760:e93e7e0caae1) | div.isa (8588:ef28ed90449d) |
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1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating --- 25 unchanged lines hidden (view full) --- 34// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 35// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 36// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 37// 38// Authors: Gabe Black 39 40let {{ 41 sdivCode = ''' | 1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating --- 25 unchanged lines hidden (view full) --- 34// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 35// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 36// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 37// 38// Authors: Gabe Black 39 40let {{ 41 sdivCode = ''' |
42 if (Op2.sw == 0) { | 42 if (Op2_sw == 0) { |
43 if (((SCTLR)Sctlr).dz) { 44#if FULL_SYSTEM 45 return new UndefinedInstruction; 46#else 47 return new UndefinedInstruction(false, mnemonic); 48#endif 49 } | 43 if (((SCTLR)Sctlr).dz) { 44#if FULL_SYSTEM 45 return new UndefinedInstruction; 46#else 47 return new UndefinedInstruction(false, mnemonic); 48#endif 49 } |
50 Dest.sw = 0; 51 } else if (Op1.sw == INT_MIN && Op2.sw == -1) { 52 Dest.sw = INT_MIN; | 50 Dest_sw = 0; 51 } else if (Op1_sw == INT_MIN && Op2_sw == -1) { 52 Dest_sw = INT_MIN; |
53 } else { | 53 } else { |
54 Dest.sw = Op1.sw / Op2.sw; | 54 Dest_sw = Op1_sw / Op2_sw; |
55 } 56 ''' 57 sdivIop = InstObjParams("sdiv", "Sdiv", "RegRegRegOp", 58 { "code": sdivCode, 59 "predicate_test": predicateTest, 60 "op_class": "IntDivOp"}, []) 61 header_output = RegRegRegOpDeclare.subst(sdivIop) 62 decoder_output = RegRegRegOpConstructor.subst(sdivIop) 63 exec_output = PredOpExecute.subst(sdivIop) 64 65 udivCode = ''' | 55 } 56 ''' 57 sdivIop = InstObjParams("sdiv", "Sdiv", "RegRegRegOp", 58 { "code": sdivCode, 59 "predicate_test": predicateTest, 60 "op_class": "IntDivOp"}, []) 61 header_output = RegRegRegOpDeclare.subst(sdivIop) 62 decoder_output = RegRegRegOpConstructor.subst(sdivIop) 63 exec_output = PredOpExecute.subst(sdivIop) 64 65 udivCode = ''' |
66 if (Op2.uw == 0) { | 66 if (Op2_uw == 0) { |
67 if (((SCTLR)Sctlr).dz) { 68#if FULL_SYSTEM 69 return new UndefinedInstruction; 70#else 71 return new UndefinedInstruction(false, mnemonic); 72#endif 73 } | 67 if (((SCTLR)Sctlr).dz) { 68#if FULL_SYSTEM 69 return new UndefinedInstruction; 70#else 71 return new UndefinedInstruction(false, mnemonic); 72#endif 73 } |
74 Dest.uw = 0; | 74 Dest_uw = 0; |
75 } else { | 75 } else { |
76 Dest.uw = Op1.uw / Op2.uw; | 76 Dest_uw = Op1_uw / Op2_uw; |
77 } 78 ''' 79 udivIop = InstObjParams("udiv", "Udiv", "RegRegRegOp", 80 { "code": udivCode, 81 "predicate_test": predicateTest, 82 "op_class": "IntDivOp"}, []) 83 header_output += RegRegRegOpDeclare.subst(udivIop) 84 decoder_output += RegRegRegOpConstructor.subst(udivIop) 85 exec_output += PredOpExecute.subst(udivIop) 86}}; | 77 } 78 ''' 79 udivIop = InstObjParams("udiv", "Udiv", "RegRegRegOp", 80 { "code": udivCode, 81 "predicate_test": predicateTest, 82 "op_class": "IntDivOp"}, []) 83 header_output += RegRegRegOpDeclare.subst(udivIop) 84 decoder_output += RegRegRegOpConstructor.subst(udivIop) 85 exec_output += PredOpExecute.subst(udivIop) 86}}; |