1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 42 unchanged lines hidden (view full) ---

51 } else if (Op1.sw == INT_MIN && Op2.sw == -1) {
52 Dest.sw = INT_MIN;
53 } else {
54 Dest.sw = Op1.sw / Op2.sw;
55 }
56 '''
57 sdivIop = InstObjParams("sdiv", "Sdiv", "RegRegRegOp",
58 { "code": sdivCode,
59 "predicate_test": predicateTest }, [])
60 header_output = RegRegRegOpDeclare.subst(sdivIop)
61 decoder_output = RegRegRegOpConstructor.subst(sdivIop)
62 exec_output = PredOpExecute.subst(sdivIop)
63
64 udivCode = '''
65 if (Op2.uw == 0) {
66 if (((SCTLR)Sctlr).dz) {
67#if FULL_SYSTEM

--- 4 unchanged lines hidden (view full) ---

72 }
73 Dest.uw = 0;
74 } else {
75 Dest.uw = Op1.uw / Op2.uw;
76 }
77 '''
78 udivIop = InstObjParams("udiv", "Udiv", "RegRegRegOp",
79 { "code": udivCode,
80 "predicate_test": predicateTest }, [])
81 header_output += RegRegRegOpDeclare.subst(udivIop)
82 decoder_output += RegRegRegOpConstructor.subst(udivIop)
83 exec_output += PredOpExecute.subst(udivIop)
84}};